NCP5316_技术文档

NCP5316

Four/Five/Six−Phase

Buck CPU Controller

The NCP5316 provides full−featured and flexible control for the

latest high−performance CPUs. The IC can be programmed as a four−,

five− or six−phase buck controller, and the per−phase switching

frequency can be as high as 1.0 MHz. Combined with external gate

drivers and power components, the controller implements a compact,

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MARKING

DIAGRAMS

highly integrated multi−phase buck converter.

2

Enhanced V

control inherently compensates for variations in

48

both line and load, and achieves current sharing between phases. This

control scheme provides fast transient response, reducing the need for

large banks of output capacitors and higher switching frequency.

The controller meets VR(M)10.x specifications with all the required

functions and protection features.

1

NCP5316

AWLYYWW

48−PIN QFN, 7 y 7

MN SUFFIX

Features

CASE 485K

(Bottom View)

• Switching Regulator Controller

♦ Programmable 4/5/6 Phase Operation

♦ Lossless Current Sensing

♦ Programmable Up to 1.0 MHz Switching Frequency Per Phase

♦ 0 to 100% Adjustment of Duty Cycle

♦ Programmable Adaptive Voltage Positioning Reduces Output

Capacitor Requirements

NCP5316

AWLYYWW

48

1

LQFP−48

FT SUFFIX

CASE 932

♦ Programmable Soft Start

• Current Sharing

A

= Assembly Location

♦ Differential Current Sense Pins for Each Phase

♦ Current Sharing Within 10% Between Phases

WL = Wafer Lot

YY = Year

WW = Work Week

• Protection Features

♦ Programmable Pulse−by−Pulse Current Limit for Each Phase

♦ “111110” and “111111” DAC Code Fault

♦ Latching Off Overvoltage Protection

♦ Programmable Latch Overcurrent Protection

♦ Undervoltage Lockout

ORDERING INFORMATION

†

Device

Package

Shipping

NCP5316MNR2

NCP5316FTR2

*7 × 7 mm

2000 Tape & Reel

48−Pin QFN*

LQFP−48*

♦ Reference Undervoltage Lockout

♦ MOSFET Driver Control through Driver−On Signal

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• System Power Management

♦ 6−Bit DAC with 0.5% Tolerance

♦ Programmable Lower Power Good Threshold

♦ Power Good Output

♦ External Enable Control

♦ 3.3 V Reference Voltage Output

Semiconductor Components Industries, LLC, 2004

1

Publication Order Number

February, 2004 − Rev. 9

NCP5316/D

NCP5316

48 47 46 45 44 43 42 41 40 39 38 37

V

1

2

3

4

5

6

7

8

9

36 CS1P

ID5

ID0

ID1

ID2

ID3

ID4

35

34

R

OSC

CC

V

33 GATE1

32 GATE2

31 GATE3

30 GATE4

29 GATE5

28 GATE6

27 GND

LGND

NC

SGND 10

PWRGD 11

PWRLS 12

26 CS4P

25 CS4N

13 14 15 16 17 18 19 20 21 22 23 24

48−Pin QFN, Top View

48 47 46 45 44 43 42 41 40 39 38 37

V

CS1P

1

36

35

34

33

32

31

30

29

28

27

26

25

ID5

V

ID0

R

2

OSC

V

ID1

V

CC

3

V

ID2

GATE1

GATE2

GATE3

GATE4

GATE5

GATE6

GND

4

V

ID3

5

V

ID4

6

LGND

NC

7

8

NC

9

SGND

PWRGD

PWRLS

10

11

12

CS4P

CS4N

13 14 15 16 17 18 19 20 21 22 23 24

LQFP−48

Figure 1. Pin Connections

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2

NCP5316

1

D R N N D P G

T G

B S T

C O

B G

V

T G

B S T

C O

B G

V

T G

B S T

C O

B G

V

S

E N

1

D R N N D P G

T G

B S T

C O

B G

V

T G

B S T

C O

B G

V

T G

B S T

C O

B G

V

S

E N

C S 1 N

C S 2 P

C S 2 N

C S 3 P

C S 3 N

L I M

I P

D R P

V

C S 5 P

2 4

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

C S 5 N

2 3

C S 6 P

2 2

C S 6 N

2 1

N C

2 0

N C

1 9

C O M P

1 8

L I M

F B

I

V

1 7

1 6

F F B

V

I O F

I O

E N A B L E

1 5

R E F

V

C C L

V

S S

1 4

V O D N R

1 3

Figure 2. Application Diagram, 12 V to 0.8375 − 1.600 V Six−Phase Converter

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3

NCP5316

MAXIMUM RATINGS

Rating

Value

150

Unit

°C

Operating Junction Temperature

Lead Temperature Soldering, Reflow (Note 1)

Storage Temperature Range

230 peak

−65 to 150

°C

ESD Susceptibility:

Human Body Model (HBM)

2.0

1

kV

−

Moisture Sensitivity Level (MSL), LQFP

MSL, QFN

2

−

q

, LQFP

52

34

°C/W

JA

, QFN, Pad Soldered to PCB

1. 60 second maximum above 183°C.

MAXIMUM RATINGS

Pin Number

Pin Symbol

V

MAX

V

MIN

I

SINK

SOURCE

15

1−6

7

ENABLE

18 V

−

−0.3 V

−

1.0 mA

−

V

ID0

−V

ID5

1.0 mA

50 mA

NA

LGND

NC

8

NA

9

NC

NA

10

11

SGND

1.0 V

18 V

7.0 V

NA

−1.0 V

−0.3 V

NA

1.0 mA

NA

−

PWRGD

PWRLS

DRVON

SS

20 mA

1.0 mA

NA

12

13

14

16

17

18

19

20

21

22

23

24

25

26

27

28−33

34

35

36

37

38

39

40

V

FFB

V

FB

COMP

NC

NA

CS6N

18 V

−

−0.3 V

−

1.0 mA

−

CS6P

CS5N

CS5P

CS4N

CS4P

GND

0.4 A, 1.0 m s, 100 mA DC

GATE6−GATE1

18 V

7.0 V

18 V

−0.3 V

0.1 A, 1.0 m s, 25 mA DC

V

CC

−

0.4 A, 1.0 m s, 100 mA DC

R

1.0 mA

OSC

CS1P

CS1N

CS2P

CS2N

CS3P

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4

NCP5316

MAXIMUM RATINGS (continued)

Pin Number

Pin Symbol

V

MAX

V

MIN

I

SINK

SOURCE

41

42

43

44

45

46

47

48

CS3N

18 V

7.0 V

18 V

−0.3 V

1.0 mA

50 mA

IP

1.0 mA

5.0 mA

−

LIM

DRP

LIM

V

I

IOF

IO

V

REF

CCL

V

VOLTAGE IDENTIFICATION (VID)

VID Pins (0 = low, 1 = high)

VID Code*(V)

−0.5%

V

OUT

No Load† (V)

+0.5%

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

V

ID5

0

1

0

1

0

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

0.8134

0.8259

0.8383

0.8507

0.8632

0.8756

0.8880

0.9005

0.9129

0.9254

0.9378

0.9502

0.9627

0.9751

0.9875

1.0000

1.0124

1.0249

1.0373

1.0497

1.0622

0.8175

0.8300

0.8425

0.8550

0.8675

0.8800

0.8925

0.9050

0.9175

0.9300

0.9425

0.9550

0.9675

0.9800

0.9925

1.0050

1.0175

1.0300

1.0425

1.0550

1.0675

0.8216

0.8342

0.8467

0.8593

0.8718

0.8844

0.8970

0.9095

0.9221

0.9347

0.9472

0.9598

0.9723

0.9849

0.9975

1.0100

1.0226

1.0352

1.0477

1.0603

1.0728

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OFF

1.1000

1.1125

1.1250

1.1375

1.1500

1.0746

1.0870

1.0995

1.1119

1.1244

1.0800

1.0925

1.1050

1.1175

1.1300

1.0854

1.0980

1.1105

1.1231

1.1357

*VID Code is for reference only.

†V No Load is the input to the error amplifier.

OUT

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5

NCP5316

VOLTAGE IDENTIFICATION (VID) (continued)

VID Pins (0 = low, 1 = high)

VID Code*(V)

−0.5%

V

OUT

No Load† (V)

+0.5%

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

V

ID5

1

0

1

0

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.1368

1.1492

1.1617

1.1741

1.1865

1.1990

1.2114

1.2239

1.2363

1.2487

1.2612

1.2736

1.2860

1.2985

1.3109

1.3234

1.3358

1.3482

1.3607

1.3731

1.3855

1.3980

1.4104

1.4229

1.4353

1.4477

1.4602

1.4726

1.4850

1.4975

1.5099

1.5224

1.5348

1.5472

1.5597

1.5721

1.1425

1.1550

1.1675

1.1800

1.1925

1.2050

1.2175

1.2300

1.2425

1.2550

1.2675

1.2800

1.2925

1.3050

1.3175

1.3300

1.3425

1.3550

1.3675

1.3800

1.3925

1.4050

1.4175

1.4300

1.4425

1.4550

1.4675

1.4800

1.4925

1.5050

1.5175

1.5300

1.5425

1.5550

1.5675

1.5800

1.1482

1.1608

1.1733

1.1859

1.1985

1.2110

1.2236

1.2362

1.2487

1.2613

1.2738

1.2864

1.2990

1.3115

1.3241

1.3367

1.3492

1.3618

1.3743

1.3869

1.3995

1.4120

1.4246

1.4372

1.4497

1.4623

1.4748

1.4874

1.5000

1.5125

1.5251

1.5377

1.5502

1.5628

1.5753

1.5879

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*VID Code is for reference only.

†V No Load is the input to the error amplifier.

OUT

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6

NCP5316

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; V

= V = 12 V; C

= 100 pF, C

= 0.01 m F,

A

CCL

CC

GATEx

COMP

C

= 0.1 m F, C

= 0.1 m F, R = 32.4 kW, V(I ) = 3.3 V, V(IP ) = 3.3 V, unless otherwise noted)

ROSC LIM LIM

SS

VCC

Characteristic

Test Conditions

Min

Typ

Max

Unit

VID Inputs

Input Threshold

VID Pin Current

SGND Bias Current

V

, V , V , V , V , V

400

−

800

1.0

40

mV

m A

ID5

ID4

ID3

ID2

ID1

ID0

, V , V , V , V , V

= 0 V

ID5

ID4

ID3

ID2

ID1

ID0

SGND < 300 mV, All DAC Codes

−

10

20

−

m

A

SGND Voltage Compliance Range

Power Good

−200

300

mV

Upper Threshold

−

85

100

115

mV

Offset from V

No Load

OUT

Lower Threshold Constant

Output Low Voltage

Delay

PWRLS/V

No Load

0.475

−

0.500

0.15

250

0.525

0.40

600

V/V

V

OUT

I

= 4.0 mA

PWRGD

V

FFB

low to PWRGD low

50

m

s

Overvoltage Protection VID

OVP Threshold above VID

Enable Input

−

190

200

250

mV

Start Threshold

Gates switching, SS high

Gates not switching, SS low

1.0 MW to GND

0.8

−

V

Stop Threshold

0.4

3.3

20

Input Pull−Up Voltage

Input Pull−Up Resistance

Voltage Feedback Error Amplifier

2.7

7.0

2.8

10

−

kW

V

Bias Current

−

40

1.1

72

−

0.1

70

1.3

80

4.0

60

3

1.0

100

1.5

−

m A

FB

COMP Source Current

COMP Sink Current

Transconductance

Open Loop DC Gain

Unity Gain Bandwidth

PSRR @ 1.0 kHz

COMP = 0.5 V to 2.0 V

−

m

A

Note 2

mmho

dB

Note 2

C

= 30 pF

−

MHz

dB

COMP

−

COMP Max Voltage

COMP Min Voltage

PWM Comparators

Minimum Pulse Width

V

= 0 V

2.9

−

V

FB

= 1.6 V

50

150

mV

FB

Measured from CSxP to GATEx,

= CSxN = 0.5, COMP = 0.5 V,

60 mV step between CSxP and CSxN;

Measure at GATEx = 1.0 V

−

40

100

60

ns

V

FB

Transient Response Time

Channel Start−Up Offset

Measured from CSxN to GATEx,

COMP = 2.1 V, CSxP = CSxN = 0.5 V,

CSxN stepped from 1.2 V to 2.0 V

CSxP = CSxN = V

= 0, Measure

0.35

−

0.6

0.75

−

V

FFB

Vcomp when GATEx switch high

Artificial Ramp Amplitude

MOSFET Driver Enable (DRVON)

Output High

50% duty cycle

100

mV

DRVON floating

−

2.3

−

V

Output Low

0.2

140

Pull−Down Resistance

DRVON = 1.5 V, ENABLE = 0 V,

R = 1.5 V/I(DRVON)

35

70

kW

Source Current

DRVON = 1.5 V

1

4

6.5

mA

V

REF

Output Voltage

GATES

0 mA < I(V ) < 1.0 mA

REF

3.25

2.25

3.3

2.70

3.35

3.00

High Voltage

Measure GATEx, I

= 1.0 mA

V

GATEx

2. Guaranteed by design, not tested in production.

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7

NCP5316

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; V

= V = 12 V; C

= 100 pF, C

= 0.01 m F,

A

CCL

CC

GATEx

COMP

C

= 0.1 m F, C

= 0.1 m F, R = 32.4 kW, V(I ) = 3.3 V, V(IP ) = 3.3 V, unless otherwise noted)

ROSC LIM LIM

SS

VCC

Characteristic

Test Conditions

Min

Typ

Max

Unit

GATES

Low Voltage

Measure GATEx, I

= 1.0 mA

−

0.1

2.5

5.0

0.7

10

V

GATEx

Rise Time GATE

Fall Time GATE

Oscillator

0.8 V < GATEx < 2.0 V, V = 10 V

ns

CC

2.0 V > GATEx > 0.8 V, V = 10 V

CC

Switching Frequency

R

= 32.4 k, 4−Phase mode

= 32.4 k, 5−Phase mode

= 32.4 k, 6−Phase mode

450

520

550

525

620

650

600

720

750

kHz

OSC

R

Voltage

−

0.95

−

1.0

60

72

90

−

1.05

−

V

OSC

Phase Delay, 6 Phases

Phase Delay, 5 Phases

Phase Delay, 4 Phases

Phase Disable Threshold

Adaptive Voltage Positioning

deg

mV

CS6P = CS6N = V

−

CC

CS3P = CS3N = CS6P = CS6N = V

−

CC

V

CC

− (CSxP = CSxN)

500

−

V

Output Voltage to DAC

Offset

CSxP = CSxN, V = COMP,

−15

2.3

1.0

0.2

−

15

2.75

14

mV

V/V

mA

DRP

OUT

FB

Measure V

− COMP

DRP

Current Sense Amplifier to V

Gain

CSxP − CSxN = 80 mV, V = COMP,

2.55

1.5

0.4

DRP

FB

Measure V

− COMP, V

= 1.0 V

DRP

V

Source Current

Sink Current

CSxP − CSxN = 0 mV, V = COMP,

FB

DRP

V

DRP

= 2.0 V

CSxP − CSxN = 80 mV, V = COMP,

0.6

DRP

FB

V

DRP

= 0.5 V

Soft Start

Charge Current

V

CCL

V

CCL

V

CCL

= 10 V

30

90

40

120

0.9

50

150

2.1

m A

Discharge Current

COMP Pull−Down Current

= 7.0 V

= 10 V

0.2

mA

Current Sensing and Overcurrent Protection

CSxP Input Bias Current

CSxN = CSxP = 0 V

−

0.1

3.0

1.0

−

m A

CSxN Input Bias Current

Current Sense Amp to PWM Gain

CSxN = 0 V, CSxP = 80 mV, Measure

V(COMP) when GATEx switches high

V/V

Current Sense Amp to PWM Bandwidth

Current Sense Amp to IO Gain

−

7.0

4.2

−

MHz

V/V

IO/(CSxP − CSxN), I

= 0.6 V,

3.85

4.4

LIM

GATEx not switching

Current Sense Amp to IO Bandwidth

IO Source Current

−

4.0

0.5

−

1.0

10

−

MHz

mA

m A

−

IO Sink Current

0.9

0.1

1.5

1.0

I

Input Bias Current

I

= 0 V

LIM

IOF Input Bias Current

IP Input Bias Current

IOF = 0 V

IP = 0 V

−

m A

−

0.1

9.5

1.0

11

m A

LIM

Current Sense Amp to Pulse−by−Pulse

Current Limit Comparator Gain

−

8.0

V/V

Current Sense Common Mode Input Range Note 2

0

−

2.0

V

General Electrical Specifications

V

Operating Current

COMP = 0.3 V (no switching)

SS charging, GATEx switching

−

36

9.0

8.0

40

9.5

8.5

mA

V

CC

UVLO Start Threshold

UVLO Stop Threshold

8.5

7.5

GATEx not switching, SS & COMP

discharging

V

UVLO Hysteresis

Start − Stop

0.8

1.0

1.2

V

2. Guaranteed by design, not tested in production.

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8

NCP5316

PIN DESCRIPTION

Pin No.

Pin Symbol

−V

Pin Name

Description

VID−compatible logic input used to program the converter output

1−6

V

DAC VID Inputs

ID0

ID5

voltage. All high on V −V generates fault.

ID0

ID4

7

8, 9, 19, 20

10

LGND

NC

Logic Ground

No Connect

IC analog ground; connected to IC substrate.

For factory test only. Let these pins float.

SGND

Remote Sense Ground

Ground connection for DAC and error amplifier. Provides remote

sensing of load ground.

11

PWRGD

Power Good Output

Open collector output goes high when the converter output is in reg-

ulation.

12

13

PWRLS

DRVON

Power Good Sense

Drive Enable

Voltage sensing pin for Power Good lower threshold.

Logic high output enables MOSFET drivers, and logic low turns all

MOSFETs off through MOSFET drivers. Pulled to ground through

internal 70 kW resistor.

14

15

SS

Soft Start

Enable

A capacitor between this pin and ground programs the soft start time.

A voltage less than the threshold puts the IC in Fault Mode, dis-

ENABLE

charging SS. Connect to system VID

signal to control power-

PWRGD

up sequencing. Hysteresis is provided to prevent chatter.

16

V

FFB

Fast Voltage Feedback

Input of PWM comparator for fast voltage feedback, and also the

inputs of Power Good sense and overvoltage protection comparators

17

18

V

Voltage Feedback

Error Amp Output

Error amplifier inverting input.

FB

COMP

Provides loop compensation and is clamped by SS during soft start

and fault conditions. It is also the inverting input of PWM compara-

tors.

21

22

CS6N

CS6P

Current Sense Reference

Current Sense Input

Inverting input to current sense amplifier #6, and Phase 6 disable

pin.

Non−inverting input to current sense amplifier #6, and Phase 6 dis-

able pin.

23

24

CS5N

CS5P

Current Sense Reference

Current Sense Input

Current Sense Reference

Current Sense Input

Ground

Inverting input to current sense amplifier #5.

Non−inverting input to current sense amplifier #5.

Inverting input to current sense amplifier #4.

Non−inverting input to current sense amplifier #4.

Power supply return of Gate circuits.

25

CS4N

26

CS4P

27

GND

28−33

34

GATE6−GATE1

Channel Outputs

PWM outputs to drive MOSFET driver ICs.

V

CC

Gate Power Supply

Power Supply Input for Gate circuits. Must be tied to V

.

CCL

35

R

Oscillator Frequency Adjust Resistor to ground programs the oscillator frequency, as shown in

Figure 5.

OSC

36

37

38

39

40

CS1P

CS1N

CS2P

CS2N

CS3P

Current Sense Input

Current Sense Reference

Current Sense Input

Non−inverting input to current sense amplifier #1.

Inverting input to current sense amplifier #1.

Non−inverting input to current sense amplifier #2.

Inverting input to current sense amplifier #2.

Current Sense Reference

Current Sense Input

Non−inverting input to current sense amplifier #3, and Phase 3 dis-

able pin.

41

42

43

CS3N

Current Sense Reference

Pulse−by−Pulse Limit

Inverting input to current sense amplifier #3, and Phase 3 disable

pin.

IP

LIM

Resistor divider from V

to ground programs the threshold of

REF

pulse−by−pulse limit of each phase.

V

DRP

Output of Current Sense

Amplifiers for Adaptive

Voltage Positioning:

“Droop” Pin

The offset above DAC voltage is proportional to the sum of inductor

current. A resistor from this pin to V programs the amount of Adap-

FB

tive Voltage Positioning. Leave this pin open for no Adaptive Voltage

Positioning.

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9

NCP5316

PIN DESCRIPTION (continued)

Pin No.

Pin Symbol

Pin Name

Description

Resistor divider between V and ground programs the average

REF

44

I

Total Current Limit

LIM

current limit.

45

IOF

Average Inductor Current

Input

Connect a low pass filter from the 10 pin to the 10F pin to provide

average inductor current information.

46

47

48

IO

Inductor Current Output

Reference

Output of the sum of inductor current.

3.3 V reference voltage output.

V

REF

V

CCL

Logic Power Supply

Power supply input for IC logic. Must be tied to V

.

CC

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10

NCP5316

TYPICAL PERFORMANCE CHARACTERISTICS

3.6

1000

6 Phases

5 Phases

3.4

4 Phases

3.2

3.0

2.8

2.6

2.4

2.2

100

10

100

(kW)

1000

0

10

20

30

40

T (°C)

50

60

70

80

R

OSC

A

Figure 5. R_OSC(kW) vs. f_SW(kHz)

Figure 6. Current Sense Amplifier to PWM Gain vs. T_A

2.65

2.60

9.80

9.75

9.70

9.65

9.60

9.55

9.50

2.55

2.50

2.45

9.45

9.40

0

10

20

30

40

T (°C)

50

60

70

80

0

10

20

30

40

T (°C)

50

60

70

80

A

Figure 7. Current Sense to V_DRPGain vs. T_A

Figure 8. IP_LIMGain vs. T_A

4.40

4.35

4.30

4.25

4.20

120

115

110

105

100

95

90

4.15

4.10

85

80

0

10

20

30

40

T (°C)

50

60

70

80

0

10

20

30

40

T (°C)

50

60

70

80

A

Figure 9. IO Gain vs. T_A

Figure 10. Artificial Ramp Amplitude at

50% Duty Cycle vs. T_A

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NCP5316

TYPICAL PERFORMANCE CHARACTERISTICS

0.25

800

750

700

650

600

550

500

450

400

0

−0.25

0

10

20

30

40

T (°C)

50

60

70

80

0

10

20

30

40

T (°C)

50

60

70

80

A

Figure 11. DAC Output vs. T_A

Figure 12. Average Channel Offset vs. T_A

220

255

250

245

240

235

215

210

205

200

195

190

230

225

0

10

20

30

40

T (°C)

50

60

70

80

0

10

20

30

40

T (°C)

50

60

70

80

A

Figure 13. OVP Latch Threshold vs. T_A

Figure 14. PWRGD Delay vs. T_A

41

44

43

42

41

40

39

37

35

33

31

29

27

25

39

38

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

T (°C)

A

T (°C)

A

Figure 15. SS Charge Current vs. T_A

Figure 16. I_CCvs. T_A

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14

NCP5316

APPLICATIONS INFORMATION

Overview

The NCP5316 controller uses six−phase, fixed−frequency,

Enhanced V architecture to measure and control currents in

2

The NCP5316 DC/DC controller from ON Semiconductor

2

was developed using the Enhanced V topology. Enhanced

individual phases. In six−phase mode, each phase is delayed

60° from the previous phase. Normally, GATEx transitions

to a high voltage at the beginning of each oscillator cycle.

Inductor current ramps up until the combination of the

current sense signal, the internal ramp and the output voltage

ripple trip the PWM comparator and bring GATEx low.

Once GATEx goes low, it will remain low until the

beginning of the next oscillator cycle. While GATEx is high,

2

V

combines the original V topology with peak

current−mode control for fast transient response and current

sensing capability. The addition of an internal PWM ramp

and implementation of fast−feedback directly from Vcore

has improved transient response and simplified design. This

controller can be adjusted to operate as a four−, five− or

six−phase controller, and can also be used in a one−, two− or

three−phase system. Differential current sensing provides

improved current sharing and easier layout. The NCP5316

includes Power Good (PWRGD), providing a highly

integrated solution to simplify design, minimize circuit

board area, and reduce overall system cost.

Two advantages of a multi−phase converter over a

single−phase converter are current sharing and increased

effective output frequency. Current sharing allows the designer

to use less inductance in each phase than would be required in

a single−phase converter. The smaller inductor will produce

larger ripple currents but the total per−phase power dissipation

is reduced because the RMS current is lower. Transient

response is improved because the control loop will measure

and adjust the current faster in a smaller output inductor.

Increased apparent output frequency is desirable because the

off− time and the ripple voltage of the multi−phase converter

will be less than that of a single−phase converter.

2

the Enhanced V loop will respond to line and load

variations. On the other hand, once GATEx is low, the loop

cannot respond until the beginning of the next PWM cycle.

2

Therefore, constant frequency Enhanced V will typically

respond to disturbances within the off−time of the converter.

2

The Enhanced V architecture measures and adjusts the

output current in each phase. An additional differential input

(CSxN and CSxP) for inductor current information has been

2

added to the V loop for each phase as shown in Figure 17.

The triangular inductor current is measured differentially

across RS, amplified by CSA and summed with the channel

startup offset, the internal ramp and the output voltage at the

non−inverting input of the PWM comparator. The purpose

of the internal ramp is to compensate for propagation delays

in the NCP5316. This provides greater design flexibility by

allowing smaller external ramps, lower minimum pulse

widths, higher frequency operation and PWM duty cycles

above 50% without external slope compensation. As the

sum of the inductor current and the internal ramp increase,

the voltage on the positive pin of the PWM comparator rises

and terminates the PWM cycle. If the inductor starts a cycle

with higher current, the PWM cycle will terminate earlier

providing negative feedback. The NCP5316 provides a

differential current sense input (CSxN and CSxP) for each

phase. Current sharing is accomplished by referencing all

phases to the same COMP pin, so that a phase with a larger

current signal will turn off earlier than a phase with a smaller

current signal.

Fixed Frequency Multi−Phase Control

In a multi−phase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

x = 1, 2, 3, 4, 5 or 6

Lx

SWNODE

CSxP

CSxN

RLx

+

CSA

−

COx

RSx

Internal Ramp

V

FFB

V

OUT

“Fast−Feedback”

Connection

+

−

To PWM Latch Reset

Channel

Start−Up

Offset

(V

)

CORE

+

V

FB

−

PWM

COMP

E.A.

+

DAC

Out

COMP

+

Figure 17. Enhanced V²Control Employing Resistive Current Sensing and Internal Ramp

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15

NCP5316

2

Enhanced V responds to disturbances in V

by

or, in a closed loop configuration when the output current

CORE

employing both “slow” and “fast” voltage regulation. The

internal error amplifier performs the slow regulation.

Depending on the gain and frequency compensation set by

the amplifier’s external components, the error amplifier will

typically begin to ramp its output to react to changes in the

output voltage in one or two PWM cycles. Fast voltage

feedback is implemented by a direct connection from Vcore

to the non−inverting pin of the PWM comparator via the

summation with the inductor current, internal ramp and

offset. A rapid increase in output current will produce a

negative offset at Vcore and at the output of the summer.

This will cause the PWM duty cycle to increase almost

instantly. Fast feedback will typically adjust the PWM duty

cycle in one PWM cycle.

As shown in Figure 17, an internal ramp (100 mV at a 50%

duty cycle) is added to the inductor current ramp at the

positive terminal of the PWM comparator. This additional

ramp compensates for propagation time delays from the

current sense amplifier (CSA), the PWM comparator and

the MOSFET gate drivers. As a result, the minimum ON

time of the controller is reduced and lower duty−cycles may

be achieved at higher frequencies. Also, the additional ramp

reduces the reliance on the inductor current ramp and allows

greater flexibility when choosing the output inductor and the

changes, the COMP pin must move to keep the same output

voltage. The required change in the output voltage or COMP

pin depends on the scaling of the current feedback signal and

is calculated as:

D V + R @ G

@ D I

OUT

S

CSA

The single−phase power stage output impedance is:

Single Stage Impedance+D V

ń

D I +R @ G

OUT OUT S CSA

The total output impedance will be the single stage

impedance divided by the number of phases in operation.

The output impedance of the power stage determines how

the converter will respond during the first few microseconds

of a transient before the feedback loop has repositioned the

COMP pin.

The peak output current can be calculated from:

I

OUT,PEAK + (V

* V

* Offset)

ń

(R @ G

)

CSA

COMP

OUT

S

Figure 18 shows the step response of the COMP pin at a

fixed level. Before T1, the converter is in normal

steady−state operation. The inductor current provides a

portion of the PWM ramp through the current sense

amplifier. The PWM cycle ends when the sum of the current

ramp, the “partial” internal ramp voltage signal and offset

exceed the level of the COMP pin. At T1, the output current

increases and the output voltage sags. The next PWM cycle

begins and the cycle continues longer than previously while

the current signal increases enough to make up for the lower

R

V

C

time constant of the feedback components from

to the CSx pin.

CSx CSx

CORE

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. When the average output

current is zero, the COMP pin will be:

voltage at the V pin and the cycle ends at T2. After T2, the

FB

output voltage remains lower than at light load and the

average current signal level (CSx output) is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system, the COMP pin would

move higher to restore the output voltage to the original

level.

V

+

V

@ 0 A ) Channel_Startup_Offset

COMP

OUT

) Int_Ramp ) G

@ Ext_Rampń2

CSA

Int_Ramp is the “partial” internal ramp value at the

corresponding duty cycle, Ext_Ramp is the peak−to−peak

external steady−state ramp at 0 A, G

is the current sense

CSA

amplifier gain (3.0 V/V) and the channel startup offset is

0.60 V. The magnitude of the Ext_Ramp can be calculated

from:

SWNODE

Ext_Ramp + D @ (V * V

IN

)ń(R

OUT

@ C

@ f )

CSx SW

CSx

V

FB

(V

OUT

)

For example, if V

at 0 A is set to 1.480 V with AVP

OUT

and the input voltage is 12.0 V, the duty cycle (D) will be

1.480/12.0 or 12.3%. Int_Ramp will be

100 mV/50% 12.3% = 25 mV. Realistic values for R

Internal Ramp

,

CSx

C

and f are 10 kW, 0.015 m F and 650 kHz. Using these

CSx

SW

CSA Out

and the previously mentioned formula, Ext_Ramp will be

15.0 mV.

COMP−Offset

CSA Out + Ramp + CS

V

+ 1.480 V ) 0.60 V ) 25 mV

) 2.65 VńV @ 15.0 mVń2

+ 2.125 Vdc.

COMP

REF

T1

T2

Figure 18. Open Loop Operation

If the COMP pin is held steady and the inductor current

changes, there must also be a change in the output voltage,

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16

NCP5316

x = 1, 2, 3, 4, 5 or 6

R

CSx

SWNODE

CSxP

+

COx

Lx

C

CSA

CSx

−

CSxN

Internal Ramp

RLx

V

FFB

To PWM

Latch Reset

V

“Fast−Feedback”

OUT

+

−

Channel

Start−Up

Offset

(V

)

Connection

−

CORE

+

V

FB

PWM

COMP

E.A.

+

DAC

Out

COMP

+

Figure 19. Enhanced V²Control Employing Lossless Inductive Current Sensing and Internal Ramp

Inductive Current Sensing

For lossless sensing, current can be measured across the

inductor as shown in Figure 19. In the diagram, L is the

Current Sense Amplifier (CSA) input mismatch and the

value of the current sense component will determine the

accuracy of the current sharing between phases. The worst

case CSA input mismatch is ±10 mV and will typically be

within 4.0 mV. The difference in peak currents between

phases will be the CSA input mismatch divided by the

current sense resistance. If all current sense components are

of equal resistance, a 3.0 mV mismatch with a 2.0 mW sense

resistance will produce a 1.5 A difference in current between

phases.

output inductance and R is the inherent inductor resistance.

L

To compensate the current sense signal, the values of R

CSx

. If this

and C

are chosen so that L/R = R

C

CSx

L

CSx

criteria is met, the current sense signal should be the same

shape as the inductor current and the voltage signal at CSx

will represent the instantaneous value of inductor current.

Also, the circuit can be analyzed as if a sense resistor of value

R was used.

L

External Ramp Size and Current Sensing

The internal ramp allows flexibility in setting the current

sense time constant. Typically, the current sense R

time constant should be equal to or slightly slower than the

inductor’s time constant. If RC is chosen to be smaller

When choosing or designing inductors for use with

inductive sensing, tolerances and temperature effects should

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per °C. The increase in

winding resistance at higher temperatures should be

considered when setting the threshold. If a more accurate

current sense is required than inductive sensing can provide,

current can be sensed through a resistor as shown in

Figure 17.

C

CSx

(faster) than L/R , the AC or transient portion of the current

L

sensing signal will be scaled larger than the DC portion. This

will provide a larger steady−state ramp, but circuit

performance will be affected and must be evaluated

carefully. The current signal will overshoot during transients

and settle at the rate determined by R

C

. It will

CSx

eventually settle to the correct DC level, but the error will

decay with the time constant of R . If this error is

Current Sharing Accuracy

C

CSx

Printed circuit board (PCB) traces that carry inductor

current can be used as part of the current sense resistance

depending on where the current sense signal is picked off.

For accurate current sharing, the current sense inputs should

sense the current at relatively the same points for each phase.

In some cases, especially with inductive sensing, resistance

of the PCB can be useful for increasing the current sense

resistance. The total current sense resistance used for

calculations must include any PCB trace resistance that

carries inductor current between the CSxP input and the

CSxN input.

excessive, it will affect transient response, adaptive

positioning and current limit. During a positive current

transient, the COMP pin will be required to undershoot in

response to the current signal in order to maintain the output

voltage. Similarly, the V

signal will overshoot which

DRP

will produce too much transient droop in the output voltage.

The single−phase pulse−by−pulse overcurrent protection

will trip earlier than it would if compensated correctly and

hiccup−mode current limit will have a lower threshold for

fast rising step loads than for slowly rising output currents.

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NCP5316

Transient Response and Adaptive Voltage Positioning

impedance, and by the ESR and ESL of the output filter. The

transition between fast and slow positioning is controlled by

the total ramp size and the error amp compensation. If the

ramp size is too large or the error amp too slow, there will be

a long transition to the final voltage after a transient. This

will be most apparent with low capacitance output filters.

For applications with fast transient currents, the output

filter is frequently sized larger than ripple currents require in

order to reduce voltage excursions during load transients.

Adaptive voltage positioning can reduce peak−peak output

voltage deviations during load transients and allow for a

smaller output filter. The output voltage can be set higher

than nominal at light loads to reduce output voltage sag

when the load current is applied. Similarly, the output

voltage can be set lower than nominal during heavy loads to

reduce overshoot when the load current is removed. For low

current applications, a droop resistor can provide fast,

accurate adaptive positioning. However, at high currents,

the loss in a droop resistor becomes excessive. For example,

a 50 A converter with a 1 mW resistor would provide a 50

mV change in output voltage between no load and full load

and would dissipate 2.5 W.

Normal

Fast Adaptive Positioning

SlowAdaptive Positioning

Limits

Figure 20. Adaptive Voltage Positioning

Lossless adaptive voltage positioning (AVP) is an

alternative to using a droop resistor, but it must respond to

changes in load current. Figure 20 shows how AVP works.

The waveform labeled “normal” shows a converter without

AVP. On the left, the output voltage sags when the output

current is stepped up and later overshoots when current is

stepped back down. With fast (ideal) AVP, the peak−to−peak

excursions are cut in half. In the slow AVP waveform, the

output voltage is not repositioned quickly enough after

current is stepped up and the upper limit is exceeded.

The controller can be configured to adjust the output

voltage based on the output current of the converter. (Refer to

the application diagram in Figure 2). The no−load positioning

is now set internally to VID − 20 mV, reducing the potential

error due to resistor and bias current mismatches.

Overvoltage Protection

Overvoltage protection (OVP) is provided as a result of

the normal operation of the Enhanced V control topology

with synchronous rectifiers. The control loop responds to an

overvoltage condition within 40 ns, causing the GATEx

output to shut off. The (external) MOSFET driver should

react normally to turn off the top MOSFET and turn on the

bottom MOSFET. This results in a “crowbar” action to

clamp the output voltage and prevent damage to the load.

The regulator will remain in this state until the fault latch is

2

reset by cycling power at the V pin.

CC

If the voltage at the V

pin exceeds 200 mV above the

FFB

VID voltage, the converter will latch off.

In order to realize the AVP function, a resistor divider

Power Good

network is connected between V , V

and V

.

FB

DRP

OUT

According to the latest specifications, the Power Good

(PWRGD) signal must be asserted when the output voltage

is within a window defined by the VID code, as shown in

Figure 21.

The PWRLS pin is provided to allow the PWRGD

comparators to accurately sense the output voltage. The

effect of the PWRGD lower threshold can be modified using

a resistor divider from the output to PWRLS to ground, as

shown in Figure 22.

During no−load conditions, the V

pin is at the same

DRP

voltage as the V pin. As the output current increases, the

FB

V

pin voltage increases proportionally. This drives the

DRP

voltage higher, causing V

to “droop” according to

FB

OUT

a loadline set by the resistor divider network.

The response during the first few microseconds of a load

transient is controlled primarily by power stage output

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NCP5316

PWRGD

HIGH

V

OUT

PWRGD

low

PWRGD

high

PWRGD

low

R1

R2

PWRLS

LOW

V

OUT

−2.6% +2.6%

−5.0% +5.0%

VID + 80 mV

V

LOWER

Figure 21. PWRGD Assertion Window

Figure 22. Adjusting the PWRGD Threshold

Current Limit

Since the internally−set thresholds for PWRLS are V

OUT

Two levels of over−current protection are provided. First,

if the absolute value of the voltage between the Current

Sense pins (CSxN and CSxP) exceeds the voltage at the

No Load /2 for the lower threshold and V

No Load

OUT

+ 100 mV for the upper threshold, a simple equation can be

provided to assist the designer in selecting a resistor divider

to provide the desired PWRGD performance.

IP

pin (Single Pulse Current Limit), the PWM

LIM

comparator is turned off. This provides fast peak current

protection for individual phases. Second, the individual

phase currents are summed and externally low−pass filtered

to compare an averaged current signal to a user adjustable

V

NoLoad

2

R ) R

OUT

1

2

V

+

@

LOWER

UPPER

R

1

+ V

NoLoad ) 100 mV

OUT

voltage on the I

fault latch trips and the converter is latched off. V must be

recycled to reset the latch.

pin. If the I

voltage is exceeded, the

LIM

The logic circuitry inside the chip sets PWRGD low only

after a delay period has been passed. A “power bad” event

does not cause PWRGD to go low unless it is sustained

through the delay time of 250 m s. If the anomaly disappears

before the end of the delay, the PWRGD output will never

be set low.

In order to use the PWRGD pin as specified, the user is

advised to connect external resistors as necessary to limit the

current into this pin to 4 mA or less.

CC

Fault Protection Logic

The NCP5316 includes fault protection circuitry to

prevent harmful modes of operation from occurring. The

fault logic is described in Table 1.

Gate Outputs

The NCP5316 is designed to operate with external gate

drivers. Accordingly, the gate outputs are capable of driving

a 100 pF load with typical rise and fall times of 5 ns.

Undervoltage Lockout

The NCP5316 includes an undervoltage lockout circuit.

This circuit keeps the IC’s output drivers low until V

CC

applied to the IC reaches 9 V. The GATE outputs are disabled

Digital to Analog Converter (DAC)

when V drops below 8 V.

The output voltage of the NCP5316 is set by means of a

6−bit, 0.5% DAC. The VID pins must be pulled high

externally. A 1 kW pullup to a maximum of 3.3 V is

recommended to meet Intel specifications. To ensure valid

logic signals, the designer should ensure at least 800 mV will

be present at the IC for a logic high.

The output of the DAC is described in the Electrical

Characteristics section of the data sheet. These outputs are

consistent with VR 10.x and processor specifications. The

DAC output is equal to the VID code specification minus

20 mV.

The latest VR and processor specifications require a

power supply to turn its output off in the event of a 11111X

VID code. When the DAC sees such a code, the GATE pins

stop switching and go low. This condition is described in

Table 1.

CC

Soft Start

At initial power−up, both SS and COMP voltages are zero.

The total SS capacitance will begin to charge with a current

of 40 m A. The error amplifier directly charges the COMP

capacitance. An internal clamp ensures that the COMP pin

voltage will always be less than the voltage at the SS pin,

ensuring proper start−up behavior. All GATE outputs are

held low until the COMP voltage reaches 0.6 V. Once this

threshold is reached, the GATE outputs are released to

operate normally.

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19

NCP5316

Table 1. Description of Fault Logic

Results

Driver

Stop

Switching

SS

Enable Characteristics

PWRGD Level

Reset Method

Power On

Faults

Overvoltage Lockout

Enable Low

Yes

High

Low

High

−0.3 mA

Depends on output voltage level

Not Affected

Power On

Module Overcurrent Limit

DAC Code = 11111x

−0.3 mA

Change VID Code

Power On

V

REF

Undervoltage Lockout

−0.3 mA

Phase Negative Overcurrent Limit

Phase Overcurrent Limit

−0.3 mA

Power On

Terminate

Pulse

Not Affected

PWRLS Out of Range

No

Low

High

Not Affected

Adjusting the Number of Phases

2. Output Capacitor Selection

The NCP5316 was designed with a selectable−phase

architecture. Designers may choose any number of phases

up to six. The phase delay is automatically adjusted to match

the number of phases that will be used. This feature allows

the designer to select the number of phases required for a

particular application.

Six−phase operation is standard. All phases switch with a

60 degree delay between pulses. No special connections are

required.

The output capacitors filter the current from the output

inductor and provide a low impedance for transient load

current changes. Typically, microprocessor applications

require both bulk (electrolytic, tantalum) and low

impedance, high frequency (ceramic) types of capacitors.

The bulk capacitors provide “hold up” during transient

loading. The low impedance capacitors reduce steady−state

ripple and bypass the bulk capacitance when the output

current changes very quickly. The microprocessor

manufacturers usually specify a minimum number of

ceramic capacitors. The designer must determine the

number of bulk capacitors.

Five−phase operation is achieved by disabling either

phase 3 or phase 6. Tie together CS3N and CS3P or CS6N

and CS6P, and then pull both pins to V . The remaining

CC

phases will continue to switch, but now there will be a 72

degree delay between pulses. The phase firing order will

become 1−2−3−4−5 or 1−2−4−5−6, depending on which

phase was disabled.

Choose the number of bulk output capacitors to meet the

peak transient requirements. The formula below can be used

to provide a starting point for the minimum number of bulk

capacitors (N

):

OUT,MIN

Four−phase operation is achieved by tying together

CS3N, CS3P, CS6N and CS6P, and pulling all of these pins

(1)

D I

O,MAX

N

+ ESR per capacitor @

OUT,MIN

D V

O,MAX

to V . This will result in a 90 degree phase delay, and a

CC

firing order of 1−2−4−5.

In reality, both the ESR and ESL of the bulk capacitors

determine the voltage change during a load transient

according to:

Three−phase operation may be realized as well. First, the

designer must choose the proper phases. For example, for

three−phase operation, phases 2, 4 and 6 must be selected.

Second, the current sense inputs should be pulled to a

defined voltage ground. Simply tie all the current sense

inputs of the unused phases together and connect them to

ground.

(2)

D t) @ ESL ) D I @ ESR

O,MAX

D V

+ (D I

O,MAX

ń

O,MAX

Unfortunately, capacitor manufacturers do not specify the

ESL of their components and the inductance added by the

PCB traces is highly dependent on the layout and routing.

Therefore, it is necessary to start a design with slightly more

than the minimum number of bulk capacitors and perform

transient testing or careful modeling/simulation to

determine the final number of bulk capacitors.

Design Procedure

1. Setting the Switching Frequency

The per−phase switching frequency is set by placing a

resistor from ROSC to GND. Choose the resistor according

to Figure 6.

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NCP5316

The latest Intel processor specifications discuss “dynamic

The maximum inductor value is limited by the transient

response of the converter. If the converter is to have a fast

transient response, the inductor should be made as small as

possible. If the inductor is too large its current will change

too slowly, the output voltage will droop excessively, more

bulk capacitors will be required and the converter cost will

be increased. For a given inductor value, it is useful to

determine the times required to increase or decrease the

current.

VID” (DVID), in which the VID codes are stepped up or

down to a new desired output voltage. Due to the timing

requirements at which the output must be in regulation, the

output capacitor selection becomes more complicated. The

ideal output capacitor selection has low ESR and low

capacitance. Too much output capacitance will make it

difficult to meet DVID timing specifications; too much ESR

will complicate the transient solution. The Sanyo

4SEPC560 and Panasonic EEU−FL provide a good balance

of capacitance vs. ESR.

For increasing current:

(3.1)

D t

INC

+ Lo @ D I ń(V * V

IN

)

OUT

O

3. Output Inductor Selection

For decreasing current:

The output inductor may be the most critical component

in the converter because it will directly effect the choice of

other components and dictate both the steady−state and

transient performance of the converter. When selecting an

inductor, the designer must consider factors such as DC

current, peak current, output voltage ripple, core material,

magnetic saturation, temperature, physical size and cost

(usually the primary concern).

(3.2)

D t

DEC

+ Lo @ D I ń(V

)

OUT

O

For typical processor applications with output voltages

less than half the input voltage, the current will be increased

much more quickly than it can be decreased. Thus, it may be

more difficult for the converter to stay within the regulation

limits when the load is removed than when it is applied and

excessive overshoot may result.

In general, the output inductance value should be

electrically and physically as small as possible to provide the

best transient response at minimum cost. If a large

inductance value is used, the converter will not respond

quickly to rapid changes in the load current. On the other

hand, too low an inductance value will result in very large

ripple currents in the power components (MOSFETs,

capacitors, etc.) resulting in increased dissipation and lower

converter efficiency. Increased ripple currents force the

designer to use higher rated MOSFETs, oversize the thermal

solution, and use more, higher rated input and output

capacitors, adversely affecting converter cost.

One method of calculating an output inductor value is to

size the inductor to produce a specified maximum ripple

current in the inductor. Lower ripple currents will result in

less core and MOSFET losses and higher converter

efficiency. Equation 3 may be used to calculate the

minimum inductor value to produce a given maximum

ripple current (a ) per phase. The inductor value calculated

by this equation is a minimum because values less than this

will produce more ripple current than desired. Conversely,

higher inductor values will result in less than the selected

maximum ripple current.

The output voltage ripple can be calculated using the

output inductor value derived in this Section (Lo

), the

MIN

number of output capacitors (N ) and the per

OUT,MIN

capacitor ESR determined in the previous Section:

V

+ (ESR per cap ń N

) @

OUT,MIN

(4)

OUT,P−P

Ǌ

ǋ

)

OUT MIN SW

(V * #Phases @ V

IN

) @ D ń (Lo

@ f

This formula assumes steady−state conditions with no

more than one phase on at any time. The second term in

Equation 4 is the total ripple current seen by the output

capacitors. The total output ripple current is the “time

summation” of the four individual phase currents that are 90

degrees out−of−phase. As the inductor current in one phase

ramps upward, current in the other phase ramps downward

and provides a canceling of currents during part of the

switching cycle. Therefore, the total output ripple current

and voltage are reduced in a multi−phase converter.

4. Input Capacitor Selection

The choice and number of input capacitors is primarily

determined by their voltage and ripple current ratings. The

designer must choose capacitors that will support the worst

case input voltage with adequate margin. To calculate the

number of input capacitors, one must first determine the

total RMS input ripple current. To this end, begin by

calculating the average input current to the converter:

(3)

(V * V

IN

a @ I

O,MAX

) @ V

OUT

@ V @ f )

IN SW

OUT

Lo

MIN

+

(

a is the ripple current as a percentage of the maximum

output current per phase (a = 0.15 for ±15%, a = 0.25 for

±25%, etc.). If the minimum inductor value is used, the

inductor current will swing ± a % about its value at the

center. Therefore, for a four−phase converter, the inductor

must be designed or selected such that it will not saturate

(5)

I

+ I @ Dńh

O,MAX

IN,AVG

where:

D is the duty cycle of the converter, D = V

h is the specified minimum efficiency;

/V ;

OUT IN

I

is the maximum converter output current.

O,MAX

with a peak current of (1 + a ) I

/4.

O,MAX

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NCP5316

The input capacitors will discharge when the control FET

is ON and charge when the control FET is OFF as shown in

Figure 23.

In general, capacitor manufacturers require derating to the

specified ripple−current based on the ambient temperature.

More capacitors will be required because of the current

derating. The designer should know the ESR of the input

capacitors. The input capacitor power loss can be calculated

from:

D I

C,IN

= I

− I

C,MAX C,MIN

I

C,MAX

I

C,MIN

2

+ I @ ESR_per_capacitorńN

CIN,RMS IN

(13)

P

CIN

t

T/4

ON

0 A

Low ESR capacitors are recommended to minimize losses

and reduce capacitor heating. The life of an electrolytic

capacitor is reduced 50% for every 10°C rise in the

capacitor’s temperature.

FET Off,

Caps Charging

−I

IN,AVG

FET On,

Caps Discharging

5. Input Inductor Selection

The use of an inductor between the input capacitors and

the power source will accomplish two objectives. First, it

will isolate the voltage source and the system from the noise

generated in the switching supply. Second, it will limit the

inrush current into the input capacitors at power up. Large

inrush currents reduce the expected life of the input

capacitors. The inductor’s limiting effect on the input

current slew rate becomes increasingly beneficial during

load transients.

The worst case input current slew rate will occur during

the first few PWM cycles immediately after a step−load

change is applied as shown in Figure 24. When the load is

applied, the output voltage is pulled down very quickly.

Current through the output inductors will not change

instantaneously, so the initial transient load current must be

conducted by the output capacitors. The output voltage will

step downward depending on the magnitude of the output

Figure 23. Input Capacitor Current for a

Four−Phase Converter

The following equations will determine the maximum and

minimum currents delivered by the input capacitors:

(6)

(7)

I

+ I

ńh * I

Lo,MAX

C,MAX

IN,AVG

ńh * I

Lo,MIN IN,AVG

I

+ I

C,MIN

I

is the maximum output inductor current:

Lo,MAX

(8)

(9)

I

+ I

O,MAX

ń

f ) D I ń2

Lo

Lo,MAX

where f is the number of phases in operation.

is the minimum output inductor current:

I

Lo,MIN

I

+ I

O,MAX

ń

f * D I ń2

Lo

Lo,MIN

current (I

), the per capacitor ESR of the output

DI is the peak−to−peak ripple current in the output

O,MAX

Lo

capacitors (ESR

) and the number of the output

OUT

inductor of value Lo:

capacitors (N

) as shown in Figure 24. Assuming the load

OUT

(10)

D I + (V * V

Lo IN

) @ Dń(Lo @ f )

OUT SW

current is shared equally between all phases, the output

voltage at full transient load will be:

For the four−phase converter, the input capacitor(s) RMS

current is then:

(14)

V

+

OUT,FULL−LOAD

V

(11)

2

I

+ [4D @ (I

C,MIN

) I

C,MIN

@

D I

C,IN

* (I

O,MAX

ń

f

)

@

E

S

R

ńN

OUT OUT

CIN,RMS

OUT,NO−LOAD

2

1ń2

@ (1 * 4D)]

)

D I

C,IN

ń3) ) I

IN,AVG

When the control MOSFET (Q1 in Figure 24) turns ON,

the input voltage will be applied to the opposite terminal of

the output inductor (the SWNODE). At that instant, the

voltage across the output inductor can be calculated as:

Select the number of input capacitors (N ) to provide the

IN

RMS input current (I

) based on the RMS ripple

CIN,RMS

current rating per capacitor (I

):

RMS,RATED

(12)

N

+ I

ńI

IN

CIN,RMS RMS,RATED

(15)

D

V

+

V

*

V

Lo

IN

OUT,FULL−LOAD

OUT,NO−LOAD

For a four−phase converter with perfect efficiency (h = 1),

the worst case input ripple−current will occur when the

converter is operating at a 12.5% duty cycle. At this

operating point, the parallel combination of input capacitors

must support an RMS ripple current equal to 12.5% of the

converter’s DC output current. At other duty cycles, the

ripple−current will be less. For example, at a duty cycle of

either 6% or 19%, the four−phase input ripple−current will

be approximately 10% of the converter’s DC output current.

V

* V

+

IN

) (I

ń

f

)

@

E

S

R

ńN

OUT OUT

O,MAX

The differential voltage across the output inductor will

cause its current to increase linearly with time. The slew rate

of this current can be calculated from:

dI ńdt + D V ńLo

Lo Lo

(16)

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22

NCP5316

SWNODE

Q2

V

OUT

MAX dI/dt occurs in

first few PWM cycles.

I

Lo

Li

Vi(t = 0) = 12 V

Q1

Vo(t = 0) = 1.480 V

Li

Lo

470 nH

V

Ci

+

N

× Ci

N

× Co

Ci

Co

Vi

12 V

+

−

60 u(t)

ESR /N

Co Co

Ci Ci

Figure 24. Calculating the Input Inductance

6. MOSFET & Heatsink Selection

Current changes slowly in the input inductor so the input

capacitors must initially deliver the vast majority of the

input current. The amount of voltage drop across the input

Power dissipation, package size and thermal requirements

drive MOSFET selection. To adequately size the heat sink,

the design must first predict the MOSFET power

dissipation. Once the dissipation is known, the heat sink

thermal impedance can be calculated to prevent the

specified maximum case or junction temperatures from

being exceeded at the highest ambient temperature. Power

dissipation has two primary contributors: conduction losses

and switching losses. The control or upper MOSFET will

display both switching and conduction losses. The

synchronous or lower MOSFET will exhibit only

conduction losses because it switches into nearly zero

voltage. However, the body diode in the synchronous

MOSFET will suffer diode losses during the non−overlap

time of the gate drivers.

capacitors (DV ) is determined by the number of input

Ci

capacitors (N ), their per capacitor ESR (ESR ) and the

IN

current in the output inductor according to:

(17)

D V + ESR ńN dl @ ńdt @ Dńf

Ci IN IN Lo

SW

Before the load is applied, the voltage across the input

inductor (V ) is very small and the input capacitors charge

Li

to the input voltage V . After the load is applied, the voltage

IN

drop across the input capacitors, DV , appears across the

Ci

input inductor as well. Knowing this, the minimum value of

the input inductor can be calculated from:

(18)

+ V ń dI ńdt

Li IN MAX

Li

MIN

For the upper or control MOSFET, the power dissipation

can be approximated from:

+

D V ń dI ńdt

Ci IN MAX

dI /dt

rate.

is the maximum allowable input current slew

(19)

2

IN MAX

P

+ (I

@ R

)

DS(on)

D,CONTROL

RMS,CNTL

@ Q ńI @ V @ f

) (I

)

Lo,MAX

switch g IN SW

The input inductance value calculated from Equation 18

is relatively conservative. It assumes the supply voltage is

very “stiff” and does not account for any parasitic elements

that will limit dI/dt such as stray inductance. Also, the ESR

values of the capacitors specified by the manufacturer’s data

sheets are worst case high limits. In reality, input voltage

“sag,” lower capacitor ESRs and stray inductance will help

reduce the slew rate of the input current.

As with the output inductor, the input inductor must

support the maximum current without saturating the

inductor. Also, for an inexpensive iron powder core, such as

the −26 or −52 from Micrometals, the inductance “swing”

with DC bias must be taken into account and inductance will

decrease as the DC input current increases. At the maximum

input current, the inductance must not decrease below the

minimum value or the dI/dt will be higher than expected.

) (Q

ń2 @ V @ f

) ) (V @ Q

IN SW IN

@ f )

RR SW

oss

The first term represents the conduction or IR losses when

the MOSFET is ON while the second term represents the

switching losses. The third term is the loss associated with

the control and synchronous MOSFET output charge when

the control MOSFET turns ON. The output losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control FET. The fourth term is the loss

due to the reverse recovery time of the body diode in the

synchronous MOSFET. The first two terms are usually

adequate to predict the majority of the losses.

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NCP5316

I

is the RMS value of the trapezoidal current in

RMS,CNTL

the control MOSFET:

I

D

Ǹ

(20)

I

+ D

RMS,CNTL

2

) I )ń3]

Lo,MIN

1ń2

(21)

(22)

@ [(I

) I

@ I

Lo,MAX

Lo,MAX Lo,MIN

V

GATE

I

is the maximum output inductor current:

Lo,MAX

I

+ I

O,MAX

ń

f ) D I ń2

Lo

Lo,MAX

is the minimum output inductor current:

V

Lo,MIN

O,MAX

GS_TH

I

+ I

O,MAX

ń

f * D I ń2

Lo

Lo,MIN

is the maximum converter output current.

Q

V

DRAIN

GS1

GS2

GD

D is the duty cycle of the converter:

(23)

D + V

ńV

OUT IN

Figure 25. MOSFET Switching Characteristics

DI is the peak−to−peak ripple current in the output

Lo

When the MOSFET power dissipations are known, the

designer can calculate the required thermal impedance to

maintain a specified junction temperature at the worst case

ambient operating temperature.

inductor of value L :

o

(24)

D I + (V * V

Lo IN

) @ Dń(Lo @ f )

OUT SW

R

DS(on)

is the ON resistance of the MOSFET at the

applied gate drive voltage.

is the post gate threshold portion of the

(28)

q

T

t (T * T )ńP

J A D

Q

switch

gate−to−sourcecharge plus the gate−to−drain charge. This

may be specified in the data sheet or approximated from the

gate−charge curve as shown in the Figure 25.

(25)

where:

q

i

s

t

h

e

t

o

t

a

l

t

h

e

r

m

a

l

i

m

p

e

d

a

n

c

e

(

q

+

q

)

;

T

JC

SA

q

is the junction−to−case thermal impedance of the

JC

MOSFET;

is the sink−to−ambient thermal impedance of the

Q

+ Q

) Q

gs2 gd

switch

q

SA

I is the output current from the gate driver IC.

g

heatsink assuming direct mounting of the MOSFET (no

thermal “pad” is used);

V

IN

is the input voltage to the converter.

f

Q

is the switching frequency of the converter.

is the MOSFET total gate charge to obtain R

sw

T

is the specified maximum allowed junction

temperature;

J

;

DS(on)

G

commonly specified in the data sheet.

V is the gate drive voltage.

T is the worst case ambient operating temperature.

A

g

For TO−220 and TO−263 packages, standard FR−4

copper clad circuit boards will have approximate thermal

resistances (q ) as shown below:

Q

is the reverse recovery charge of the lower MOSFET.

is the MOSFET output charge specified in the data

RR

oss

SA

sheet.

For the lower or synchronous MOSFET, the power

dissipation can be approximated from:

Pad Size

Single−Sided

2

(in /mm )

0.50/323

0.75/484

1.00/645

1.50/968

1 oz. Copper

60−65°C/W

55−60°C/W

50−55°C/W

45−50°C/W

2

P

+ (I

RMS,SYNCH

@ R

)

DS(on)

D,SYNCH

) (Vf

(26)

@ I

diode O,MAX

ń2 @ t_nonoverlap @ f )

SW

where:

Vf

is the forward voltage of the MOSFET’s intrinsic

diode

diode at the converter output current.

t_nonoverlap is the non−overlap time between the upper

and lower gate drivers to prevent cross conduction.

This time is usually specified in the data sheet for the

control IC.

The first term represents the conduction or IR losses when

the MOSFET is ON and the second term represents the diode

losses that occur during the gate non−overlap time.

All terms were defined in the previous discussion for the

control MOSFET with the exception of:

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading and component

variations (i.e., worst case MOSFET R

). Also, the

DS(on)

inductors and capacitors share the MOSFET’s heatsinks and

will add heat and raise the temperature of the circuit board

and MOSFET. For any new design, it is advisable to have as

much heatsink area as possible. All too often, new designs are

found to be too hot and require re−design to add heatsinking.

Ǹ

(27)

I

+ 1 * D

RMS,SYNCH

2

2 1ń2

) I )ń3]

Lo,MIN

@ [(I

Lo,MAX

) I

@ I

Lo,MAX Lo,MIN

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NCP5316

+ −

R

CS1

CS1P

+

−

G

+

−

COMP

VID − 20 mV

S

L1

0 A

VDRP

C

CS1

Error

Amp

CS1N

CSxP

R

FB

DRP

CSx

+

−

V

DRP

= VID

V

FB

= VID − 20 mV

V

CORE

Lx

0 A

G

VDRP

C

CSx

I

= 0

I

FB

= 0

DRP

CSxN

V

CORE

= VID + IBIAS

w R

VFB

FB

Figure 26. AVP Circuitry at No−Load

+ −

VID − 20 mV

R

CS1

CS1P

+

−

COMP

S

−

G

L1

VDRP

Error

Amp

I

/2

MAX

C

CS1

CS1N

CSxP

R

FB

DRP

R

CSx

+

−

V

I

= VID +

V

= VID − 20 mV V

CORE

DRP

MAX

FB

• R • G

L

VDRP

Lx

G

VDRP

I

/n

MAX

C

CSx

I

FB

CSxN

DRP

I

= I

• R • G /R

VDRP DRP

DRP

FBK

MAX

DRP

L

V

CORE

= VID − I

w R

FB

DRP

w R w G

w R /R

FB DRP

MAX

L

VDRP

Figure 27. AVP Circuitry at Full−Load

7. Adaptive Voltage Positioning

causes the voltage at the V pin to rise, reducing the output

FB

Two resistors program the Adaptive Voltage Positioning

(AVP): R and R . These components form a resistor

voltage. Figure 28 shows the DC effect of AVP, given an

appropriate resistor ratio.

FB

DRP

divider, shown in Figures 26 and 27, between V , V

,

DRP FB

0

and V

.

OUT

Resistor R is connected between V

of the controller. At no load, this resistor will conduct the

very small internal bias current of the V pin. Therefore

and the V pin

FB

OUT

−0.02

Spec Max

FB

−0.04

VID − V

OUT

V

FB

should be kept below 10 kW to avoid output voltage

−0.06

−0.08

−0.10

−0.12

−0.14

error due to the input bias current. If the R resistor is kept

FB

small, the V bias current can be ignored.

FB

Resistor R

is connected between the V and V

DRP FB

DRP

Spec Min

pins of the controller. At no load, these pins should be at an

equal potential, and no current should flow through R . In

DRP

reality, the bias current coming out of the V

pin is likely

DRP

to have a small positive voltage with respect to V . This

FB

0

10

20

30

(A)

40

50

60

current produces a small decrease in output voltage at no

I

load, which can be minimized by keeping the R

resistor

OUT

DRP

below 30 kW. As load current increases, the voltage at the

pin rises. The ratio of the R and R resistors

Figure 28. The DC Effects of AVP vs. Load

V

DRP

FB

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NCP5316

Figure 29. V_DRPTuning Waveforms. The RC Time

Constant of the Current Sense Network Is Too Long

(Slow): V_DRPand V_OUTRespond Too Slowly.

Figure 30. V_DRPTuning Waveforms. The RC Time

Constant of the Current Sense Network Is Too Short

(Fast): V_DRPand V_OUTBoth Overshoot.

(31)

R

@ C

+ Loń(R

)

sense

To choose components, recall that the two resistors R

FB

CSx

and R

form a voltage divider. Select the appropriate

DRP

resistor ratio to achieve the desired loadline. At no load, the

output voltage is positioned 20 mV below the DAC output

setting. The output voltage droop will follow the equation:

R R

L FB

(29)

R

+ g @

DRP

R

LL

where:

g = gain of the current sense amplifiers (V/V);

R

= resistance of the sense element (mW);

= load line resistance (mW).

SENSE

LL

It is easiest to select a value for R and then evaluate the

FB

equation to find R . R is simply the desired output

DRP LL

voltage droop divided by the output current. If a sense

resistor is used to detect inductor current, then R

will

SENSE

be the value of the sense resistor. If inductor sensing is used,

will be the resistance of the inductor, assuming that

the current sense network equation (eq. 30) is valid. Refer to

the discussion on Current Sensing for further information.

Figure 31. V_DRPTuning Waveforms. The RC Time

Constant of the Current Sense Network Is Optimal:

R

SENSE

V

_DRPand V_OUTRespond to the Load Current Quickly

Without Overshooting.

8. Current Sensing

This will provide an adequate starting point for R

and

Current sensing is used to balance current between

different phases, to limit the maximum phase current and to

limit the maximum system current. Since the current

information, sensed across the inductor, is a part of the

control loop, better stability is achieved if the current

information is accurate and noise−free. The NCP5316

introduces a novel feature to achieve the best possible

performance: differential current sense amplifiers.

Two sense lines are routed for each phase, as shown in

Figure 27.

CSx

C

. After the converter is constructed, the value of R

CSx

(and/or C ) should be fine−tuned in the lab by observing

CSx

the V

signal during a step change in load current. Tune

DRP

the R

C

CSx

network by varying R

to provide a

CSx

“square−wave” at the V

output pin with maximum rise

DRP

time and minimal overshoot as shown in Figure 31.

9. Error Amplifier Tuning

After the steady−state (static) AVP has been set and the

current sense network has been optimized, the Error

Amplifier must be tuned. The gain of the Error Amplifier

should be adjusted to provide an acceptable transient

response by increasing or decreasing the Error Amplifier’s

For inductive current sensing, choose the current sense

network (R , C , x = 1, 2, 3, 4, 5 or 6) to satisfy

CSx CSx

(30)

R

@ C

+ Loń(R ) R

)

PCB

CSx

L

feedback capacitor (C

loop will vary directly with the gain of the error amplifier.

). The bandwidth of the control

For resistive current sensing, choose the current sense

network (R , C , x = 1, 2, 3, 4, 5 or 6) to satisfy

AMP

CSx CSx

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NCP5316

If C

is too large, the loop gain/bandwidth will be low,

AMP

the COMP pin will slew too slowly and the output voltage

will overshoot as shown in Figure 32. On the other hand, if

C

AMP

is too small, the loop gain/bandwidth will be high, the

COMP pin will slew very quickly and overshoot will occur.

Integrator “wind up” is the cause of the overshoot. In this

case, the output voltage will transition more slowly because

COMP spikes upward as shown in Figure 33. Too much loop

gain/bandwidth increases the risk of instability. In general,

one should use the lowest loop gain/bandwidth possible to

achieve acceptable transient response. This will insure good

stability. If C

is optimal, the COMP pin will slew

AMP

quickly but not overshoot and the output voltage will

monotonically settle as shown in Figure 35.

After the control loop is tuned to provide an acceptable

transient response, the steady−state voltage ripple on the

COMP pin should be examined. When the converter is

operating at full steady−state load, the peak−to−peak voltage

Figure 33. The Value of C_AMPIs Too Low and the

Loop Gain/Bandwidth Too High. COMP Moves Too

Quickly, Which Is Evident from the Small Spike in Its

Voltage When the Load Is Applied or Removed. The

Output Voltage Transitions More Slowly Because of

the COMP Spike.

ripple (V ) on the COMP pin should be less than 20 mV

PP

as shown in Figure 34. Less than 10 mV is ideal. Excessive

PP

ripple on the COMP pin will contribute to jitter.

Figure 34. At Full−Load the Peak−to−Peak Voltage

Ripple on the COMP Pin Should Be Less than 20 mV

for a Well−Tuned/Stable Controller. Higher COMP

Voltage Ripple Will Contribute to Output Voltage Jitter.

Figure 32. The Value of C_AMPIs Too High and the

Loop Gain/Bandwidth Too Low. COMP Slews Too

Slowly Which Results in Overshoot in V_OUT

.

Figure 35. The Value of C_AMPIs Optimal. COMP Slews

Quickly Without Spiking or Ringing. V_OUTDoes Not

Overshoot and Monotonically Settles to Its Final Value.

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27

NCP5316

10. Current Limit Setting

V

IO

can be calculated as

When the output of the current sense amplifier (COx in the

V

+ n @ I @ R @ g @ 3.3

F L L

IO

block diagram) exceeds the voltage on the I

will latch off. For inductive sensing, the I

pin, the part

pin voltage

LIM

where:

= the number of phases;

I = inductor current (A);

R = sense element resistance (W);

g = current sense to IO pin gain.

LIM

n

F

should be set based on the inductor’s maximum resistance

(R ). The design must consider the inductor’s

L

LMAX

L

resistance increase due to current heating and ambient

temperature rise. Also, depending on the current sense

points, the circuit board may add additional resistance. In

general, the temperature coefficient of copper is +0.39% per

The user may easily set the phase and module current

limits at this point. This limit is programmed by a resistor

°C. If using a current sense resistor (R ), the I

SENSE

divider from V , as shown in Figure 37.

LIM

REF

voltage should be set based on the maximum value of the

sense resistor.

V

REF

Since under transient conditions, a single phase may see

a very high positive or negative current for mere

microseconds at a time, the user may set a limit to the

maximum phase current. The phase current limit prevents an

individual phase from conducting too much current in either

R1

R2

R3

R4

I

PLIM

LIM

the positive or negative direction. The IP

set this threshold.

pin is used to

LIM

The IO pin provides an output signal proportional to

inductor current, which can be used for system validation

purposes as well as for current limiting. This signal is fed

back into the IC through a low−pass filter between IO and

IOF, as shown in Figure 36, so designers may customize the

response time of the current limit functions.

Figure 37. Programming the Current Limits

When the NCP5316 is powered up, V

will be 3.3 V.

REF

This allows the user to set the module and phase current

limits with the resistor divider shown above.

IO

V

R1

R1 ) R2

REF

Module Current Limit +

@

R @ g @ n

L

F

RIO

V

R3

R3 ) R4

REF

Phase Current Limit +

@

IOF

9.5 @ R

L

For convenience in component selection, as well as to

keep the V pin current below 1 mA, the designer is

CIO

REF

recommended to set R2 and R4 equal to 10 kW.

For the overcurrent protection to work properly, the

current sense time constant (RC) should be slightly larger

Figure 36. Filtering the IO Signal

than the R time constant. If the RC time constant is too fast,

L

a step load change will cause the sensed current waveform

to appear larger than the actual inductor current and will trip

the current limit at a lower level than expected.

The designer should select these values empirically. A

0.01 m F capacitor and a 20 kW resistor will prevent

inadvertent current limit triggering in many cases.

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28

NCP5316

PACKAGE DIMENSIONS

48−PIN QFN, 7 y 7

MN SUFFIX

CASE 485K−02

ISSUE B

−X−

A

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

−Y−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.30 AND 0.35 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. 485K−01 OBSOLETE, NEW STANDARD IS

485K−02.

B

MILLIMETERS

DIM MIN MAX

7.00 BSC

INCHES

MIN MAX

0.276 BSC

2 PL

A

B

C

D

E

F

0.15 (0.006) T

2 PL

0.80

0.23

5.26

1.00 0.031 0.039

0.28 0.009 0.011

5.46 0.207 0.215

0.15 (0.006) T

TOP VIEW

G

J

0.50 BSC

0.20 REF

0.020 BSC

0.008 REF

K

L

M

N

R

P

0.00

0.35

2.85

0.60

0.05 0.000 0.002

0.45 0.014 0.018

2.95 0.112 0.116

0.80 0.024 0.031

J

0.10 (0.004) T

R

C

SEATING

PLANE

−T−

0.08 (0.0031)

T

0.42 REF

0.165 REF

SIDE VIEW

K

E

M

EXPOSED PAD

L

48 PL

P

4 PL

13

24

12

25

F

N

1

36

48

37

48 PL NOTE 3

D

G

M

0.10 (0.004)

T X Y

BOTTOM VIEW

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29

NCP5316

PACKAGE DIMENSIONS

LQFP−48

FTB SUFFIX

CASE 932−02

ISSUE E

4X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

0.200 AB T−U

Z

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT

DATUM PLANE AB.

DETAIL Y

P

9

A

A1

48

37

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

1

36

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350.

T

U

B

V

AE

B1

V1

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

12

25

MILLIMETERS

13

24

DIM MIN

MAX

7.000 BSC

3.500 BSC

Z

A

A1

B

S1

7.000 BSC

3.500 BSC

T, U, Z

B1

C

1.400

1.600

0.270

1.450

0.230

S

D

0.170

1.350

0.170

DETAIL Y

4X

E

F

0.200 AC T−U

Z

G

H

0.500 BSC

0.050

0.090

0.500

1

0.150

0.200

0.700

5

J

K

L

_

0.080 AC

M

N

12 REF

_

G

AB

AC

0.090

0.160

P

0.250 BSC

R

0.150

0.250

S

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

S1

V

V1

W

AA

AD

_

M

BASE METAL

TOP & BOTTOM

R

N

J

E

C

F

D

M

0.080

AC T−U Z

SECTION AE−AE

W

H

_

L

K

DETAIL AD

AA

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30

NCP5316

Notes

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31

NCP5316

2

V

is a trademark of Switch Power, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

NCP5316/D

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32


型号：	NCP5316
厂家：	ONSEMI
描述：	Four/Five/Six-Phase Buck CPU Controller 四/五/六相降压控制器的CPU 控制器
文件：	总32页 (文件大小：358K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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