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NCP5318 [ONSEMI]

Two/Three/Four−Phase Buck CPU Controller; 二/三/四相降压控制器的CPU
NCP5318
型号： NCP5318
厂家： ONSEMI    ONSEMI
描述：

Two/Three/Four−Phase Buck CPU Controller
二/三/四相降压控制器的CPU

控制器
文件： 总31页 (文件大小：374K)
中文：  中文翻译
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NCP5318  
Two/Three/Four−Phase  
Buck CPU Controller  
The NCP5318 provides full−featured and flexible control  
conforming to the Intel® VRM 10.1 specification for  
high−performance CPUs. The IC can be programmed as a two−,  
three− or four−phase buck controller, and the per−phase switching  
frequency can be as high as 1.0 MHz. Combined with external gate  
drivers and power components, the controller implements a compact,  
highly integrated multi−phase buck converter.  
http://onsemi.com  
MARKING  
DIAGRAM  
2
Enhanced V ™ control inherently compensates for variations in  
both line and load, and achieves current sharing between phases. This  
control scheme provides fast transient response, reducing the need for  
large banks of output capacitors and higher switching frequency.  
NCP5318  
AWLYYWWG  
LQFP−32  
FT SUFFIX  
CASE 873A  
Features  
• Switching Regulator Controller  
♦ Programmable 2/3/4 Phase Operation  
♦ Lossless Current Sensing  
A
= Assembly Location  
WL  
YY  
WW  
G
= Wafer Lot  
= Year  
2
♦ Enhanced V Control Method Provides Fast Transient Response  
♦ Programmable Up to 1.0 MHz Switching Frequency Per Phase  
♦ Programmable Adaptive Voltage Positioning  
♦ Programmable Soft−Start Time  
= Work Week  
= Pb−Free Package  
• Current Sharing  
PIN CONNECTIONS  
♦ Differential Current Sense Pins for Each Phase  
♦ Current Sharing Within 10% Between Phases  
(Top View)  
• Protection Features  
♦ Programmable Latching Overcurrent Protection  
♦ “111110” and “111111” DAC Code Fault  
♦ Latched Overvoltage Protection  
♦ Undervoltage Lockout  
♦ External Enable Control  
V
V
V
I
R
V
ID2  
ID3  
ID4  
LIM  
OSC  
CC  
♦ Three−State MOSFET Driver Control through DRVON Signal  
PWRLS  
GATE1  
• System Power Management  
V
GATE2  
GATE3  
GATE4  
GND  
FFB  
♦ 6−Bit DAC with 0.5% Tolerance Compatible with VRM 10.1  
Specification  
SS  
PWRGD  
DRVON  
♦ Programmable Lower Power Good Threshold  
♦ Power Good Output with Delay  
♦ Pre−set No Load Offset Voltage  
• Pb−Free Package is Available*  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
NCP5318FTR2  
LQFP−32  
2000 Tape & Reel  
2000 Tape & Reel  
NCP5318FTR2G LQFP−32  
(Pb−Free)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number  
June, 2006 − Rev. 4  
NCP5318/D  
NCP5318  
12V_FILTER  
CVCC2  
4.7mF  
C4  
4.7mF  
+12V  
D1  
BAT54HT1  
12V_FILTER  
+3.3V  
C3  
0.1mF  
RVCC  
10  
CVCC1  
0.1mF  
R1  
2.2  
NCP5355  
1x NTD60N02RT4  
3
2
1
7
8
BST  
1.5K  
6
5
4
280nH  
TG  
DRN  
BG  
VS  
EN  
CO  
22  
17  
U1  
BI Tech  
30  
31  
32  
1
VID5  
VID0  
VID5 VCC  
VID0  
GND  
PGND  
R2  
2.2  
HM00−02702  
21  
VID1  
C1  
4.7mF  
VID1  
RS1  
3.4K  
GATE1  
VID2  
VID2  
2
VID3  
VID3  
2x NTD85N02RT4  
3
25  
26  
C2  
4.7nF  
VID4  
CS1P  
CS1N  
VID4  
29  
VID_PWRGD  
VCC_PWRGD  
ENABLE  
7
PWRGD  
SGND  
9
4
CS1  
0.1mF  
20  
RS 15K  
GATE2  
PWRLS  
27  
28  
12V_FILTER  
12V_FILTER  
CS2P  
CS2N  
NCP5318FTR2  
RP  
20K  
5
VFFB  
VFB  
19  
GATE3  
11  
3
RF2*  
15K NTC  
RF1  
2K  
16  
15  
BST  
2
6
5
4
CS3P  
CS3N  
TG  
1
VS  
EN  
CO  
DRN  
7
RFB  
1.5K  
BG  
8
18  
PGND  
GATE4  
14  
13  
RDRP  
3.25K  
CS4P  
CS4N  
10  
12  
VDRP  
RD1 1K  
RF  
OPEN  
CD1  
1nF  
8
DRVON  
12V_FILTER  
12V_FILTER  
COMP  
ILIM  
ROSC  
23  
SS  
6
CF  
OPEN  
24  
CA1  
TBD  
RA1  
TBD  
RLIM1  
18.2K  
CSS  
0.1mF  
3
BST  
2
6
TG  
1
VS  
5
4
DRN  
7
EN  
CO  
BG  
8
CA2  
4.7nF  
RLIM2  
35.5K  
PGND  
165A Trip @  
1.25mW  
2x2 HEADER  
12V_FILTER  
1 mH  
1
3
4
BI Tech  
2
12V_FILTER  
12V_FILTER  
+
PA0343−1  
5x 1000mF  
SANYO  
16SA1000M  
3
BST  
2
6
5
4
TG  
1
VS  
EN  
CO  
SIGNAL  
GND  
POWER  
GND  
DRN  
7
RGND  
0
BG  
8
PGND  
* RF2 LOCATED NEAR OUTPUT INDUCTORS  
VCCP  
10x 560mF  
SANYO  
SEPC560M  
CO2  
16x 22mF  
+
VSSP  
CPU GND  
Figure 1. 4−Phase Solution for VRM10.1: 120 A max, 101 A thermals, 1.4 Vo, 400 kHz, 1 mW LL  
http://onsemi.com  
2
NCP5318  
MAXIMUM RATINGS  
Rating  
Value  
Unit  
°C  
Operating Junction Temperature  
150  
Lead Temperature Soldering, Reflow (Note 1)  
NCP5318FTR2  
NCP5318FTR2G  
230 peak  
260 peak  
°C  
Storage Temperature Range  
−65 to 150  
°C  
ESD Susceptibility: Human Body Model  
JEDEC Moisture Sensitivity Level  
2.0  
kV  
NCP5318FTR2  
NCP5318FTR2G  
1
3
−
−
Package Thermal Resistance: R  
52  
°C/W  
q
JA  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. 60 second maximum above 183°C.  
MAXIMUM RATINGS  
Pin Number  
Pin Symbol  
−V  
V
V
I
I
SINK  
MAX  
MIN  
SOURCE  
1−3, 30−32  
V
18 V  
7.0 V  
7.0 V  
7.0 V  
18 V  
7.0 V  
1.0 V  
7.0 V  
7.0 V  
7.0 V  
18 V  
18 V  
18 V  
18 V  
−
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−1.0 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−
1.0 mA  
1.0 mA  
1.0 mA  
ID0  
ID5  
4
5
PWRLS  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
V
1.0 mA  
FFB  
6
SS  
1.0 mA  
7
PWRGD  
DRVON  
SGND  
20 mA  
8
1.0 mA  
9
−
10  
11  
12  
13  
14  
15  
16  
17  
18−21  
22  
23  
24  
25  
26  
27  
28  
29  
V
1.0 mA  
DRP  
V
1.0 mA  
FB  
COMP  
CS4N  
1.0 mA  
1.0 mA  
CS4P  
1.0 mA  
CS3N  
1.0 mA  
CS3P  
1.0 mA  
GND  
0.4 A 1.0 ms, 100 mA DC  
−
GATE4−GATE1  
18 V  
18 V  
7.0 V  
7.0 V  
18 V  
18 V  
18 V  
18 V  
18 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
−0.3 V  
0.1 A 1.0 ms, 25 mA DC  
0.1 A 1.0 ms, 25 mA DC  
0.4 A 1.0 ms, 100 mA DC  
1.0 mA  
V
−
CC  
R
OSC  
I
LIM  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
1.0 mA  
CS1P  
CS1N  
1.0 mA  
1.0 mA  
CS2P  
1.0 mA  
CS2N  
1.0 mA  
ENABLE  
1.0 mA  
http://onsemi.com  
3
NCP5318  
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; V = 12 V; C  
= 100 pF, C  
= 0.01 mF,  
A
CC  
GATEx  
COMP  
C
= 0.1 mF, C  
= 0.1 mF, R  
= 95.3 kW, V(I ) = 1.0 V, DAC Code 010100; unless otherwise noted)  
SS  
VCC  
ROSC LIM  
VOLTAGE IDENTIFICATION (VID)  
Voltage Identification Bits  
(Connect V to COMP, measure COMP)  
Nominal  
Voltage  
(V)  
Min  
Typ  
Max  
FB  
V
V
V
V
V
V
−0.5%  
0.8144  
0.8268  
0.8393  
0.8517  
0.8642  
0.8766  
0.8890  
0.9015  
0.9139  
0.9263  
0.9388  
0.9512  
0.9637  
0.9761  
0.9885  
1.0010  
1.0134  
1.0258  
1.0383  
1.0507  
1.0632  
No Load  
0.8185  
0.8310  
0.8435  
0.8560  
0.8685  
0.8810  
0.8935  
0.9060  
0.9185  
0.9310  
0.9435  
0.9560  
0.9685  
0.9810  
0.9935  
1.0060  
1.0185  
1.0310  
1.0435  
1.0560  
1.0685  
+0.5%  
0.8226  
0.8352  
0.8477  
0.8603  
0.8728  
0.8854  
0.8980  
0.9105  
0.9231  
0.9357  
0.9482  
0.9608  
0.9733  
0.9859  
0.9985  
1.0110  
1.0236  
1.0362  
1.0487  
1.0613  
1.0738  
Units  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID4  
ID3  
ID2  
ID1  
ID0  
ID5  
0
1
0
1
0
0
0.8375  
0.8500  
0.8625  
0.8750  
0.8875  
0.9000  
0.9125  
0.9250  
0.9375  
0.9500  
0.9625  
0.9750  
0.9875  
1.0000  
1.0125  
1.0250  
1.0375  
1.0500  
1.0625  
1.0750  
1.0875  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF  
OFF  
1.1000  
1.1125  
1.1250  
1.1375  
1.1500  
1.1625  
1.1750  
1.1875  
1.2000  
1.2125  
1.2250  
1.2375  
1.0756  
1.0880  
1.1005  
1.1129  
1.1253  
1.1378  
1.1502  
1.1627  
1.1751  
1.1875  
1.2000  
1.2124  
1.0810  
1.0935  
1.1060  
1.1185  
1.1310  
1.1435  
1.1560  
1.1685  
1.1810  
1.1935  
1.2060  
1.2185  
1.0864  
1.0990  
1.1115  
1.1241  
1.1367  
1.1492  
1.1618  
1.1743  
1.1869  
1.1995  
1.2120  
1.2246  
*VID Code is for reference only.  
†V No Load is the input to the error amplifier.  
OUT  
http://onsemi.com  
4
NCP5318  
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; V = 12 V; C  
= 100 pF, C  
= 0.01 mF,  
A
CC  
GATEx  
COMP  
C
= 0.1 mF, C  
= 0.1 mF, R  
= 95.3 kW, V(I ) = 1.0 V, DAC Code 010100; unless otherwise noted)  
SS  
VCC  
ROSC LIM  
VOLTAGE IDENTIFICATION (VID) (continued)  
Voltage Identification Bits  
Nominal  
Voltage  
(V)  
Min  
Typ  
Max  
(Connect V to COMP, measure COMP)  
FB  
V
V
V
V
V
V
−0.5%  
1.2248  
1.2373  
1.2497  
1.2622  
1.2746  
1.2870  
1.2995  
1.3119  
1.3243  
1.3368  
1.3492  
1.3617  
1.3741  
1.3865  
1.3990  
1.4114  
1.4238  
1.4363  
1.4487  
1.4612  
1.4736  
1.4860  
1.4985  
1.5109  
1.5233  
1.5358  
1.5482  
1.5607  
1.5731  
No Load  
1.2310  
1.2435  
1.2560  
1.2685  
1.2810  
1.2935  
1.3060  
1.3185  
1.3310  
1.3435  
1.3560  
1.3685  
1.3810  
1.3935  
1.4060  
1.4185  
1.4310  
1.4435  
1.4560  
1.4685  
1.4810  
1.4935  
1.5060  
1.5185  
1.5310  
1.5435  
1.5560  
1.5685  
1.5810  
+0.5%  
1.2372  
1.2497  
1.2623  
1.2748  
1.2874  
1.3000  
1.3125  
1.3251  
1.3377  
1.3502  
1.3628  
1.3753  
1.3879  
1.4005  
1.4130  
1.4256  
1.4382  
1.4507  
1.4633  
1.4758  
1.4884  
1.5010  
1.5135  
1.5261  
1.5387  
1.5512  
1.5638  
1.5763  
1.5889  
Units  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID4  
ID3  
ID2  
ID1  
ID0  
ID5  
1
1
0
0
0
1
1.2500  
1.2625  
1.2750  
1.2875  
1.3000  
1.3125  
1.3250  
1.3375  
1.3500  
1.3625  
1.3750  
1.3875  
1.4000  
1.4125  
1.4250  
1.4375  
1.4500  
1.4625  
1.4750  
1.4875  
1.5000  
1.5125  
1.5250  
1.5375  
1.5500  
1.5625  
1.5750  
1.5875  
1.6000  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*VID Code is for reference only.  
†V No Load is the input to the error amplifier.  
OUT  
http://onsemi.com  
5
NCP5318  
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; V = 12 V; C  
= 100 pF, C  
= 0.01 mF,  
A
CC  
GATEx  
COMP  
C
= 0.1 mF, C  
= 0.1 mF, R  
= 95.3 kW, V(I ) = 1.0 V, DAC Code 010100; unless otherwise noted)  
SS  
VCC  
ROSC LIM  
Characteristic  
Test Conditions  
Min  
Typ  
Max  
Unit  
VID Inputs  
Input Threshold  
VID Pin Current  
V
V
, V , V , V , V , V  
400  
−
600  
0.2  
20  
−
800  
1.0  
40  
mV  
mA  
ID5  
ID4  
ID3  
ID2  
ID1  
ID0  
, V , V , V , V , V  
= 0 V  
ID5  
ID4  
ID3  
ID2  
ID1  
ID0  
SGND Bias Current  
SGND < 300 mV, All DAC Codes  
10  
mA  
SGND Voltage Compliance Range  
Power Good  
−
−200  
300  
mV  
Upper Threshold, Offset from No Load Set Point  
Lower Threshold Constant  
Output Low Voltage  
Delay  
85  
0.475  
−
97  
0.505  
0.18  
2.0  
115  
0.525  
0.40  
4.0  
mV  
V/V  
V
PWRGDS/No Load Set Point  
V
V
= 1.0 V, I  
= 4.0 mA  
FFB  
FFB  
PWRGD  
high to PWRGD high  
1.0  
ms  
Overvoltage Protection  
OVP Threshold above VID  
Enable Input  
−
170  
215  
250  
mV  
Start Threshold  
Gates switching, SS high  
−
−
−
0.8  
−
V
V
Stop Threshold  
Gates not switching, SS low  
0.4  
100  
2.7  
7.0  
Hysteresis  
−
170  
2.9  
10  
−
mV  
V
Input Pull−Up Voltage  
Input Pull−Up Resistance  
Error Amplifier  
1.0 MW to GND  
3.3  
20  
−
kW  
V
Bias Current  
−
−
40  
40  
1.1  
72  
−
0.1  
70  
1.0  
100  
100  
1.5  
−
mA  
mA  
FB  
COMP Source Current  
COMP Sink Current  
Transconductance  
Open Loop DC Gain  
Unity Gain Bandwidth  
PSRR @ 1.0 kHz  
COMP = 0.5 V to 2.0 V  
−
70  
mA  
(Note 2)  
(Note 2)  
1.3  
80  
mmho  
dB  
C
COMP  
= 30 pF (Note 2)  
(Note 2)  
4.0  
60  
−
MHz  
dB  
−
−
COMP Max Voltage  
COMP Min Voltage  
PWM Comparators  
Minimum Pulse Width  
V
V
= 0 V  
2.4  
−
2.9  
80  
−
V
FB  
FB  
= 1.6 V  
150  
mV  
Measured from CSxP to GATEx,  
= CSxN = 0.5, COMP = 0.5 V,  
−
−
40  
40  
100  
60  
ns  
ns  
V
FB  
60 mV step between CSxP and CSxN;  
Measure at GATEx = 1.0 V (Note 2)  
Transient Response Time  
Channel Startup Offset  
Measured from CSxN to GATEx,  
COMP = 2.1 V, CSxP = CSxN = 0.5 V,  
CSxN stepped from 1.2 V to 2.0 V (Note 2)  
CSxP = CSxN = V = 0, Measure Vcomp  
when GATEx switch high  
0.35  
0.62  
175  
0.75  
V
FB  
Artificial Ramp Amplitude  
MOSFET Driver Enable (DRVON)  
Output High  
50% duty cycle  
−
−
mV  
DRVON floating  
2.3  
−
−
−
−
V
V
Output Low  
I = 100 mA  
0.2  
140  
Pull−Down Resistance  
DRVON = 1.5 V, ENABLE = 0 V,  
R = 1.5 V/I(DRVON)  
35  
70  
kW  
Source Current  
DRVON = 1.5 V  
0.5  
3.0  
6.5  
mA  
2. Guaranteed by design, not tested in production.  
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6
NCP5318  
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; V = 12 V; C  
= 100 pF, C = 0.01 mF,  
COMP  
= 95.3 kW, V(I ) = 1.0 V, DAC Code 010100; unless otherwise noted)  
A
CC  
GATEx  
C
= 0.1 mF, C  
= 0.1 mF, R  
SS  
VCC  
ROSC LIM  
Characteristic  
Test Conditions  
Min  
Typ  
Max  
Unit  
GATES  
High Voltage  
Low Voltage  
Measure GATEx, I  
= 1.0 mA  
2.25  
−
−
−
V
V
GATEx  
Measure GATEx, I  
= 1.0 mA  
0.1  
5.0  
5.0  
0.7  
10  
10  
GATEx  
Rise Time GATE  
Fall Time GATE  
Oscillator  
0.8 V < GATEx < 2.0 V, V = 10 V  
−
ns  
ns  
CC  
2.0 V > GATEx > 0.8 V, V = 10 V  
−
CC  
Switching Frequency  
R
R
= 95.3 k, 3 Phase  
= 95.3 k, 4 Phase  
276  
213  
325  
251  
374  
289  
kHz  
OSC  
OSC  
R
Voltage  
−
0.95  
100  
75  
1.02  
120  
90  
1.05  
140  
105  
−
V
OSC  
Phase Delay, 3 Phases  
Phase Delay, 4 Phases  
V
V
= CS4P = CS4N  
deg  
deg  
mV  
CC  
CC  
−
Phase Disable Threshold  
Adaptive Voltage Positioning  
− (CS4P = CS4N)  
500  
−
V
Output Voltage to DAC  
Offset  
CSxP = CSxN, V = COMP,  
−20  
0
+20  
mV  
V/V  
DRP  
OUT  
FB  
Measure V  
− COMP  
DRP  
Current Sense Amplifier to V  
(each channel separately)  
Gain  
CSxP − CSxN = 80 mV, V = COMP, Mea-  
4.37  
4.6  
4.83  
DRP  
FB  
sure V  
− COMP for 25°C < T < 70°C  
DRP  
A
V
V
Source Current  
Sink Current  
−
−
0.95  
0.2  
1.3  
0.4  
3.0  
0.6  
mA  
mA  
DRP  
DRP  
Soft−Start  
Charge Current  
−
−
−
30  
90  
44  
120  
0.9  
50  
160  
2.1  
mA  
mA  
Discharge Current  
COMP Pull−Down Current  
0.2  
mA  
Current Sensing and Overcurrent Protection  
CSxP Input Bias Current  
CSxN = CSxP = 0 V  
CSxN = CSxP = 0 V  
−
−
0.1  
0.1  
4.6  
1.0  
1.0  
5.8  
mA  
mA  
CSxN Input Bias Current  
Current Sense Amp to PWM Gain  
CSxN = 0 V, CSxP = 80 mV, Measure  
V(COMP) when GATEx switches high  
3.4  
V/V  
Current Sense Amp to PWM Bandwidth  
(Note 2)  
−
7.0  
−
MHz  
V/V  
Current Sense Amp to I  
Gain  
CSxP − CSxN = 20 mV to 60 mV, Ramp  
3.228  
3.390  
3.526  
LIM  
I
until SS goes low  
LIM  
Current Sense Amp to I  
Bandwidth  
(Note 2)  
−
2.0  
−
1.0  
5.0  
0.1  
−12  
−
−
MHz  
mV/ms  
mA  
LIM  
Current Limit Filter Slew Rate  
Input Bias Current  
(Note 2)  
13  
1.0  
58  
2.0  
I
I
= 0 V  
LIM  
LIM  
Current Sense Amp to I  
Output Offset  
T = 80°C  
−82  
0
mV  
LIM  
Current Sense Common Mode Input Range  
(Note 2)  
V
General Electrical Specifications  
V
Operating Current  
COMP = 0.3 V (no switching)  
SS charging, GATEx switching  
−
27  
9.0  
8.0  
35  
9.5  
8.5  
mA  
V
CC  
UVLO Start Threshold  
UVLO Stop Threshold  
8.5  
7.5  
GATEx not switching, SS and COMP  
discharging  
V
UVLO Hysteresis  
Start − Stop  
0.8  
1.0  
1.2  
V
2. Guaranteed by design, not tested in production.  
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7
NCP5318  
PIN DESCRIPTION  
Pin No.  
Pin Symbol  
−V  
Pin Name  
Description  
1−3,  
30−32  
V
DAC VID Inputs  
VID−compatible logic input used to program the converter output voltage.  
All high on V −V generates fault.  
ID0  
ID5  
ID0  
ID4  
4
5
PWRLS  
Power Good Sense  
Voltage sensing pin for Power Good lower threshold.  
V
Fast Voltage Feedback  
Input of PWM comparator for fast voltage feedback, and also the inputs of  
Power Good sense and overvoltage protection comparators  
FFB  
6
7
8
SS  
Soft−Start  
Power Good Output  
Drive ON  
A capacitor between this pin and ground programs the soft−start time.  
PWRGD  
DRVON  
Open collector output goes high when the converter output is in regulation.  
Logic high enables MOSFET drivers, and logic low turns all MOSFETs off  
through MOSFET drivers. Pulled to ground through internal 70 k resistor.  
9
SGND  
Remote Sense Ground  
Ground connection for DAC and error amplifier. Provides remote sensing of  
load ground.  
10  
V
Output of Current Sense  
Amplifiers for Adaptive  
Voltage Positioning  
The offset above DAC voltage is proportional to the sum of inductor current.  
DRP  
A resistor from this pin to V programs the amount of Adaptive Voltage  
FB  
Positioning. Leave this pin open for no Adaptive Voltage Positioning.  
11  
12  
V
Voltage Feedback  
Error Amp Output  
Error amplifier inverting input.  
FB  
COMP  
Provides loop compensation and is clamped by SS during soft−start and  
fault conditions. It is also the inverting input of PWM comparators.  
13  
14  
CS4N  
CS4P  
Current Sense Reference  
Current Sense Input  
Current Sense Reference  
Current Sense Input  
Ground  
Inverting input to current sense amplifier #4.  
Non−inverting input to current sense amplifier #4.  
Inverting input to current sense amplifier #3, and Phase 3 disable pin.  
Non−inverting input to current sense amplifier #3, and Phase 3 disable pin.  
IC power supply return. Connected to IC substrate.  
PWM outputs to drive MOSFET driver ICs.  
15  
CS3N  
16  
CS3P  
17  
GND  
18−21  
22  
GATE4−GATE1  
Channel Outputs  
V
IC Power Supply  
Power Supply Input for IC.  
CC  
23  
R
I
Oscillator Frequency Adjust Resistor to ground programs the oscillator frequency.  
OSC  
LIM  
24  
Total Current Limit  
Current Sense Input  
Current Sense Reference  
Current Sense Input  
Current Sense Reference  
Enable  
Resistor divider between R  
and ground programs the over current limit.  
OSC  
25  
CS1P  
CS1N  
Non−inverting input to current sense amplifier #1.  
Inverting input to current sense amplifier #1.  
26  
27  
CS2P  
Non−inverting input to current sense amplifier #2.  
Inverting input to current sense amplifier #2.  
28  
CS2N  
29  
ENABLE  
A voltage less than the threshold puts the IC in Fault Mode, discharging SS.  
Connect to system VID  
signal to control powerup sequencing.  
PWRGD  
Hysteresis is provided to prevent chatter.  
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8
NCP5318  
VFB  
SS  
−
+
COMP  
COMP  
+
−
19 mV  
ERROR AMP  
SOFT−START  
SS CLAMP  
FAULT  
6−BIT DAC  
VID4  
VID3  
VID2  
VID1  
VID0  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
VID5  
DAC  
VDRP  
POWER GOOD  
PWRGD  
111111  
DAC  
REF  
SGND  
PGD  
PWRLS  
PWRLS  
RAMP4  
RAMP3  
RAMP2  
RAMP1  
ROSC  
ROSC  
CS4P  
S
R
Q
Q
Q
Q
GATE1  
GATE2  
GATE3  
GATE4  
CLK1  
CLK2  
CLK3  
CLK4  
−
+
CLK1  
CLK2  
CLK3  
CLK4  
CLK1  
CLK2  
CLK3  
CLK4  
S
R
−
+
OSCILLATOR  
− +  
0.62 V  
VFFB  
S
R
−
+
CURRENT SENSE  
CS1P  
CS1N  
CS1P  
CS1N  
S
R
−
+
I_SUM  
CS2P  
CS2N  
CS2P  
CS2N  
I1  
RESET  
DOMINANT  
I2  
I3  
I4  
CS3P  
CS3N  
CS3P  
CS3N  
CS4P  
CS4N  
CS4P  
CS4N  
3.3 V  
GND  
I_SUM  
VCORE  
111111  
0.7 V  
10 K  
FAULT  
OVERVOLTAGE  
0.5 V  
FAULT  
OV  
DRVON  
ENABLE  
ILIM  
DISABLE  
ILIM  
70 K  
VCC  
VCC_UVLO  
PROTECTIONS  
Figure 2. Block Diagram  
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9
NCP5318  
TYPICAL PERFORMANCE CHARACTERISTICS  
0.50  
0.40  
3.00  
2.50  
0.30  
VID = 101101  
0.20  
VID = 111101  
2.00  
1.50  
1.00  
0.50  
0.00  
0.10  
0.00  
−0.10  
−0.20  
−0.30  
−0.40  
−0.50  
VID = 010100  
VID = 010101  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 3. DAC Variation versus Temperature  
Figure 4. Power Good Delay versus  
Temperature  
245  
240  
235  
230  
225  
220  
215  
210  
205  
700  
650  
600  
550  
500  
450  
400  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 5. OVP Threshold above VID versus  
Temperature  
Figure 6. Channel Startup Offset versus  
Temperature  
1000  
3 Phase Mode  
4 Phase Mode  
100  
100  
10  
1000  
R
OSC  
(kW)  
Figure 7. Oscillator Frequency versus Total  
OSC Value  
R
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10  
NCP5318  
249  
248  
247  
246  
245  
244  
243  
242  
241  
319  
318  
317  
316  
315  
314  
313  
312  
311  
3 Phase Mode  
4 Phase Mode  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
Figure 8. Switching Frequency versus  
Temperature (ROSC = 95.3 kW)  
4.75  
4.70  
4.65  
4.60  
4.55  
4.50  
1.019  
1.018  
1.017  
1.016  
1.015  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 9. VROSC versus Temperature  
Figure 10. Current Sense to VDRP Gain versus  
Temperature  
5.50  
5.00  
4.50  
4.00  
3.50  
46  
45  
44  
43  
42  
41  
40  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 11. Soft−start Charge Current versus  
Figure 12. Current Sense Amplifier to PWM  
Gain versus Temperature  
Temperature  
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11  
NCP5318  
TYPICAL PERFORMANCE CHARACTERISTICS  
3.41  
3.40  
3.39  
3.38  
3.37  
3.36  
3.35  
3.34  
3.33  
10  
5
0
−5  
−10  
−15  
−20  
−25  
−30  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 13. CS Amp to ILIM Gain versus  
Temperature  
Figure 14. ILIM Offset versus Temperature  
31.0  
30.5  
30.0  
29.5  
29.0  
28.5  
28.0  
27.5  
27.0  
26.5  
26.0  
25.5  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
Figure 15. VCC Operating Current versus  
Temperature  
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12  
NCP5318  
V
CC  
Enable  
Fault  
V
REF  
UVLO Fault  
Fault Reset  
Fault Latch  
Fault  
DRVON  
SS  
COMP  
V
I
OUT  
OUT  
PWRGD  
Figure 16. Operating Waveforms  
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13  
NCP5318  
APPLICATIONS INFORMATION  
Overview  
decrease in phase ripple current, output di/dt change from  
positive to negative during switching is reduced. This  
reduction of output di/dt change decreases the output  
capacitor ESL component of output ripple voltage − often  
allowing a reduction in the number of ceramic output  
capacitors.  
Because the inductors are always connected between the  
output and some low impedance (either the input supply or  
ground), the effective inductance value seen at the output is  
the value of all inductors connected in parallel (the value of  
a single inductor divided by the number of phases).  
Multiphase output current ramp−up (+di/dt) or ramp−down  
(−di/dt) exhibits finer granularity due to the summation of  
the smaller individual phase di/dt produced by the larger  
individual inductors. Within one switching cycle, however,  
total converter di/dt can sum to the same di/dt as a power  
stage with a single inductor of the same effective value.  
The NCP5318 is a multiphase, synchronous buck  
controller using the Enhanced V topology which combines  
the fast transient response of the original V topology with  
2
2
the load current sharing characteristic of peak current−mode  
control. The NCP5318 can be operated as an interleaved  
two/three/four−phase controller. Differential current  
sensing is incorporated in order to more easily achieve  
effective current sharing. Converter output is regulated to a  
voltage corresponding to the logic states at six digital inputs.  
The NCP5318 incorporates a Power Good (PWRGD)  
function, providing integrated fault monitoring and  
sequencing that simplifies design, minimizes circuit board  
area, and reduces overall system cost.  
Fixed Frequency Multi−Phase Control  
In a multi−phase buck converter, multiple, synchronously  
rectified, buck power stages are connected in parallel and are  
energized at a common frequency but with staggered  
phasing (interleaving). Each stage carries only part of the  
total output current. In four−phase mode, each phase  
oscillator is delayed 360/4 − or 90 − degrees from that of the  
previous phase. Likewise, for other phase counts, each phase  
oscillator is delayed 360/N degrees from that of the previous  
phase, where N is the number of phases.  
Advantages of a multiphase converter over a single−phase  
converter include a better heat distribution and decreased  
input and output ripple currents. Breaking up heat into a  
greater number of smaller amounts, reduces PC Board  
thermal stress. Multiple phases also permits phase  
inductance to be higher than used in a single−phase  
converter capable of equal transient response, with  
Enhanced V2 Control  
2
Enhanced V control measures and adjusts the output  
current in each phase while simultaneously adjusting the  
current of all phases to maintain the correct output voltage.  
2
Enhanced V responds to output voltage disturbances by the  
combined effect of two mechanisms. The first mechanism  
includes the response of the Error Amplifier, and is  
responsible for maintaining the DC accuracy of the output  
voltage setting. Depending on the frequency compensation  
set by the amplifier’s external components, the Error  
Amplifier response begins to change the PWM duty cycle  
within one to two cycles. The second mechanism is the direct  
coupling of converter output voltage to all non−inverting  
PWM comparator inputs, which dominates PWM response  
at frequencies above the unity−gain crossover frequency of  
the compensated Error Amplifier. A rapid increase in load  
current that decreases converter output voltage immediately  
extends the duty cycle of any phase already on, and will  
typically increase the duty cycle of several of the following  
phases for one cycle.  
2
correspondingly lower phase ripple current and I R losses.  
In addition to the higher efficiency, input capacitor current  
appears even lower because of the cancellation achieved by  
the summation of individual, phase shifted, ripple currents.  
This often allows the use of fewer input capacitors without  
exceeding the capacitor RMS current rating. Also due to the  
x = 1, 2, 3 or 4  
Lx  
SWNODE  
CSxP  
RLx  
+
COx  
CSA  
−
RSx  
Internal Ramp  
CSxN  
V
FFB  
V
OUT  
“Fast−Feedback”  
+
To PWM Latch Reset  
Channel  
Startup  
Offset  
(V  
)
CORE  
Connection  
+
−
V
FB  
−
PWM  
COMP  
E.A.  
+
DAC  
Out  
COMP  
+
Figure 17. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp  
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14  
NCP5318  
The NCP5318 provides a differential input (CSxN and  
When the technique known as “lossless inductor current  
CSxP) that accepts inductor current information for each  
phase as shown in Figure 17. The triangular inductor current  
sensing” is used as in Figure 19, the magnitude of Ext_Ramp  
is:  
is measured across R and amplified before being summed  
S
Ext_Ramp + D   (V * V  
IN OUT  
)ń(R  
CSx  
  C )  
@ f  
CSx SW  
with the channel startup offset, the internal ramp and the  
output voltage. The internal ramp provides greater design  
flexibility by allowing smaller external (current) ramps,  
lower minimum pulse widths, higher frequency operation  
and PWM duty cycles above 50% without external slope  
compensation.  
where D is duty cycle expressed as a fraction.  
For example, if V at zero load is set to 1.480 volts and  
OUT  
the input voltage V is 12.0 V, the duty cycle (D) will be  
IN  
1.480/12.0 or 12.3%. Int_Ramp will be 100 mV/50% x  
12.3% = 25 mV. Realistic values for R , C  
and f are  
CSx CSx  
SW  
When the controller is enabled, GATEx output (GATE  
output of any phase) transitions to a high voltage at the start  
of the oscillator cycle for that phase, commanding a power  
stage to switch on. Inductor current in that power stage then  
ramps up until the combination of startup offset voltage, its  
current sense signal, its internal ramp and the output voltage  
ripple exceed the compensated feedback signal at the other  
PWM comparator input. This brings GATEx low, which  
commands that power stage off. While GATEx is high, the  
2.5 kW, 0.1 mF and 350 kHz. Using these and the previously  
mentioned formula, Ext_Ramp will be 14.8 mV.  
1.480 V ) 0.60 V ) 25 mV  
V
+
COMP  
3.0 V 14.8 mV  
)
 
2
V
+ 2.127 Vdc.  
Error Amplifier Output (COMP) Voltage Bias Point  
Change with Load  
2
Enhanced V control circuit will respond to line and load  
In a closed loop configuration, the COMP pin may move  
in order to maintain the output voltage constant when load  
current changes. The required change at the COMP pin  
depends partially on the scaling of the current feedback  
signal as follows:  
variations, but once GATEx is low, that phase cannot  
respond until the next start of its oscillator cycle. Therefore,  
the NCP5318 will take, at most, the off−time of the oscillator  
to respond to disturbances. With multiple phases, the time to  
respond to disturbances is significantly reduced due to the  
increased likelihood of a GATEx being high, and closer  
average proximity of oscillator starts, however the  
magnitude of that response (for equivalent total inductance)  
is equivalently reduced.  
Turn on of a phase with higher inductor current will  
terminate the PWM cycle earlier, providing negative  
feedback. Current sharing is accomplished by referencing  
the PWM comparators of all phases to the same Error  
Amplifier signal (COMP pin).  
DI  
OUT  
N
DV + R   G  
CSA  
 
S
where R is the current sense resistance in each phase and  
S
N is the number of phases.  
Also, when load current changes, nonideal conversion  
efficiency causes the change in input power to exceed the  
change in output power, and the duty cycle becomes:  
D
DȀ +  
Efficiency  
Error Amplifier Output (COMP) Voltage No Load Bias  
Point  
and  
As shown in Figure 17, the voltage present at each PWM  
comparator’s non−inverting input is the sum of the channel  
startup offset, output voltage, and the inductor current and  
internal ramps corresponding to that phase. When the  
average output current is zero, the Error Amplifier output at  
the COMP pin will be:  
(D   Efficiency)  
D
DD + DȀ * D +  
*
Efficiency  
Efficiency  
D   (1 * Efficiency)  
+
Efficiency  
Peak to peak ripple current therefore also changes by  
nearly (1− Efficiency) / Efficiency, thereby changing the  
amplitude of the external ramp by this amount. The  
complete change required at the COMP pin will therefore  
be:  
V
) Channel_Startup_Offset  
OUT  
+
V
COMP  
Ext_Ramp  
) Int_Ramp ) G  
CSA  
 
2
Int_Ramp is the fraction of the internal ramp (“Artificial  
Ramp Amplitude” = 100 mV at a 50% duty cycle)  
corresponding to the steady state duty cycle, Ext_Ramp is the  
peak−to−peak external steady−state current ramp appearing  
DI  
OUT  
N
DV + R   G  
CSA  
 
)
S
(Int_Ramp ) G  
  Ext_Ramp) (1 * Efficiency)  
CSA  
2
 
Efficiency  
across CSxP to CSxN, G  
is the current sense amplifier  
CSA  
gain (“Current Sense Amp to PWM Gain” = 3.0 V/V).  
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15  
NCP5318  
For the converter described above with 4 phases and 85%  
efficiency at 100 A full load, the Error Amplifier output  
changes by:  
sensed current previously described, which reduces the  
amount of Error Amplifier output movement required.  
Figure 18 shows the open loop response of the PWM  
comparator and resulting phase current upon an output  
voltage dip. Before T1, the converter is in steady−state  
operation. The inductor current provides a portion of the  
PWM ramp through the current sense amplifier. The PWM  
cycle ends when the sum of the current ramp, the “partial”  
internal ramp, the offset and the output voltage exceeds the  
level of the COMP pin. At T1, the load current increases and  
the output voltage sags. The next PWM cycle begins and the  
cycle continues longer than before until T2, when the current  
signal has increased enough to make up for the lower voltage  
at the VFB pin. After T2, the output voltage remains lower,  
and the average current signal level (CSA output) is raised  
so that the sum of the current and voltage signal is the same  
as with the original load. In a closed loop system, the COMP  
pin would move higher to restore the output voltage to the  
original level.  
3.0 V 100 A  
DV  
+ 1.0 mW   
 
)
COMP  
4
V
(25 mV ) 3.0 VńV   14.8 mV)  
(1 * 0.85)  
 
2
0.85  
+ 83 mV  
Additionally, if the “Droop” feature is used, the output  
voltage change resulting from the synthesized, closed loop  
output impedance (referred to as the output loadline) is as  
follows:  
DV + * R   DI  
LL  
OUT  
where R is the value, in ohms, of the output loadline.  
LL  
Summation of this change at the PWM comparator input  
forces the Error Amplifier output voltage to respond with an  
identical change which always opposes that forced by the  
SWNODE  
V
(V  
OUT  
)
FFB  
Internal Ramp  
CSA Out  
COMP  
CSA Output +  
Internal Ramp +  
Offset + CSxN  
T1  
T2  
Figure 18. Open Loop Operation  
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16  
NCP5318  
Inductive Current Sensing  
Current Sharing Accuracy  
For lossless sensing, current can be measured across the  
inductor as shown in Figure 19. In the diagram, L is the  
For accurate current sharing, the current sense inputs  
should sense the current at identical points at each phase  
sense resistance. Printed Circuit Board (PCB) traces that  
carry inductor current can be used as part of the current sense  
resistance by selecting where the current sense signal is  
picked up along a current carrying trace, but variations of  
PCB copper base thickness, plating, and etching can degrade  
current sharing and must be well controlled. The total  
current sense resistance used for calculations must include  
any PCB trace resistance that carries inductor current  
between the CSxP input and the CSxN input. Current Sense  
Amplifier (CSA) input mismatch and the value of the  
current sense component will determine the accuracy of the  
current sharing between phases. The worst case CSA input  
mismatch is 4 mV and will typically be within 1.5 mV. The  
difference in peak currents between phases will be the CSA  
input mismatch divided by the current sense resistance. If all  
current sense components are of equal resistance, a  
1.5 mV mismatch with a 1.0 mW sense resistance will  
contribute 1.5 A of current difference between phases.  
output inductance and R is the inherent inductor resistance.  
L
To compensate the current sense signal, the values of R  
CSx  
and C  
are chosen so that L/R = R  
x C . If this  
CSx CSx  
CSx  
L
criteria is met, the current sense signal should be the same  
shape as the inductor current and the voltage signal between  
CSxP and CSxN will represent the instantaneous value of  
inductor current. Also, the circuit can be analyzed as if a  
sense resistor of value R was used. When choosing or  
L
designing inductors for use with inductive sensing,  
tolerances and temperature effects should be considered.  
Cores with a low permeability material or a large gap will  
usually have minimal inductance change with temperature  
and load. Copper magnet wire has a temperature coefficient  
of 0.39% per degree C. The increase in winding resistance  
at higher temperatures should be considered when setting  
the phase peak current limit threshold. If current sensing  
more accurate than provided by inductive sensing is  
required, current can be sensed through a resistor as shown  
in Figure 17.  
x = 1, 2, 3 or 4  
R
CSx  
SWNODE  
CSxP  
+
CSA  
−
COx  
Lx  
C
CSx  
CSxN  
Internal Ramp  
RLx  
V
FFB  
To PWM  
Latch Reset  
V
“Fast−Feedback”  
OUT  
+
Channel  
Startup  
Offset  
(V  
)
Connection  
CORE  
+
−
V
FB  
PWM  
COMP  
−
E.A.  
+
DAC  
Out  
COMP  
+
Figure 19. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp  
External Ramp Size and Current Sensing  
The internal ramp allows flexibility in setting the current  
sense time constant. Typically, the current sense R  
the time constant of R  
x C . Excessive error can  
CSx  
CSx  
degrade transient response, adaptive positioning (droop)  
and current limit. During a positive current transient, the  
COMP pin will be required to overshoot in response to the  
current signal in order to maintain the output voltage. Phase  
pulse−by−pulseovercurrent protection will trip earlier than  
x
CSx  
C
CSx  
time constant should be equal to or slightly slower than  
the inductor’s time constant. If RC is chosen to be smaller  
(faster) than L/R , the AC or transient portion of the current  
L
sensing signal will be scaled larger than the DC portion. This  
will provide a larger steady−state ramp, but transient circuit  
response will be affected and must be evaluated carefully.  
The current signal will overshoot during transients and settle  
it would if compensated correctly. Similarly, the V  
DRP  
signal will overshoot which will produce too much transient  
droop in the output voltage, and also result in hiccup−mode  
current limit having a lower threshold for fast rising step  
loads than for slowly rising output currents.  
at the rate determined by R  
x C . It will eventually  
CSx  
CSx  
settle to the correct DC level, but the error will decay with  
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NCP5318  
Transient Response and Adaptive Voltage Positioning  
the output filter. The transition between fast and slow  
positioning is controlled by the total ramp size and the error  
amp compensation. If the ramp size is too large or the error  
amp too slow, there will be a long transition to the final  
voltage after a transient. This will be most apparent with low  
capacitance output filters.  
For applications with fast transient currents, the output  
filter is frequently sized larger than ripple currents require in  
order to reduce voltage excursions during load transients. In  
addition, adaptive voltage positioning can reduce  
peak−peak output voltage deviations due to load transients  
and allow use of a smaller output filter. Adaptive voltage  
positioning sets output voltage higher than nominal at light  
loads, and output voltage is allowed limited sag when the  
load current is applied. Upon removal of the load, output  
voltage returns no higher than the original level, allowing  
one output transient peak to be canceled over a load  
application and release cycle.  
For low current applications, a simple dropping resistor in  
series with the output can provide fast, accurate adaptive  
positioning. However, at high currents, the loss in a dropping  
resistor becomes excessive. For example, a 50 A converter  
with a 1.0 mW resistor would provide a 50 mV change in  
output voltage between no load and full load and would  
dissipate 2.5 W. Lossless Adaptive Voltage Positioning  
(AVP) is an alternative to using a droop resistor. Figure 20  
shows how AVP works. The waveform labeled “normal”  
shows a converter without AVP.  
Overvoltage Protection  
Overvoltage Protection (OVP) in the Enhanced V  
2
control topology is provided by operation of the  
synchronous rectifiers. The control loop responds to an  
overvoltage condition within 40 ns, causing the GATEx  
output to shut off. The (external) MOSFET driver should  
react normally to turn off the top MOSFET and turn on the  
bottom MOSFET. This acts quickly to discharge the output  
voltage and prevent damage to the load. The regulator will  
remain in this state until the fault latch is reset by cycling  
power at the V pin. If the voltage at the V  
pin exceeds  
CC  
FFB  
200 mV above the VID voltage, the converter will latch off.  
The OVP circuit begins monitoring the output voltage as  
soon as the V voltage exceeds the UVLO threshold of the  
CC  
part. The OVP circuit is then always active, regardless of  
operating status.  
Power Good  
According to the latest specifications, the Power Good  
(PWRGD) signal must be asserted when the output voltage  
is within a window defined by the VID code, as shown in  
Figure 21. The PWRLS pin is provided to allow the  
PWRGD comparators to accurately sense the output  
voltage. The effect of the PWRGD lower threshold can be  
modified using a resistor divider from the output to PWRLS  
to ground, as shown in Figure 22.  
Normal  
FastAdaptive Positioning  
SlowAdaptive Positioning  
Limits  
PWRGD  
Figure 20. Adaptive Voltage Positioning  
PWRGD  
low  
PWRGD  
high  
PWRGD  
low  
HIGH  
LOW  
On the left, the output voltage sags when the output current  
is stepped up and later overshoots when current is stepped  
back down. With fast (ideal) AVP, the peak−to−peak  
excursions are cut in half. In the slow AVP waveform, the  
output voltage is not repositioned quickly enough after  
current is stepped up and the upper limit is exceeded. The  
controller can be configured to adjust the output voltage  
based on the output current of the converter as shown in the  
application diagram in Figure 1. The no−load positioning is  
set internally to VID − 19 mV, reducing the potential error  
due to resistor and bias current mismatches. In order to  
realize the AVP function, a resistor divider network is  
V
OUT  
−2.6 +2.6%  
%
−5.0 +5.0%  
%
VID + 80 mV  
V
LOWER  
Figure 21. PWRGD Assertion Window  
V
OUT  
R1  
connected between V , V  
and V . During no−load  
OUT  
FB  
DRP  
conditions, the V  
pin. As the output current increases, the V  
pin is at the same voltage as the V  
DRP  
FB  
PWRLS  
pin voltage  
DRP  
increases proportionally. This drives the V voltage higher,  
R2  
FB  
causing V  
to “droop” according to a loadline set by the  
OUT  
resistor divider network. The response during the first few  
microseconds of a load transient is controlled primarily by  
power stage output impedance, and by the ESR and ESL of  
Figure 22. Adjusting the PWRGD Threshold  
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18  
NCP5318  
Fault Protection Logic  
Since the internally−set thresholds for PWRLS are  
/2 for the lower threshold and V  
100 mV for the upper threshold, a simple equation can be  
provided to assist the designer in selecting a resistor divider  
to provide the desired PWRGD performance.  
The NCP5318 includes fault protection circuitry to  
prevent harmful modes of operation from occurring. The  
fault logic is described in Table 1.  
V
+
OUT No Load  
OUTNo Load  
Gate Outputs  
V
R ) R  
The NCP5318 is designed to operate with external gate  
drivers. Accordingly, the gate outputs are capable of driving  
a 100 pF load with typical rise and fall times of 5.0 ns.  
An additional signal, DRVON, works in conjunction with  
the Gate Outputs. The DRVON signal is intended to be used  
as an enable signal for external gate drivers, such as the  
NCP3418B. If the DRVON signal is low, the gate driver will  
be disabled and both MOSFETs in the synchronous rectified  
phase channel will be held in the off position. If the DRVON  
signal is high, the gate driver will be enabled. The high side  
MOSFET will be enabled if the Gate Output is high and  
DRVON is high. The low side MOSFET will be enabled if  
the Gate Output is low and DRVON is high. The DRVON  
OUTNoLoad  
2
1
2
V
V
+
 
LOWER  
R
2
+ V  
) 100 mV  
UPPER  
OUTNoLoad  
The logic circuitry inside the chip sets PWRGD low only  
after a delay period has been passed. A “power bad” event  
does not cause PWRGD to go low unless it is sustained  
through the delay time of 1 ms. If the anomaly disappears  
before the end of the delay, the PWRGD output will never  
be set low. In order to use the PWRGD pin as specified, the  
user is advised to connect external resistors as necessary to  
limit the current into this pin to 4.0 mA or less.  
Undervoltage Lockout  
The NCP5318 includes an undervoltage lockout circuit.  
This circuit keeps the IC’s output drivers low until V  
applied to the IC reaches 9.0 V. The GATE outputs are  
signal at power up will initially go high as V rises above  
CC  
CC  
the power on reset (POR) of the IC, roughly 5 V. It will stay  
high until the V voltage exceeds the UVLO threshold of  
CC  
disabled when V drops below 8.0 V.  
CC  
the part. DRVON will then go to a low state and stay low  
until the part is enabled or an OVP is detected.  
Soft−Start  
At initial power−up, both SS and COMP voltages are zero.  
The total SS capacitance will begin to charge with a current  
of 70 mA. The error amplifier directly charges the COMP  
capacitance. An internal clamp ensures that the COMP pin  
voltage will always be less than the voltage at the SS pin,  
ensuring proper startup behavior. All GATE outputs are held  
low until the COMP voltage reaches 0.6 V. Once this  
threshold is reached, the GATE outputs are released to  
operate normally.  
Digital to Analog Converter (DAC)  
The output voltage of the NCP5318 is set by means of a  
6−bit, 0.5% DAC. The VID pins must be pulled high  
externally. A 1.0 kW pullup to a maximum of 3.3 V is  
recommended to meet Intel specifications. To ensure valid  
logic signals, the designer should ensure at least 800 mV will  
be present at the IC for a logic high. The output of the DAC  
is described in the Electrical Characteristics section of the  
data sheet. These outputs are consistent with VR 10.x and  
processor specifications. The DAC output is equal to the  
VID code specification minus 19 mV. The latest VR and  
processor specifications require a power supply to turn its  
output off in the event of a 11111X VID code. When the  
DAC sees such a code, the GATE pins stop switching and go  
low. This condition is described in Table 1.  
Current Limit  
The individual phase currents are summed to compare a  
total current signal to a user adjustable voltage on the I  
LIM  
pin. If the I  
voltage is exceeded, the fault latch trips and  
LIM  
the converter is latched off. V must be recycled to reset the  
CC  
latch.  
Table 1. Description of Fault Logic  
Results  
Driver  
Enable  
SS Character-  
istics  
Stop Switching  
PWRGD Level  
Reset Method  
Power On  
Faults  
Overvoltage Lockout  
Enable Low  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
High  
Low  
Low  
Low  
Low  
High  
−0.3 mA  
−0.3 mA  
Depends on output voltage level  
Depends on output voltage level  
Depends on output voltage level  
Depends on output voltage level  
Low  
Not Affected  
Power On  
Module Overcurrent Limit  
DAC Code = 11111x  
−0.3 mA  
−0.3 mA  
Change VID Code  
Power On  
V
Undervoltage Lockout  
−0.3 mA  
REF  
PWRLS Out of Range  
Not Affected  
Not Affected  
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19  
NCP5318  
Adjusting the Number of Phases  
The designer must determine the number of bulk  
capacitors so as to meet the peak transient requirements. The  
formula below can be used to provide a starting point for the  
The NCP5318 is designed with a selectable−phase  
architecture. Designers may choose any number of phases  
up to four. The phase delay is automatically adjusted to  
match the number of phases that will be used. This feature  
allows the designer to select the number of phases required  
for a particular application.  
minimum number of bulk capacitors (NB  
):  
OUT,MIN  
(eq. 1)  
DI  
DV  
O,MAX  
NB  
OUT,MIN  
+ ESR per capacitor   
O,MAX  
Four−phase operation is standard. All phases switch with  
a 90 degree delay between pulses. No special connections  
are required. Three−phase operation is achieved by  
disabling phase 4. Tie together CS4N and CS4P, and then  
The ESL of the bulk plus ceramic capacitors also affects  
the voltage change during a load transient according to:  
DI  
O,MAX  
Dt  
DV  
+ (  
)   ESL  
O,MAX  
(eq. 2)  
pull both pins to V . The remaining phases will continue  
CC  
ESR  
) DI  
 
O,MAX  
to switch, but now there will be a 120 degree delay between  
phases. The phase firing order will become 1−2−3.  
Two− and single−phase operation may be realized as well.  
First, the designer must choose the proper phases. Two phase  
operation must use phases 2 and 4 by tying CS1N, CS1P,  
CS3N and CS3P to ground. This will then use phases 2 and  
4 to control gate drivers. The other gate control outputs may  
switch, so leave them unconnected.  
Single phase is best accomplished by using only Phase 2  
as the switch controller. Connect CS2P and CS2N pins to the  
current sense circuit, and gate control output 2 to the gate  
driver IC input. Tie all other CSxx pins together and connect  
them to ground.  
NB  
OUT,MIN  
where ESL is the equivalent ESL of all bulk and ceramic  
output capacitors in parallel. Capacitor manufacturers do  
not always specify the ESL of their components and it is  
affected by the inductance added by the PCB layout.  
Therefore, it is necessary to start a design with slightly more  
than the minimum number of bulk and ceramic capacitors  
and perform transient testing to determine the final number  
of bulk capacitors.  
Intel processor specifications discuss “DynamicVID”  
(DVID), by which the VID codes are stepped up or down to  
a new desired output voltage. Timing requirements for when  
the output must be in regulation further complicates output  
capacitor selection. The ideal output capacitor selection has  
low ESR and low capacitance. Too much output capacitance  
will make it difficult to meet DVID timing specifications;  
too much ESR will complicate the transient solution. The  
Sanyo 4SEPC560 and Panasonic EEU−FL provide a good  
balance of capacitance vs. ESR.  
Design Procedure  
1. Setting the Switching Frequency  
The total resistance from R  
to ground sets the  
OSC  
operating frequency for all phases of the converter. The  
frequency can be set for either the three phase or four phase  
mode by using Figure 7, “Oscillator Frequency versus Total  
Microprocessor manufacturers often specify a minimum  
number of ceramic capacitors, which may need adjustment  
to meet ripple voltage requirements. The output voltage  
ripple can be calculated using the output inductor value  
R
OSC  
Value”. After choosing the desired operating  
frequency and the number of phases, use the figure to  
determine the necessary resistance. If two phase operation  
is desired, use the value given for four phase operation.  
derived in the following section (L ) and the number of  
O,MIN  
The voltage from R  
is closely regulated at 1.0 V. This  
OSC  
bulk output capacitors (NB ) determined above:  
OUT,MIN  
voltage can be used as the reference for the overcurrent limit  
set point on the I pin. Design a voltage divider with the  
V
+ (ESRperbulkcap.ńNB )   
OUT,MIN  
OUT,P * P  
LIM  
appropriate division ratio to give the desired I  
voltage  
(
)
(
) (eq. 3)  
]
SW  
Ǔ
ńL  
[ V * #Phase   V  
IN OUT  
  Dń L  
  f  
LIM  
O,MIN  
and total resistance to set the operating frequency. Since  
loading by the I pin is very small, the frequency selection  
ǒ
) V   ESLperceramiccap.ńNC  
IN OUT,MIN O,MIN  
LIM  
will not be affected.  
This formula assumes steady−state conditions with no  
more than one phase on at any time. The second term in  
Equation 3 is the total ripple current seen by the output  
capacitors. The total output ripple current is the “time  
summation” of the four individual phase currents that are 90  
degrees out−of−phase. As the inductor current in one phase  
ramps upward, current in the other phases ramp downward  
and provides a canceling of currents during part of the  
switching cycle. Therefore, the total output ripple current  
and voltage are reduced in a multi−phase converter.  
2. Output Capacitor Selection  
The output capacitors filter the current from the output  
inductors and provide a low impedance for transient load  
current changes. Typically, microprocessor applications  
require both bulk (polymer, aluminum, or tantalum  
electrolytic) and low impedance, high frequency (ceramic)  
types of capacitors. The bulk capacitors provide “hold up”  
during transient loading until phase currents ramp up or  
down. The low impedance capacitors reduce steady−state  
ripple voltage and bypass the bulk capacitance for fast  
output current changes.  
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20  
NCP5318  
3. Output Inductor Selection  
For increasing current:  
The output inductor is a very critical component in the  
converter because it directly affects the choice of other  
components and affects both the steady−state and transient  
performance of the converter. When selecting an inductor,  
the designer must consider factors such as DC current, peak  
current, core loss, magnetic saturation, output voltage  
ripple, load step and release, temperature, physical size and  
cost.  
In general, the output inductance value should be  
electrically and physically as small as possible in order to  
provide the best transient response at minimum cost. If a  
large inductance value is used, the converter will not  
respond quickly to rapid changes in the load current. On the  
other hand, lower inductance requires more parallel ceramic  
output capacitors to make the output filter ESL low enough  
to avoid excessive output voltage ripple. And the higher  
ripple current in the MOSFETs and input capacitors  
increases dissipation and lowers converter efficiency  
(especially at light loads) − possibly requiring the use of  
higher rated MOSFETs, an oversized thermal solution, and  
the use of more or higher current rated input capacitors,  
which increases converter cost. Too high a ripple current  
may saturate the inductor, further increasing ripple current  
and all losses including core loss.  
One method of calculating an output inductor value is to  
size the inductor to produce a specified maximum ripple  
current in the inductor. Lower ripple currents will result in  
less core and MOSFET losses and higher converter  
efficiency. Equation 4 may be used to calculate the inductor  
value to produce a given maximum ripple current (a) per  
phase. The inductor value calculated by this equation is a  
minimum because values less than this will produce more  
ripple current than desired. Conversely, higher inductor  
values will result in less than the selected maximum ripple  
current.  
DI  
O
(eq. 5)  
(eq. 6)  
Dt  
+ Lo   
INC  
(V * V  
)
IN OUT  
For decreasing current:  
DI  
OUT  
O
Dt  
+ Lo   
DEC  
(V  
)
For typical processor applications with output voltages  
less than one quarter of the input voltage, the current can be  
increased more quickly than it can be decreased. Thus, it  
may be more difficult for the converter to avoid  
overshooting the regulation limits when the load is removed  
than when it is applied.  
4. Input Capacitor Selection  
Input capacitors must be both bulk electrolytic and  
ceramic types. Bulk capacitors are needed to ensure  
converter stability, and can provide some buffering of the  
ATX power supply from the effects of load step and release.  
The ceramic capacitors are needed to provide the input  
ripple current. The choice and number of ceramic input  
capacitors is primarily determined by their voltage and  
ripple current ratings. The designer must choose capacitors  
that will support the worst case input voltage with adequate  
margin. To calculate the number of input capacitors, the  
converter RMS input ripple current must be calculated by  
the following procedure:  
D
(eq. 7)  
I
+ I  
 
O,MAX  
IN,AVG  
h
where:  
D is the duty cycle of the converter, D = V  
h is the specified minimum efficiency;  
/V ;  
OUT IN  
I
is the maximum converter output current.  
O,MAX  
The input capacitors will discharge when the control FET  
is ON and charge when the control FET is OFF as shown in  
Figure 23.  
(eq. 4)  
(V * V  
IN OUT  
)   V  
OUT  
Lo  
MIN  
+
(a   I   V   f  
O,MAX IN  
)
DI  
= I  
− I  
SW  
C,IN  
C,MAX C,MIN  
I
C,MAX  
a is the ripple current as a percentage of the maximum  
output current per phase (a = 0.15 for 15%, a = 0.25 for  
25%, etc.). If the minimum inductor value is used, the  
inductor current will swing (a/2)% about its value at the  
center. Therefore, for a four−phase converter, the inductor  
must be designed or selected such that it will not saturate  
I
C,MIN  
t
ON  
0 A  
Control FET Off,  
Input Caps  
Charging  
−I  
IN,AVG  
with a peak current of (1 + a/2) ⋅ I /4.  
O,MAX  
T/4  
The maximum inductor value is limited by the transient  
response required of the converter. If the converter is to have  
a fast transient response, the inductor should be made as  
small as will be allowed by other constraints. If the inductor  
is too large, its current will change too slowly, the output  
voltage will droop excessively, more bulk capacitors will be  
required and the converter cost will be increased. For a given  
Control FET On,  
Input Caps Discharging  
Figure 23. Input Capacitor Current for a  
Four−Phase Converter  
inductor value (L ), it is useful to determine the time  
O
required to increase or decrease the current.  
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21  
NCP5318  
The following equations will determine the maximum and  
minimum currents delivered by the input capacitors:  
In general, capacitor manufacturers require derating to the  
specified ripple−current based on the ambient temperature.  
More capacitors will be required because of the current  
derating.  
I
Lo,MAX  
(eq. 8)  
(eq. 9)  
I
+
* I  
C,MAX  
IN,AVG  
h
5. Input Inductor Selection  
I
Lo,MIN  
I
+
* I  
C,MIN  
IN,AVG  
h
The use of an inductor between the input capacitors and  
the power source isolates the voltage source and the system  
from noise generated by the switching converter, while also  
reducing the input current slew rate during load transients.  
The worst case input current slew rate will occur during the  
first few PWM cycles immediately after a step−load change  
is applied as shown in Figure 24. When the load is applied,  
the output voltage is pulled down very quickly. Current  
through the output inductors will not change  
instantaneously, so the initial transient load current is  
conducted by the output capacitors. The output voltage will  
step downward depending on the magnitude of the output  
I
is the maximum output inductor current:  
Lo,MAX  
I
DI  
O,MAX  
Lo  
(eq. 10)  
I
+
)
Lo,MAX  
f
2
where f is the number of phases in operation.  
is the minimum output inductor current:  
I
Lo,MIN  
I
DI  
O,MAX  
Lo  
(eq. 11)  
I
+
*
Lo,MIN  
f
2
DI is the peak−to−peak ripple current in the output  
Lo  
inductor of value Lo:  
current (I  
capacitors (ESR  
output capacitors (NB  
output voltage at full transient load will be:  
), the per capacitor ESR of the output  
O,MAX  
D
(eq. 12)  
DI + (V * V  
)   
Lo IN OUT  
) and the number of bulk electrolytic  
OUT  
(Lo @ f  
)
SW  
) as shown in Figure 24. The  
OUT  
For the four−phase converter, the input capacitor(s) RMS  
current is then:  
(eq. 15)  
V
+
OUT,FULL−LOAD  
2
(eq. 13)  
I
+ [4D   (I  
) I  
  DI  
C,MIN C,IN  
CIN,RMS  
C,MIN  
2
ESR  
OUT  
V
* (I  
)   
O,MAX  
OUT,NO−LOAD  
NB  
OUT  
DI  
C,IN  
3
2 1ń2  
  (1 * 4D)]  
IN,AVG  
)
) ) I  
When the control MOSFET (Q1 in Figure 24) turns ON,  
the input voltage will be applied to the input terminal of the  
output inductor (the SWNODE). At that instant, the voltage  
across the output inductor can be calculated as:  
Select the number of input capacitors (NC ) to provide  
IN  
the RMS input current (I ) based on the RMS ripple  
CIN,RMS  
current rating per capacitor (I  
):  
RMS,RATED  
I
CIN,RMS  
(eq. 14)  
NC  
+
IN  
(eq. 16)  
DV + V * V  
OUT,FULL−LOAD  
I
Lo  
IN  
RMS,RATED  
V
* V  
OUT,NO−LOAD  
IN  
For a four−phase converter with perfect efficiency (h = 1),  
the worst case input ripple−current will occur when the  
converter is operating at a 12.5% duty cycle. At this  
operating point, the parallel combination of input capacitors  
must support an RMS ripple current equal to 12.5% of the  
converter’s DC output current. At other duty cycles, the  
ripple−current will be less. For example, at a duty cycle of  
either 6% or 19%, the four−phase input ripple−current will  
be approximately 10% of the converter’s DC output current.  
+
ESR  
OUT  
OUT  
) (I  
)   
O,MAX  
NB  
The differential voltage across the output inductor will  
cause its current to increase linearly with time. The slew rate  
of this current can be calculated from:  
dI  
Lo  
DV  
Lo  
(eq. 17)  
+
dt  
Lo  
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22  
NCP5318  
SWNODE  
Q2  
V
OUT  
MAX dI/dt occurs in  
first few PWM cycles.  
I
I
Lo  
Li  
Vi(t = 0) = 12 V  
Q1  
Vo(t = 0) = 1.480 V  
Li  
Lo  
470 nH  
V
+
+
Ci  
NB × CB  
NB  
× CB  
OUT  
IN  
IN  
OUT  
+
−
Vi  
12 V  
60 u(t)  
ESR /NB  
ESR  
/NB  
OUT OUT  
IN  
IN  
Figure 24. Calculating the Input Inductance  
6. MOSFET and Heatsink Selection  
Current changes slowly in the input inductor so the input  
capacitors must initially deliver most of the input current.  
The amount of voltage drop across the input capacitors  
Power dissipation, package size and thermal requirements  
drive MOSFET selection. To adequately size the heat sink,  
the design must first predict the MOSFET power  
dissipation. Once the dissipation is known, the heat sink  
thermal impedance can be calculated to prevent the  
specified maximum case or junction temperatures from  
being exceeded at the highest ambient temperature. Power  
dissipation has two primary contributors: conduction losses  
and switching losses. The control or upper MOSFET will  
display both switching and conduction losses. The  
synchronous or lower MOSFET will exhibit only  
conduction losses because it switches with nearly zero  
voltage. However, the body diode in the synchronous  
MOSFET will incur diode losses during the non−overlap  
time of the gate drivers.  
(DV ) is determined by the number of bulk input  
CIN  
capacitors (NB ), their per capacitor ESR (ESR ) and the  
IN  
IN  
current in the output inductor according to:  
ESR  
IN  
dl  
D
SW  
Lo  
 
(eq. 18)  
DV  
+
 
CIN  
NB  
IN  
dt  
f
Before the load is applied, the voltage across the input  
inductor (V ) is very small and the input capacitors charge  
LIN  
to the input voltage V . After the load is applied, the voltage  
IN  
drop across the input capacitors, DV , appears across the  
CIN  
input inductor as well. From this, the minimum value of the  
input inductor can be calculated from:  
V
LIN  
+
+
dI  
For the upper or control MOSFET, the power dissipation  
can be approximated from:  
IN  
(eq. 19)  
(
)
Li  
MIN  
dt  
MAX  
DV  
CIN  
dI  
IN  
2
P
+ (I  
  R  
RMS,CNTL DS(on)  
)
(
)
(eq. 20)  
D,CONTROL  
dt  
MAX  
Q
switch  
) (I  
) (  
 
  V   f  
IN  
)
SW  
Lo,MAX  
dI /dt  
slew rate.  
is the maximum allowable input current  
IN MAX  
I
g
Q
oss  
2
  V   f  
IN  
) ) (V @ Q  
IN  
@ f  
)
The input inductance value calculated from Equation 19  
is relatively conservative. It assumes the supply voltage is  
very “stiff” and does not account for any parasitic elements  
that will limit dI/dt such as stray inductance. Also, the ESR  
values of the capacitors specified by the manufacturer’s data  
sheets are worst case high limits. In reality, input voltage  
“sag,” lower capacitor ESRs and stray inductance will  
further reduce the slew rate of the input current.  
As with the output inductor, the input inductor must  
support the maximum current without saturating. Also, for  
an inexpensive iron powder core, such as the −26 or −52  
from Micrometals, the inductance “swing” with DC bias  
must be taken into account since inductance will decrease as  
the DC input current increases. At the maximum input  
current, the inductance must not decrease below the  
minimum value or the dI/dt will be higher than expected.  
SW  
RR SW  
2
The first term represents the conduction or I R losses  
when the MOSFET is ON while the second term represents  
switching OFF losses. The third term is the loss associated  
with charging the control and synchronous MOSFET output  
capacitances when the control MOSFET turns ON. The  
output losses are caused by the output capacitances of both  
the control and synchronous MOSFET but are dissipated  
only in the control FET. The fourth term is the loss due to the  
reverse recovered charge of the body diode in the  
synchronous MOSFET. The first two terms are usually  
adequate to predict the majority of the losses.  
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23  
NCP5318  
2
I
is the RMS value of the current in the control  
The first term represents the conduction or I R losses  
when the MOSFET is ON and the second term represents the  
diode losses that occur during the gate non−overlap time.  
All terms were defined in the previous discussion for the  
control MOSFET with the exception of:  
RMS,CNTL  
MOSFET:  
(eq. 21)  
I
+ (D   
RMS,CNTL  
2
I
Lo,MIN  
3
2
1ń2  
))  
(I  
* I  
  I )  
Lo,MIN  
Lo,MAX  
Lo,MAX  
I
is the maximum output inductor current:  
(eq. 28)  
Lo,MAX  
Lo,MIN  
O,MAX  
I
+ ((1 * D)   
RMS,SYNCH  
2
I
I
DI  
Lo,MIN  
3
O,MAX  
Lo  
2
(I  
1ń2  
))  
(eq. 22)  
) I  
  I  
)
I
+
)
Lo,MAX  
Lo,MAX  
Lo,MIN  
Lo,MAX  
f
2
I
is the minimum output inductor current:  
I
DI  
O,MAX  
Lo  
(eq. 23)  
I
+
*
I
Lo,MIN  
D
f
2
I
is the maximum converter output current.  
D is the duty cycle of the converter:  
V
GATE  
V
OUT  
(eq. 24)  
D +  
V
IN  
DI is the peak−to−peak ripple current in the output  
Lo  
V
GS_TH  
inductor of value L :  
o
D
(eq. 25)  
DI + (V * V  
Lo IN OUT  
)   
(Lo   f  
)
SW  
Q
Q
Q
V
DRAIN  
GS1  
GS2  
GD  
R
DS(on)  
is the ON resistance of the high side MOSFET at  
the applied gate drive voltage. Q  
is the post gate  
switch  
Figure 25. MOSFET Switching Characteristics  
threshold portion of the gate−to−source charge plus the  
gate−to−draincharge. This may be specified in the data sheet  
or approximated from the gate−charge curve as shown in the  
Figure 25.  
When the MOSFET power dissipations are known, the  
designer can calculate the required thermal impedance to  
maintain a specified junction temperature at the worst case  
ambient operating temperature.  
(eq. 26)  
Q
+ Q  
) Q  
gs2 gd  
switch  
(eq. 29)  
q
T
t (T * T )ńP  
J A D  
I is the output current from the gate driver IC.  
g
V
is the input voltage to the converter.  
is the switching frequency of the converter.  
IN  
where:  
f
sw  
q is the total thermal impedance (q + q );  
T
JC  
SA  
Q
is the reverse recovery charge of the lower  
RR  
q
is the junction−to−case thermal impedance of the  
JC  
MOSFET.  
is the sum of the high and low side MOSFET  
MOSFET;  
is the sink−to−ambient thermal impedance of  
Q
oss  
q
SA  
output charges specified in the data sheets, or  
estimated from integrating C from zero volts to  
the heatsink assuming direct mounting of the  
MOSFET if no thermal “pad” is used;  
OSS  
V .  
IN  
T
is the specified maximum allowed junction  
J
For the lower or synchronous MOSFET, the power  
dissipation can be approximated from:  
temperature;  
T is the worst case ambient operating temperature.  
A
(eq. 27)  
2
P
+ (I  
  R  
)
For TO−220 and TO−263 packages, standard FR−4  
copper clad circuit boards will have approximate thermal  
D,SYNCH  
) (Vf  
RMS,SYNCH  
  I   t  
DS(on)  
  f )  
SW  
diode  
O,MAX  
nonoverlap  
resistances (q ) as shown below:  
SA  
where:  
2
2
Pad Size (in /mm )  
Single−Sided 1 oz. Copper  
60−65°C/W  
Vf  
is the forward voltage of the MOSFET’s  
diode  
0.50/323  
intrinsic diode at the converter output current.  
is the non−overlap time between the upper  
t
nonoverlap  
0.75/484  
55−60°C/W  
and lower gate drivers to prevent cross conduction.  
This time is usually specified in the data sheet for the  
driver IC.  
1.00/645  
50−55°C/W  
1.50/968  
45−50°C/W  
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24  
NCP5318  
As with any power design, proper laboratory testing  
LOAD CURRENT, 60 A/DIV  
should be performed to insure the design will dissipate the  
required power under worst case operating conditions.  
Variables considered during testing should include  
maximum ambient temperature, minimum airflow,  
maximum input voltage, maximum loading and component  
OUTPUT VOLTAGE, 50 mV/DIV  
COMP VOLTAGE, 100 mV/DIV  
variations (i.e., worst case MOSFET R  
). Also, the  
DS(on)  
inductors and capacitors share the MOSFET’s heatsinks and  
will add heat and raise the temperature of the circuit board  
and MOSFET. For any new design, it is advisable to have as  
much heatsink area as possible. All too often, new designs are  
found to be too hot and require re−design to add heatsinking.  
20 mS/DIV  
7. Error Amplifier Tuning  
The high frequency gain of the voltage feedback loop  
affects transient response and control loop stability. This  
loop gain can be adjusted by changing the Error Amplifier’s  
high frequency gain, which is done by increasing or  
decreasing the Error Amplifier output loading capacitor  
Figure 26. Converter Output and COMP Response to  
a Load Step (No Droop). 0 W in Series with CAMP  
LOADCCuUrreRnRt ENT, 60 A/DIV  
(C ). The Error Amplifier has a transconductance  
AMP  
characteristic (amplifier output current is proportional to  
amplifier input voltage), causing amplifier output voltage to  
be proportional to amplifier output load impedance.  
OUTPUT VOLTAGE, 50 mV/DIV  
If C  
is too large, the loop gain at high frequencies will  
AMP  
be too low, and the converter output voltage may exhibit an  
underdamped response to a load transient. On the other  
hand, if C  
is too small, there will be too much loop gain  
COMP VOLTAGE, 100 mV/DIV  
AMP  
at high frequencies, which may decrease converter output  
voltage stability. For initial prototype startup, C = 10 nF  
AMP  
is recommended. When reducing C , peak−to−peak  
AMP  
20 mS/DIV  
ripple voltage at the COMP pin should remain less than  
20 mVp−p. Excessive ripple at the COMP pin will  
contribute to PWM pulse jitter. In general, the lowest loop  
gain that achieves acceptable transient response should be  
used.  
Figure 27. Converter Output and COMP Response to  
a Load Step (No Droop), Resistance in Series with  
CAMP  
Adding a resistor in series with C  
will increase control  
AMP  
loop damping in response to load transients as shown in  
Figures 26 and 27, where 1430 W was added in series with  
the 1.8 nF C  
(Adaptive Voltage Positioning not used).  
AMP  
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25  
NCP5318  
8. Adaptive Voltage Positioning  
Two resistors program the Adaptive Voltage Positioning  
(AVP): R and R . These components form a resistor  
divider, shown in Figures 28 and 29, between V , V ,  
DRP FB  
and V .  
FB  
DRP  
OUT  
+ −  
R
CS1  
CS1P  
+
−
G
COMP  
+
−
VID − 19 mV  
S
L1  
0 A  
VDRP  
C
CS1  
Error  
Amp  
CS1N  
CSxP  
R
DRP  
R
FB  
R
CSx  
+
−
G
V
= VID − 19 mV V  
CORE  
FB  
V
VDRP  
= VID − 19 mV  
DRP  
Lx  
C
CSx  
0 A  
I
= 0  
I
= 0  
FB  
DRP  
CSxN  
V
= VID − 19 mV + IBIAS  
w R  
CORE  
VFB  
FB  
Figure 28. AVP Circuitry at No−Load  
+ −  
R
CS1  
CS1P  
+
−
G
COMP  
Error  
+
−
VID − 19 mV  
S
L1  
VDRP  
I
/n  
MAX  
C
CS1  
Amp  
CS1N  
CSxP  
R
DRP  
R
FB  
R
CSx  
+
−
G
V
= VID − 19 mV V  
CORE  
FB  
V
I
= VID − 19 mV +  
DRP  
MAX  
Lx  
VDRP  
• R • G  
L VDRP  
I
/n  
MAX  
C
CSx  
CSxN  
I
I
FB  
DRP  
I
I
= I  
• R • G /R  
VDRP DRP  
DRP  
MAX  
L
= I  
DRP  
FB  
V
= VID − 19 mV − I  
w R  
CORE  
DRP  
w R w G  
FB  
= VID − 19 mV − I  
w R /R  
MAX  
L
VDRP  
FB DRP  
Figure 29. AVP Circuitry at Full−Load  
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26  
NCP5318  
Resistor R is connected between V  
of the controller. At no load, this resistor will conduct the  
very small internal bias current of the V pin. Therefore  
and the V pin  
To choose components, select the appropriate resistor  
ratio based on the desired loadline and sense resistor. At no  
load, the output voltage is positioned 19 mV below the DAC  
output setting. The output voltage droop will follow the  
equation:  
FB  
OUT  
FB  
FB  
R
should be kept below 10 kW to avoid output voltage  
FB  
error due to the input bias current. If the R resistor is kept  
FB  
small, the V bias current can be ignored.  
FB  
R
R
R
SENSE  
DRP  
FB  
(eq. 30)  
+ g   
Resistor R  
is connected between the V  
and V  
OUT  
DRP  
DRP FB  
R
LL  
pins of the controller. At no load, V  
, V and V are  
DRP  
FB  
where:  
at the same potential, and no current should flow through  
or R . As load current increases, the voltage at the  
g = gain of the current sense amplifiers (V/V);  
R
DRP  
FB  
R
= resistance of the sense element (mW);  
= load line resistance (mW).  
SENSE  
V
DRP  
pin rises. The the R and R resistors cause the  
DRP FB  
R
LL  
voltage at V  
to fall in order to keep the voltage at the V  
OUT  
FB  
It is easiest to select a value for R and then evaluate the  
FB  
pin close to the reference voltage. Figure 30 shows the  
DC effect of AVP.  
equation to find R . R is simply the desired output  
DRP LL  
voltage droop divided by the output current. If a sense  
resistor is used to detect inductor current, then R  
will  
0
SENSE  
be the value of the sense resistor. If inductor sensing is used,  
will be the resistance of the inductor. Refer to the  
discussion on Current Sensing for further information.  
Depending on inductor ESR and the loadline desired,  
−0.02  
R
SENSE  
Spec Max  
−0.04  
V
− VID  
OUT  
adding a capacitor on the order of 1 nF in parallel with R  
may improve the transient output voltage waveshape.  
−0.06  
−0.08  
−0.10  
−0.12  
−0.14  
DRP  
Spec Min  
0
10  
20  
30  
(A)  
40  
50  
60  
I
OUT  
Figure 30. The DC Effects of AVP vs. Load  
LOAD CURRENT, 60 A/DIV  
LOAD CURRENT, 60 A/DIV  
OUTPUT VOLTAGE, 50 mV/DIV  
OUTPUT VOLTAGE, 50 mV/DIV  
VDRP VOLTAGE, 200 mV/DIV  
VDRP VOLTAGE, 200 mV/DIV  
5 mS/DIV  
5 mS/DIV  
Figure 32. Output Voltage – 1.2 nF Capacitor  
in Parallel with RDRP  
Figure 31. Output Voltage − No Capacitor  
in Parallel with RDRP  
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27  
NCP5318  
9. Current Sensing  
where R is the inductor ESR. This will provide an adequate  
L
Current sensing is used to balance current between  
different phases, to limit the maximum phase current and to  
limit the maximum system current. Since the current  
information is a part of the control loop, better stability is  
achieved if the current information is accurate and  
noise−free. The NCP5318 uses differential current sense  
amplifiers to achieve the best possible performance.  
Two sense lines are routed for each phase, as shown in  
Figure 29.  
starting point for R  
constructed, the value of R  
fine−tuned in the lab by observing the V  
step change in load current. Tune the R  
and C . After the converter is  
CSx  
CSx  
(and/or C ) should be  
CSx  
CSx  
signal during a  
DRP  
x C  
network  
CSx  
CSx  
by varying R  
to provide a “square−wave” at the V  
CSx  
DRP  
output pin with maximum rise time and minimal overshoot  
as shown in Figure 35.  
For resistive current sensing, choose the current sense  
network (R , C , x = 1, 2, 3, or 4) to reject noise spikes,  
CSx CSx  
For inductive current sensing, choose the current sense  
but maintain the fidelity of the triangular current waveform.  
network (R , C , x = 1, 2, 3 or 4) to satisfy  
CSx CSx  
Lo  
L
(eq. 31)  
R
CSx  
  C +  
CSx  
R
LOAD CURRENT, 60 A/DIV  
LOAD CURRENT, 60 A/DIV  
OUTPUT VOLTAGE,  
50 mV/DIV  
OUTPUT VOLTAGE, 50 mV/DIV  
VDRP VOLTAGE,  
200 mV/DIV  
VDRP VOLTAGE,  
500 mV/DIV  
200 mS/DIV  
200 mS/DIV  
Figure 33. VDRP tuning waveforms. The RC time  
constant of the current sense network is too long  
(Slow): VDRP and VOUT respond too slowly.  
Figure 34. VDRP tuning waveforms. The RC time  
constant of the current sense network is too short  
(Fast): VDRP and VOUT both overshoot.  
LOAD CURRENT, 60 A/DIV  
OUTPUT VOLTAGE,  
50 mV/DIV  
VDRP VOLTAGE,  
200 mV/DIV  
200 mS/DIV  
Figure 35. VDRP tuning waveforms. The RC time  
constant of the current sense network is optimal:  
VDRP and VOUT respond to the load current quickly  
without overshooting.  
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28  
NCP5318  
10. Current Limit Setting  
When the output of the current sense amplifier (COx in the  
block diagram) exceeds the voltage on the I  
will latch off. For inductive sensing, the I  
The proper I  
pin voltage can be calculated by:  
LIM  
V
ILIM  
+ (I  
ń(2   #PH) ) I )   R   (1 ) 0.004   
RIPP−P  
L
L
pin, the part  
pin voltage  
LIM  
(T * 25))   g ) OS  
L
ILIM  
LIM  
should be set based on the inductor’s maximum resistance  
(R ). The design must consider the inductor’s  
resistance increase due to current heating and ambient  
temperature rise. Also, depending on the current sense  
points, the circuit board may add additional resistance. In  
general, the temperature coefficient of copper is +0.39% per  
where:  
I
= maximum converter current (A)  
= maximum 25°C sense element  
resistance (W)  
LMAX  
L
R
g
I
#PH  
T
OS  
L
= maximum current sense to I  
(see tabulated specs)  
gain  
LIM  
°C. If using a current sense resistor (R  
), the I  
pin  
= peak−to−peak phase ripple current (A)  
= number of phases  
SENSE  
LIM  
RIPP−P  
voltage should be set based on the maximum value of the  
sense resistor.  
= inductor temperature at overload (°C)  
L
For the overcurrent protection to avoid false tripping, the  
= maximum I  
offset  
ILIM  
LIM  
voltage at the I  
pin should be set even higher if the  
(see tabulated specs) (V)  
This voltage can be programmed by a resistor divider  
LIM  
R
CSx  
x C time constant is set faster than the L / R time  
CSx O L  
constant. A step load change may cause the current signal to  
appear larger than the actual inductor current and trip the  
current limit at a lower level than desired. The waveforms in  
Figure 36 show a simulation of the current sense signal and  
the actual inductor current during a positive step in load  
from the R  
pin, as shown in Figure 37.  
OSC  
R
OSC  
R1  
R2  
current with values of L = 500 nH, R = 1.6 mW, R  
=
L
CSx  
I
20 kW, and C  
= 0.01 mF. In this case, ideal current signal  
LIM  
CSx  
compensation would require V  
to be 31 k. Due to the  
CSx  
faster than ideal RC time constant, there is an overshoot of  
50% and the overshoot decays with a 200 ms time constant.  
With this compensation, the I  
pin threshold must be set  
LIM  
more than 50% above the full load current to avoid  
triggering current limit during a large output load step.  
Figure 37. Programming the Current Limit  
When the NCP5318 is powered up, the R  
pin will be  
OSC  
1.0 V. This allows the user to determine the resistor divider  
above by:  
R2 = R  
R1 = R  
x V  
− R2  
/ 1.0 V  
TOTAL  
TOTAL  
LIM  
Where R  
is determined as in Section 1 above.  
TOTAL  
Figure 36. Inductive sensing waveform during a load  
step with fast RC time constant (50 ms/div)  
http://onsemi.com  
29  
NCP5318  
PACKAGE DIMENSIONS  
32 LEAD LQFP  
CASE 873A−02  
ISSUE C  
4X  
A
A1  
0.20 (0.008) AB T−U  
Z
32  
25  
1
AE  
AE  
−U−  
−T−  
P
B
V
B1  
DETAIL Y  
BASE  
METAL  
DETAIL Y  
V1  
17  
8
N
9
4X  
−Z−  
0.20 (0.008) AC T−U  
Z
9
F
D
S1  
S
_
8X M  
J
R
DETAIL AD  
G
SECTION AE−AE  
−AB−  
−AC−  
E
C
SEATING  
PLANE  
0.10 (0.004) AC  
W
_
Q
H
K
X
DETAIL AD  
NOTES:  
MILLIMETERS  
DIM MIN MAX  
7.000 BSC  
3.500 BSC  
INCHES  
MIN MAX  
0.276 BSC  
1. DIMENSIONING AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
A
A1  
B
2. CONTROLLING DIMENSION:  
MILLIMETER.  
0.138 BSC  
0.276 BSC  
0.138 BSC  
7.000 BSC  
3.500 BSC  
3. DATUM PLANE −AB− IS LOCATED AT  
BOTTOM OF LEAD AND IS COINCIDENT  
WITH THE LEAD WHERE THE LEAD  
EXITS THE PLASTIC BODY AT THE  
BOTTOM OF THE PARTING LINE.  
4. DATUMS −T−, −U−, AND −Z− TO BE  
DETERMINED AT DATUM PLANE −AB−.  
5. DIMENSIONS S AND V TO BE  
DETERMINED AT SEATING PLANE −AC−.  
6. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION. ALLOWABLE  
PROTRUSION IS 0.250 (0.010) PER SIDE.  
DIMENSIONS A AND B DO INCLUDE  
MOLD MISMATCH AND ARE  
DETERMINED AT DATUM PLANE −AB−.  
7. DIMENSION D DOES NOT INCLUDE  
DAMBAR PROTRUSION. DAMBAR  
PROTRUSION SHALL NOT CAUSE THE  
D DIMENSION TO EXCEED 0.520 (0.020).  
8. MINIMUM SOLDER PLATE THICKNESS  
SHALL BE 0.0076 (0.0003).  
B1  
C
1.400  
1.600 0.055  
0.063  
0.018  
0.057  
0.016  
D
0.300  
1.350  
0.300  
0.450 0.012  
1.450 0.053  
0.400 0.012  
E
F
G
H
0.800 BSC  
0.031 BSC  
0.050  
0.090  
0.450  
0.150 0.002  
0.200 0.004  
0.750 0.018  
0.006  
0.008  
0.030  
J
K
_
12 REF  
_
12 REF  
M
N
0.090  
0.160 0.004  
0.006  
P
0.400 BSC  
1_  
0.016 BSC  
1_  
Q
R
5_  
5 _  
0.150  
0.250 0.006  
0.010  
S
9.000 BSC  
0.354 BSC  
S1  
V
4.500 BSC  
9.000 BSC  
4.500 BSC  
0.200 REF  
1.000 REF  
0.177 BSC  
0.354 BSC  
0.177 BSC  
0.008 REF  
0.039 REF  
V1  
W
X
9. EXACT SHAPE OF EACH CORNER MAY  
VARY FROM DEPICTION.  
http://onsemi.com  
30  
NCP5318  
Intel is a registered trademark of Intel Corporation.  
2
V is a trademark of Switch Power, Inc.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5773−3850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
NCP5318/D  

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