概述
数据手册NCP3232N 概述
High Current Synchronous Buck Converter
NCP3232N 数据手册
通过下载NCP3232N数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载NCP3232N
High Current Synchronous
Buck Converter
The NCP3232N is a high current, high efficiency voltage−mode
synchronous buck converter which operates from 4.5 V to 21 V input
and generates output voltages down to 0.6 V at up to 15 A.
www.onsemi.com
Features
• Wide Input Voltage Range from 4.5 V to 21 V
• 0.6 V Internal Reference Voltage
• 500 kHz Switching Frequency
MARKING
DIAGRAM
1
• External Programmable Soft−Start
• Lossless Low−side FET Current Sensing
• Output Over−voltage Protection and Under−voltage Protection
• System Over−temperature Protection using a Thermistor or Sensor
• Hiccup Mode Operation for all Faults
• Pre−bias Start−up
1
40
NCP3232N
AWLYYWWG
QFN40 6x6, 0.5P
CASE 485CM
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
• Adjustable Output Voltage
= Work Week
= Pb−Free Package
• Power Good Output
• Internal Over−temperature Protection
• These Devices are Pb−Free and are RoHS Compliant*
PIN CONNECTIONS
Typical Application
• Cellular Base Stations
• ASIC, FPGA, DSP and CPU Core and I/O Supplies
• Telecom and Network Equipment
• Server and Storage System
VIN
VIN
EN
11
40
39
38
37
VCC
VB
12
13
14
15
16
VIN
EP42
GND
EP41
VIN
VIN
PGND
VSWH
PGND
36 BST
35
34
33
32
31
VSW
PGND 17
PGND 18
VSWH
VSWH
VSWH
VSWH
VSWH
EP43
19
20
PGND
PGND
(TOP VIEW)
ORDERING INFORMATION
†
Device
Package
Shipping
NCP3232NMNTXG QFN−40
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2015 − Rev. 5
NCP3232N/D
NCP3232N
VB
VCC
VB
LDO
VCC
VB
VB
BST
VIN
OSC
COMP
FB
VB
Control Logic
Ramp Generator
PWM Logic
VREF
+
E/A
−
− and −
VSWH
VSW
UVLO
Soft Start
VCC
SS
OVP, UVP
Power Good
OCP, TSD
Protection
VB
VB
2 mA
Enable
Logic
EN
PG
1.2 V
POR
PGND
VB
VREF
+
−
OTS
ISET
AGND
Figure 1. NCP3232N Block Diagram
www.onsemi.com
2
NCP3232N
PIN DESCRIPTION
Pin No.
Symbol
Description
1
2
3
4
5
6
7
SS
FB
A capacitor from this pin to GND allows the user to adjust the soft−start ramp time.
Output voltage feedback.
COMP
ISET
AGND
OTS
PG
Output of the error amplifier.
A resistor from this pin to ground sets the over−current protection (OCP) threshold.
Analog ground.
Negative input of internal thermal comparator. Tie this pin to ground if not in use.
Power good indicator of the output voltage. Open−drain output. Connect PG to VDD with an extern-
al resistor.
8−14, EP42
VIN
The VIN pin is connected to the internal power NMOS switch. The VIN pin has high di/dt edges and
must be decoupled to ground close to the pin of the device.
15, 29−34,
EP43
VSWH
The VSWH pin is the connection of the drain and source of the internal NMOS switches. At switch
off, the inductor will drive this pin below ground as the body diode and the NMOS conducts with a
high dv/dt.
16−28, 37
35
PGND
VSW
Ground reference and high−current return path for the bottom gate driver and low- side NMOS
IC connection to the switch node between the top MOSFET and bottom MOSFET. Return path of
the high−side gate driver.
36
38
BST
VB
Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
The internal LDO output and input supply for the charge pump. Connect a minimum of 4.7uF ce-
ramic capacitor from this pin to ground.
39
40
VCC
EN
Input Supply for IC. This pin must be connected to VIN.
Logic control for enabling the switcher. An internal pull−up enables the device automatically. The
EN pin can also be driven high to turn on the device, or low to turn off the device. A comparator
and precision reference allow the user to implement this pin as an adjustable UVLO circuit.
EP41
GND
Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissip-
ation.
www.onsemi.com
3
NCP3232N
VIN
VIN
BST
VCC
VOUT
VSWH
VSW
VB
PGND
NCP3232N
ISET
AGND
VPG
EN
FB
OTS
PG
SS
COMP
Figure 2. Typical Application Circuit
ABSOLUTE MAXIMUM RATINGS (measured vs. GND pad, unless otherwise noted)
Rating Symbol
, V
Value
Unit
Power Supply to GND
VSW to GND
V
IN
23
−0.3
V
CC
VSWH, VSW
BST
30
−0.6 (DC)
35 (t < 50 ns)
−5 (t < 100 ns)
V
BST to GND
All other pins
35 (DC)
−0.6 (DC)
40 (t < 50 ns)
V
V
6.0
−0.3
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
T
−40 to +85
−40 to +125
+150
°C
°C
°C
°C
kV
kV
A
T
J
T
J(MAX)
Storage Temperature Range
T
stg
−55 to +150
1.0
Electrostatic Discharge − Human Body Model
Electrostatic Discharge − Charge Device Model
HBM
CDM
2.0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL INFORMATION
HS FET Junction-to-case thermal resistance (Note 1)
LS FET Junction-to-case thermal resistance (Note 1)
Junction-to-ambient thermal resistance
R
1.3
0.6
35
°C/W
°C/W
°C/W
q
JC−HS
R
q
JC−LS
R
q
JA
1. R
thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but
θ
JC
a close description can be found in the ANSI SEMI standard G30-88.
www.onsemi.com
4
NCP3232N
ELECTRICAL CHARACTERISTICS (−40°C < T < +125°C, V = 12 V, for min/max values unless otherwise noted, T = +25°C
J
CC
J
for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
POWER SUPPLY
VIN/VCC Operation Voltage
VB UVLO Threshold (Rising)
VB UVLO Threshold (Falling)
VB Output Voltage
VIN/VCC
4.5
4.1
3.4
4.9
21
4.3
V
V
4.2
3.6
5.15
36
3.8
V
VB
VCC = 6 V, 0 ≤ IB ≤ 40 mA
5.45
110
6.4
V
VB Dropout Voltage
IB = 25 mA, VCC = 4.5 V
mV
mA
VCC Quiescent Current
EN = H, COMP = H, no switching;
PG open; no switching
4.7
Shutdown Supply Current
EN = 0; V = 21 V; PG open
100
55
140
75
mA
mA
CC
EN = 0;V = 4.5 V; PG open
CC
FEEDBACK VOLTAGE
FB Input Voltage
VFB
IFB
T = 25°C, 4.5 V ≤ VCC ≤ 21 V
0.597
0.594
0.6
0.6
0.603
0.606
75
V
J
−40°C < TJ < 125°C; 4.5 V ≤ VCC ≤ 21 V
Feedback Input Bias Current
ERROR AMPLIFIER
VFB = 0.6 V
nA
Open Loop DC Gain (GBD)
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
60
85
24
dB
MHz
°
F0dB,EA
60
COMP pin to GND = 10 pF
2.5
V/m
V
COMP Clamp Voltage, High
COMP Clamp Voltage, Low
Output Source Current
Output Sink Current
3.4
0.465
V
VFB = 0 V
VFB = 1 V
15
20
mA
mA
CURRENT LIMIT
Low−side ISET Current Source
LS_ISET
Sourced from ISET pin, before SS,
30.5
33
+0.31
600
35.5
mA
%/°C
mV
T = 25°C
J
Low−side ISET Current Source
Temperature Coefficient
TC_LS_I−
SET
Low−side OCP Switch−over
Threshold
Guaranteed by design
Low−side Fixed OCP Threshold
LS_OCPth
LS_Tblnk
Guaranteed by design
300
mV
mV
Low−side Programmable OCP
Range
Guaranteed by characterization
< 600
LS OCP Blanking time
PWM
Guaranteed by design
150
92
ns
%
Maximum duty cycle
fsw = 500 kHz, VFB = 0 V
4.5 V < VCC < 21 V
Minimum duty cycle
Minimum GH on−time
PWM Ramp Amplitude
PWM Ramp Offset
VCOMP < PWM Ramp Offset Voltage
Guaranteed by characterization
Guaranteed by characterization
0
%
ns
V
60
VCC/8.6 VCC/6.6 VCC/5.6
0.64
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
5
NCP3232N
ELECTRICAL CHARACTERISTICS (−40°C < T < +125°C, V = 12 V, for min/max values unless otherwise noted, T = +25°C
J
CC
J
for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OSCILLATOR
Oscillator Frequency Range
fsw
fsw = 500 kHz
4.5 V < VCC < 21 V
450
500
550
kHz
Hiccup Timer
thiccup
tss < 1 ms, fsw = 500 kHz
tss > 1 ms, fsw = 500 kHz
4
ms
ms
4xtss
ENABLE INPUT (EN)
EN Input Operating Range
Enable Threshold Voltage
Enable Hysteresis
5.5
V
V
VEN rising
VEN falling
1.11
0.7
1.2
144
0.78
2
1.29
mV
V
Deep Disable Threshold
Enable Pull−up Current
SOFTSTART INPUT (SS)
SS Start Delay
0.9
mA
tSSD
SSEND
ISS
1.33
0.6
ms
V
SS End Threshold
SS Source Current
2.15
2.5
2.8
mA
VOLTAGE MONITOR
Power Good Sink Current
Output Overvoltage Rising
Overvoltage Fault Blanking Time
PG = 0.15 V
10
20
675
20
30
mA
mV
ms
665
685
Guaranteed by design
Output Under−Voltage Trip
Threshold
500
525
550
mV
Under−voltage Protection Blanking
Time
20
ms
UVP Enable Delay
POWER STAGE
t
SS
s
High−side on Resistance
Low−side on Resistance
VFBOOT
RDSONH
RDSONL
VIN/VCC = 5 V, ID = 2 A
VIN/VCC = 5 V, ID = 2 A
IBOOT = 2 mA
6.5
2.9
10
mW
mW
V
5.2
0.28
THERMAL MONITOR (OTS)
OTS comparator reference volt-
age (Rising Threshold)
0.59
0.6
50
0.61
V
OTS comparator reference volt-
age (Falling Hysteresis)
mV
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Guaranteed by characterization
Guaranteed by characterization
150
25
°C
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
6
NCP3232N
TYPICAL CHARACTERISTICS
0.602
0.601
0.600
0.599
0.598
504
V
CC
= 12 V
503
502
501
500
V
= 4.5 V
CC
0.597
0.596
499
498
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Reference Voltage vs. Temperature
Figure 4. Switching Frequency vs.
Temperature
1.23
1.22
1.10
1.09
1.21
1.08
1.20
1.19
1.07
1.06
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Rising Enable Threshold vs.
Temperature
Figure 6. Falling Enable Threshold vs.
Temperature
100
90
80
70
60
7
6
5
4
3
2
50
40
30
20
V
CC
= 12 V
1
0
V
CC
= 12 V, No Switching
10
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Shutdown Current vs. Temperature
Figure 8. Quiescent Current vs. Temperature
www.onsemi.com
7
NCP3232N
TYPICAL CHARACTERISTICS
2.70
2.65
2.60
2.55
2.50
2.45
2.40
50
45
40
35
30
25
20
2.35
2.30
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Soft−start Current vs. Temperature
Figure 10. ISET Current vs. Temperature
0.61
4.30
4.26
4.22
4.18
Rising Threshold
0.60
0.59
0.58
0.57
0.56
4.14
4.10
Falling Threshold
0.55
0.54
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. OTS Threshold vs. Temperature
Figure 12. VB UVLO Rising Threshold vs.
Junction Temperature
3.80
680
679
678
677
676
675
674
673
672
3.76
3.72
3.68
3.64
3.60
671
670
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. VB UVLO Falling Threshold vs.
Junction Temperature
Figure 14. Output OVP vs. Junction
Temperature
www.onsemi.com
8
NCP3232N
TYPICAL CHARACTERISTICS
560
558
556
554
552
550
548
546
544
542
540
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Output UVP vs. Junction
Temperature
Figure 16. Efficiency vs. Load Current (Vin=12 V)
Figure 17. Efficiency vs. Load Current (Vin=5.5 V)
www.onsemi.com
9
NCP3232N
TYPICAL CHARACTERISTICS
CH1 (Blue): VOUT
CH2 (Aqua): PG
CH3 (Purple): EN
CH1 (Blue): VOUT
CH2 (Aqua): PG
CH3 (Purple): EN
Figure 18. Soft Start Waveform
(Vin = 12 V, Vout = 1 V)
Figure 19. Pre−bias Soft Start Waveform
(Vin = 12 V, Vout = 1 V, Pre−bias = 0.5 V)
CH1 (Blue): VOUT
CH1 (Blue): VOUT
CH2 (Aqua): VSW
Figure 20. Output Voltage Hiccup Protection
Waveform
Figure 21. Over−current Protection Pulse
Skipping Waveform
www.onsemi.com
10
NCP3232N
OVERVIEW
Adaptive Non-Overlap Gate Driver
The NCP3232N is a 500 kHz, high efficiency, high current
PWM synchronous buck converter. It operates with a single
supply voltage from 4.5 to 21 V and provide output current
as high as 15 A. NCP3232N utilizes voltage mode with
voltage feed-forward control to response instantly to Vin
changes and provide for easier compensation over the
supply range of the converter. The device also includes
pre-bias startup capability to allow monotonic startup in the
event of a pre-biased output condition.
Protection features include overcurrent protection (OCP),
output over and under voltage protection (OVP, UVP), and
power good. The enable function is highly programmable to
allow for adjustable startup voltages at higher input
voltages. There is also an adjustable soft-start, and
over-temperature/over-voltage comparator, and internal
thermal shutdown.
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET freewheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. NCP3232N implements adaptive dead time
control to minimize the dead time, as well as preventing
shoot through.
Precision Enable (EN)
The ENABLE block allows the output to be toggled on
and off and is a precision analog input.
When the EN voltage exceeds V_EN, the controller will
initiate the soft-start sequence as long as the input voltage
and sub-regulated voltage have exceeded their UVLO
thresholds. V_EN_hyst helps to reject noise and allow the
pin to be resistively coupled to the input voltage or
sequenced with other rails.
If the EN voltage is held below typically 0.8 V, the
NCP3232N enters a deep disable state where the internal
bias circuitry is off. As the voltage at EN continues to rise,
the Enable comparator and reference are active and provide
a more accurate EN threshold. The drivers are held off until
the rising voltage at EN crosses V_EN.
Reference Voltage
The NCP3232N incorporates an internal reference that
allows output voltages as low as 0.6 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
Oscillator Ramp
The ramp waveform is a saw tooth form at the PWM
frequency with a peak-to-peak amplitude of VCC/6.6, offset
from GND by typically 0.64 V. The PWM duty cycle is
limited to a maximum of 92%, allowing the bootstrap
capacitors to charge during each cycle.
An internal 2 mA pullup automatically enables the device
when the EN pin is left floating.
INPUT SUPPLY / VCC
Error Amplifier
VDD
2 uA
The error amplifier’s primary function is to regulate the
converter’s output voltage using a resistor divider connected
from the converter’s output to the FB pin of the controller,
as shown in the Applications Schematic. A type III
compensation network must be connected around the error
amplifier to stabilize the converter. It has a bandwidth of
greater than 24 MHz, with open loop gain of at least 60 dB.
EN
Enable
Logic
1.2 V
Programmable Soft-Start
Figure 22. Enable Functional Block Diagram
An external capacitor connected from the SS pin to
ground sets up the soft start period, which can limit the
start-up inrush current. The soft start period can be
programmed based on the Equation 1.
Pre-bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP3232N supports
pre bias start up by holding off switching until the feedback
voltage and thus the output voltage rises above the set
regulated voltage. If the pre-bias voltage is higher than the
set regulated voltage, switching does not occur until the
output voltage drops back to the regulation point.
CSS @ Vref
tss
+
(eq. 1)
ISS
OCP is the only fault that is active during a soft-start.
www.onsemi.com
11
NCP3232N
Power Good(PG) Operation
Power Good Pullup Voltage
LSOCP Trip Level
Inductor Current
Start
Hiccup
OCP Counter
tHiccup = 4xtSS
1
2
3
Skipped Pulses showing Skip Count
Figure 23. LSOCP Function with Counters and Power Good Shown (exaggerated for informational purposes)
PROTECTION FEATURES
Undervoltage Protection Threshold (UVP), the device will
enter hiccup mode.
Hiccup Mode
The NCP3232N utilizes hiccup mode for all of its fault
conditions. Upon entering hiccup mode after a fault
detection, the NCP3232N turns off the high side and low
side FETs and PG goes low. It waits for tHICCUP ms before
reinitiating a soft-start. tHiccup is defined as four soft start
timeouts (tss). The equation for tss is shown in Equation 1.
OCP is the only active fault detection during the hiccup
mode soft start.
Under Voltage Protection (UVP)
A UVP circuit monitors the VFB voltage to detect an
under voltage event. If the VFB voltage is below this
threshold for more than 20 ms, a UVP fault is set and the
device will enter hiccup mode.
Over Current Protection (OCP)
The NCP3232N over current protection scheme senses
the peak freewheeling current in the low-side FET (LSOCP)
after a blanking time of 150 ns as shown in Figure 23. The
low-side FET drain-to-source voltage, VDS, is compared
against the voltage of a fixed, internal current source, ISET
and a user-selected resistor, RSET. Voltage across the
low-side FET is sensed from the VSW pin to GND.
After an OCP detection, the NCP3232N keeps the
high-side FET off until the Low-side FET current falls
below the trip point again and the next clock cycle occurs.
An internal OCP counter will count up to 3 consecutive
LSOCP events. After the third consecutive count, the device
enters hiccup mode.
Over Temperature Comparator (OTS)
The NCP3232N provides an over-temperature shutdown
(OTS) comparator with 50 mV hysteresis and a 0.6 V
reference in order to remotely sense an external temperature
detector or thermistor. When the voltage at the OTS pin rises
above 0.6 V, the drivers stop switching and both FETs
remain off. When this voltage drops below typically 0.55 V,
a new soft-start cycle is generated automatically. Tie the
OTS pin to ground if this function is not required.
Over Voltage Protection (OVP)
When the voltage at the FB pin (VFB) is above the OVP
threshold for greater than 20 ms (typical), an OVP fault is set.
The high side FET (HSFET) will turn off and the low side
FET (LSFET) will turn on to discharge output voltage. The
open-drain PG pull down will turn on at that point as well,
thus pulling PG low. Once VFB has fallen below the
To prevent nuisance trips, there is a backup counter that
will reset the OCP counter after 7 consecutive cycles without
an LSOCP trigger. The backup counter is reset and then
started again after each OCP trip until the third OCP count
as stated above occurs.
www.onsemi.com
12
NCP3232N
Over Current Protection Threshold (ISET)
Ground Return for Power and Signals: Solid,
uninterrupted ground planes must be present and adjacent to
the high current path.
Copper Shapes on Component Layers: Large copper
planes on one or multiple layers with adequate vias will
increase thermal transfer, reduce copper conduction losses,
and minimize loop inductance. Greater than 20 A designs
require 2~3 layer shapes or more, increasing the number of
layers will only improvement performance.
Via Placement for Power and Ground: Place enough vias
to adequately connect outer layers to inner layers for thermal
transfer and to minimize added inductance in layer
transition. Multiple vias should be placed near important
components like input ceramics and output ceramic
capacitors.
Key Signal Routes: Do not route sensitive signals, such as
FB near or under noisy nets such as the switch node VSW
and BST node, to reduce noise coupling effects on the
sensitive lines.
The NCP3232N allows the user to adjust the LSOCP
threshold with an external resistor, RSET. This resistor,
along with an internal temperature compensated current
source, ISET, sets the current limit reference voltage for the
LSOCP comparator.
Internally, a current sense circuit samples the voltage from
VSW to GND. This voltage is then multiplied by a factor of
2X and compared against the ISET*RSET voltage
threshold.
The basic design equation for LSOCP trip point selection
is:
2 ISET RDSON
(eq. 2)
RSET +
33 10−6
In case RSET is not connected, the device switches the
OCP threshold to a fixed 300 mV value: an internal safety
clamp on ISET is triggered as soon as the ISET voltage
reaches 600 mV, enabling the 300 mV fixed threshold.
Thermal Shutdown (TSD)
To improve the Low-side OCP accuracy, users should use
single ground connection instead of separate analog ground
and power ground. Make sure that the inner layers (at least
2nd layer, 3rd layer and 4th layer) are dedicated for ground
plane. Do not use other copper planes to break or interrupt
the shape of ground plane, which may add more parasitic
components to affect the sensing accuracy.
The NCP3232N protects itself from overheating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF. Once the
temperature drops below the falling hysteresis threshold, the
voltage at the COMP pin will be pulled below the ramp
valley voltage and a soft-start will be initiated.
Thermal management consideration: the major heat flow
path from package to the ambient is through the copper on
the PCB, the area and thickness of copper plane affect the
themeral performance; maximize the copper coverage on all
the layers to increase the effective thermal conductivity of
the board. This is importatnt especially when there is no heat
sinks attached to the PCB on the other side of the package;
add as many thermal vias as possible directly under the
package ground pad to maximize the effective out-of-plane
thermal conductivity of the board; all the thermal vias must
be either plated (copper) shut or plugged and capped on both
sides of the board. This prevents solder seeping in to the
thermal vias causing solder voids. Solder voides are higher
detrimental to the thermal and electrical performance of the
package; to ensure reliability and performance, the solder
coverage should be at least 85 percent. This means the total
voids on the ground pad should be less than 15 percent with
no single void larger than 1 mm. Several smaller voids are
always better than a few big voids.
Power Good Monitor (PG)
NCP3232N monitors the output voltage and signal when
the output is out of regulation or during a non-regulated
pre-bias condition, or fault condition. When the output
voltage is within the OVP and UVP thresholds, the power
good pin is a high impedance output. If the NCP3232N
detects an OCP, OVP, UVP, OTS, TSD or is in soft start, it
pulls PG pin low. The PG pin is an open drain 5-mA pull
down output.
Layout Guideline
When laying out a power PCB for the NCP3232N there
are several key points consider.
General Layout Guide: these are the common techniques
for high frequency high power board layout design.
Base component placement: High current path
components should be placed to keep the current path as
tight as possible. Placement of components on the bottom of
the board such as input or output decoupling can add loop
inductance.
www.onsemi.com
13
NCP3232N
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 485CM
ISSUE O
D
A B
NOTES:
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN ONE
LOCATION
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
L1
DETAIL A
ALTERNATE
E
CONSTRUCTIONS
2X
MILLIMETERS
0.15
C
DIM MIN
MAX
1.00
0.05
EXPOSED Cu
MOLD CMPD
A
A1
A3
b
0.80
−−−
0.20 REF
2X
TOP VIEW
0.15
C
0.18
0.30
DETAIL B
(A3)
D
6.00 BSC
DETAIL B
0.10
C
C
D2
D3
E
2.30
1.40
2.50
1.60
ALTERNATE
CONSTRUCTION
A
43X
6.00 BSC
E2
E3
E4
e
G
K
4.30
1.90
1.64
0.50 BSC
2.20 BSC
0.20
0.30
−−−
4.50
2.10
1.84
0.08
SIDE VIEW
D2
A1
SEATING
PLANE
NOTE 4
C
0.10
C A B
−−−
0.50
0.15
NOTE 5
40X L
D3
L
L1
G
DETAIL A
SOLDERING FOOTPRINT*
6.30
E3
4.56
2.56
40X
0.63
E2
1.66
E4
1
1
G
40
K
e
2.16
40X b
e/2
0.10
C
C
A
B
4.56
6.30
G
NOTE 3
0.05
BOTTOM VIEW
2.16
40X
0.30
PKG
OUTLINE
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP3232N/D
NCP3232N 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| NCP3232NMNTXG | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3233 | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3233MNTXG | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3233_16 | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3235 | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3235MNTXG | ONSEMI | High Current Synchronous Buck Converter | 获取价格 |
|
| NCP3237MNTXG | ONSEMI | 8 A Integrated Synchronous Buck Regulator | 获取价格 |
|
| NCP3284 | ONSEMI | Single-Phase Voltage Regulator | 获取价格 |
|
| NCP3284A | ONSEMI | Single-Phase Voltage Regulator | 获取价格 |
|
| NCP3284AMNTXG | ONSEMI | Single-Phase Voltage Regulator | 获取价格 |
|
NCP3232N 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
