NCP3284A [ONSEMI]
Single-Phase Voltage Regulator;型号: | NCP3284A |
厂家: | ONSEMI |
描述: | Single-Phase Voltage Regulator |
文件: | 总13页 (文件大小:383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Single-Phase Voltage
Regulator
High Efficiency, Integrated Power MOSFETs
NCP3284, NCP3284A
The NCP3284/A, a single−phase synchronous buck regulator,
integrates power MOSFETs to provide a high−efficiency and
compact−footprint power management solution. The NCP3284 is able
to deliver up to 30 A TDC output current, 35 A TDC for NCP3284A,
over a wide input and output operating voltage range. Operating in
high switching frequency up to 1 MHz allows employing small size
inductors and capacitors while maintaining high efficiency due to
integrated solution with high performance power MOSFETs. It
provides differential voltage sense, flexible soft−start programming,
and comprehensive protections.
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MARKING
DIAGRAM
NCP3284x
AWLYWWG
PQFN37 5x6, 0.5P
CASE 483BZ
Features
• V = 4.5 V ~ 18 V with Input Feedforward
IN
A
WL
Y
WW
G
= Assembly Site
= Wafer Lot Number
= Year of Production
= Work Week Number
= Pb−Free Designator
• V
= 0.8 V ~ 5.5 V with Remote Voltage Sense
OUT
• Fsw = 500k/600k/800k/1 MHz Switching Frequency
• Output Current: NCP3284 up to 30 A Continuous, 45 A Pulsed
Output Current: NCP3284A up to 35 A Continuous, 50 A Pulsed
• Integrated 5 V LDO or External 5 V Supply
PINOUT
• Enable with Programmable V UVLO
IN
• Selectable Forced CCM and Auto DCM/CCM for High Efficiency at
Light Load
36
35
34
33
32
31
30
29
• Programmable Soft Start
ILIM
28
1
2
VOS
• Output Discharge in Shutdown
PGOOD
27 EN
• Programmable Current Limit
VIN
3
26
BOOT
• Under−Voltage Protection and Over−Voltage Protection
• Recoverable Thermal Shutdown Protection
• Selectable Protection Mode (Latch−off or Hiccup)
• Power Good Indicator
VCC
4
25 PHASE
24 PVIN
23 PVIN
22 PVIN
VDRV
GL
5
PGND
PVIN
GL
6
PGND
PGND
7
• PQFN37, 5x6 mm, 0.5 mm Pitch Package
• This Device is Pb−Free and is RoHS Compliant
8
21
20
19
PVIN
PGND
PGND
9
PVIN
PGND
Typical Applications
10
• Point of Load
11
12
13
14
15
16
17
18
• Telecom and Networking
• Server and Storage System
• Computing Applications
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
February, 2021 − Rev. 7
NCP3284/D
NCP3284, NCP3284A
VIN
PVIN
VIN
PGND
BOOT
VDRV
VCC
PHASE
VOUT
NCP3284/A SW
AGND
FB
PGOOD
EN
VSNS −
VOS
MODE/
FSET
SS
ILIM
Figure 1. Typical Application Circuit with Single Input Power Supply (LDO Enabled)
+5V
VIN
PVIN
VIN
PGND
VDRV
VCC
BOOT
PHASE
SW
VOUT
NCP3284/A
AGND
FB
PGOOD
EN
VSNS −
VOS
MODE/
FSET
SS
ILIM
Figure 2. Typical Application Circuit with External 5 V Supply for VCC (LDO Disabled)
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2
NCP3284, NCP3284A
VIN
BOOT
PHASE
MOSFETs
VDRV
PVIN
5V
LDO
VDRV
SW
GL
Gate Drive
VDRV
Vref
FB
VCC
PGND
Gate Driver
Control Logic
&
EN
Protections
&
PWM
VR Ready
EN_INT
PGOOD
Soft Start
Vref
HICC
UP#
PWM
Control
FB
COMP
VSNS
−
VIN
AGND
VOS
MODE
/FSET
Controller
Programming
Detection
SS
ILIM
Figure 3. Functional Block Diagram
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3
NCP3284, NCP3284A
PIN DESCRIPTION
Pin
1
Name
ILIM
Type
Description
Analog Output
Logic Output
Current Limit. A resistor between this pin and AGND to program current limit.
2
PGOOD
Power Good. Open−drain output. Provides a logic high valid power good output
signal, indicating the regulator’s output is in regulation window.
3
VIN
Power Input
Power Supply Input of LDO. Power supply input pin of internal 5 V LDO. A 1.0 mF
or more ceramic capacitor must bypass this input to power ground.
The capacitor should be placed as close as possible to this pin. A direct short
from this pin to VDRV (pin 5) disables the internal LDO for applications with an
external 5 V supply as power of VDRV and VCC.
4
5
VCC
Analog Power
Analog Power
Supply Voltage Input of Controller. A 2.2 mF or larger ceramic capacitor bypasses
this input to GND. This capacitor should be placed as close as possible to this pin.
VDRV
Output of LDO and Supply Voltage Input of Gate Drivers. Output of integrated
5.0 V LDO and power supply input of gate drivers. A 4.7 mF/25 V or larger
ceramic capacitor bypasses this pin to PGND. The capacitor should be placed as
close as possible to this pin.
6
GL
Analog Output
Power Ground
Gate of Low−Side MOSFET. Internally connected to the gate of the low−side
power MOSFET. No external connection required.
7~10,19
PGND
Power Ground. These pins are the power supply ground pins of the device, which
are connected to source of internal low−side power MOSFET. Must be connected
to the system ground.
11~18
20~24
SW
Power
Switch Node. Pins to be connected to an external inductor. These pins are
Bidirectional
interconnection between internal high−side MOSFET and low−side MOSFET.
PVIN
Power Input
Power Supply Input. These pins are the power supply input pins of the device,
which are connected to drain of internal high−side power MOSFET. A 22 mF or
more ceramic capacitor must bypass this input to PGND. The capacitors should
be placed as close as possible to these pins.
25
26
27
28
29
PHASE
BOOT
EN
Power Return
Phase Node. Provides a return path for integrated high−side gate driver.
It is internally connected to source of high−side MOSFET.
Power
Bidirectional
Bootstrap. Provides bootstrap voltage for high−side gate driver. A 0.22 mF/25 V
ceramic capacitor is required from this pin to PHASE (pin 25).
Logic Input
Analog Input
Analog Input
Enable. Logic high enables controller while logic low disables controller. Input
supply UVLO can be programmed at this pin.
VOS
SS
Voltage Sense. Remote output voltage sense. Connect to VOUT through 1 kW
series resistor.
Soft Start. A resistor between this pin and GND to program the soft−start slew
rate and options.
30
31
FB
Analog Input
Analog Input
Feedback. Inverting input to error amplifier.
VSNS−
Voltage Sense Negative Input. Connect this pin to remote voltage negative sense
point.
32
AGND
NC
Analog Ground Analog Ground. Ground of controller. Must be connected to the system ground.
33~34
−
No Connection.
35
HICCUP#
Analog Input
Latch−Off / Hiccup#. Float this pin to enable latch−off mode protections (OCP/
UVP/OVP); Ground this pin to ground to enable hiccup mode protections.
36
MODE/FSET
Analog Input
Mode and Frequency Set. A resistor between this pin and AGND to program
operation mode and nominal switching frequency.
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4
NCP3284, NCP3284A
MAXIMUM RATINGS
Value
MIN
MAX
Rating
Symbol
Unit
V
Power Supply Voltage to PGND
PHASE/SW to PGND
V
, V
VIN
25
PVIN
V
, V
SW
−0.6
−5 (<50 ns)
25
V
PHASE
28 (<10 ns)
PVIN to SW/PHASE
V
−0.3
−5 (<10 ns)
25
V
PVIN_SW
33 (<10 ns)
Driver Supply Voltage to PGND
Analog Supply Voltage to AGND
BOOT to PGND
V
−0.3
−0.3
−0.3
5.5
6.5
V
V
V
VDRV
V
VCC
BOOT_PGND
30
33 (<10 ns)
BOOT to PHASE/SW
GL to PGND
BOOT_PHASE/SW
GL
−0.3
6.5
V
V
−0.3
−2 (<200 ns)
VDRV+0.3
VSNS− to AGND
VSNS−
−0.2
−0.3
−0.3
0.2
0.3
V
V
PGND to AGND
PGND
Other Pins
VCC+0.3
2000
2000
100
V
Human Body Model (HBM) ESD Rating are (Note 1)
Charge Device Model (CDM) ESD Rating are (Note 1)
Latch up Current: (Note 2)
ESD HBM
ESD CDM
V
V
I
LU
−100
−40
−40
−55
mA
_C
_C
_C
_C/W
_C/W
_C/W
W
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
T
T
125
J
100
A
T
STG
150
Thermal Resistance Junction to Top Case(Note 3)
Thermal Resistance Junction to Board (Note 3)
Thermal Resistance Junction to Ambient (Note 3)
Maximum Power Dissipation (Note 4)
Moisture Sensitivity Level (Note 5)
R
R
0.8
0.9
26.7
3.75
1
Y
JC
JB
JA
D
Y
R
q
P
MSL
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and
2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors etc.)
4. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on T
= 125°C and T = 25°C.
JMAX
A
5. Moisture Sensitivity Level (MSL): IPC/JEDEC standard: J−STD−020A.
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5
NCP3284, NCP3284A
ELECTRICAL CHARACTERISTICS (V = 12 V, typical values are referenced to T = T = 25°C, Min and Max values are referenced
IN
A
J
to T = T = −40°C to 125°C. unless other noted.)
A
J
Characteristics
Test Conditions
Symbol
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE MONITOR
VCC Under−Voltage (UVLO) VCC falling
V
4.0
V
DDUV−
Threshold
VCC OK Threshold
VCC rising
V
DDOK
4.5
V
VCC UVLO Hysteresis
SUPPLY CURRENT
PVIN Shutdown Current
V
200
mV
DDHYS
EN low
I
−
−
4.8
3.5
20
mA
SDPVIN
V
Quiescent Supply
EN high, no switching
EN low
I
mA
LDO enabled,
6.4
IN
QVIN
Current
VIN = 18 V, VCC = VDRV
(VCC Current Included)
LDO disabled,
VIN = VDRV = VCC = 4.5 V
−
−
−
3.5
42
63
6.4
60
V
IN
Shutdown Current
I
mA
LDO enabled,
VIN = 18 V, VCC = VDRV
SDVIN
(VCC Current Included)
T = T = 25 °C
A J
LDO disabled,
VIN = VDRV = VCC = 4.5 V
150
5 V LINEAR REGULATOR
Output Voltage
6V < VIN < 18 V, IDRV = 0 to 30 mA (External)
EN high, no switching
V
DRV
4.8
5.07
5.4
V
Dropout Voltage
VIN = 5 V, IDRV = 50 mA (External), EN high,
no switching
V
DO
200
mV
PWM MODULATION
Minimum On Time
(Note 6)
(Note 6)
T
50
ns
ns
on_min
Minimum Off Time
T
150
off_min
VOLTAGE REGULATION
Regulated Feedback Voltage FB to VSNS−
V
795
800
805
50
mV
nA
FB
FB
VOLTAGE ERROR AMPLIFIER
FB, VSNS− Bias Current
V
FB
= V
= 1.0 V
I
−50
VSNS−
CURRENT−SENSE AMPLIFIER
Closed−Loop DC Gain
GAIN
−10
10
−
V/V
MHz
mV
CA
−3 dB Gain Bandwidth
Input Offset Voltage
ENABLE
(Note 6)
= V
BW
CA
V
– V
(Note 6)
V
osCS
−500
500
osCS
SW
PGND
EN On Threshold
V
rising
V
1.32
1.11
1.43
1.22
40
1.54
1.31
V
V
EN
EN_THR
EN Off Threshold
V
EN
falling
V
EN_TH
Hysteresis Resistance
Hysteresis Current
EN Input Leakage Current
SWITCHING FREQUENCY
R
kW
mA
mA
HYS
I
5.4
EN_HYS
EN = 5 V
I
1.0
EN_LK
Switching Frequency in
CCM
1% Resistor from
MODE/FSET Pin to
AGND,
Vout = 5 V
(Note 6)
F
kHz
2.49k or 14.0k
12.1k or float
0 or 10.5k
1000
800
600
500
50
SW
4.99k or 7.50k
Source Current from Mode/
FSET Pin
I
45
55
mA
FSET
SOFT START
System Reset Time
Measured from EN to start of soft start
T
RST
0.7
ms
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NCP3284, NCP3284A
ELECTRICAL CHARACTERISTICS (V = 12 V, typical values are referenced to T = T = 25°C, Min and Max values are referenced
IN
A
J
to T = T = −40°C to 125°C. unless other noted.)
A
J
Characteristics
Test Conditions
Symbol
MIN
TYP
MAX
UNITS
SOFT START
Soft Start Time
1% Resistor from SS
Pin to AGND
T
ms
0 or 4.53k
1.0
2.0
4.0
8.0
50
1.1
2.2
4.4
8.8
55
SS
1.5k or 5.76k
12.1k or float
3.48k or 8.87k
Source Current from SS Pin
PGOOD
I
SS
45
mA
ms
PGOOD Shutdown Delay
From EN to PGOOD de−assertion
(Note 6)
1.0
PGOOD Low Voltage
PGOOD Leakage Current
PROTECTIONS
I
= 4 mA Sink
V
0.3
1.0
V
PGOOD
lPGOOD
PGOOD = 5 V
I
mA
lkgPGOOD
Valley Current Limit
Threshold
NCP3284
I
A
A
R
R
R
R
R
R
R
R
R
R
= 24.9 kW
= 21.5 kW
= 16.2 kW
= 12.1 kW
= 33.2 kW
= 30.1 kW
= 24.9 kW
= 21.5 kW
= 16.2 kW
= 12.1 kW
36.5
31.5
24.0
18.0
49.5
45.5
37.5
32.5
24.5
18.0
OC
LIM
LIM
LIM
LIM
LIM
LIM
LIM
LIM
LIM
LIM
T = T = −40°C to 125°C
A
J
NCP3284A
I
OC
(Note 6)
Valley Current Limit
Accuracy
I
%
V
T = 25°C
−5
5
OC_ACCY
J
T = −40°C to 125°C (Note 6)
J
−10
0.15
10
Fast Under Voltage
Protection (FUVP)
Threshold
FB to AGND
0.2
0.25
Fast Under Voltage
(Note 6)
1.0
3.0
ms
Protection (FUVP) Delay
Slow Under Voltage
Protection (SUVP)
Threshold
COMP to GND (Note 6)
V
Slow Under Voltage
Protection (SUVP) Delay
(Note 6)
50
ms
Over Voltage Threshold
FB rising
0.95
140
1.0
1.05
V
Over Voltage Protection
Hysteresis
FB falling (Note 6)
−10
mV
Over Voltage Debounce
Time
FB rising to GL high
1.0
ms
Hiccup Idle Time
Pin 35 is grounded (Note 6)
(Note 6)
32
ms
Thermal Shutdown (TSD)
Threshold
T
sd
150
°C
Recovery Temperature
Threshold
(Note 6)
(Note 6)
T
rec
125
50
°C
Thermal Shutdown (TSD)
Debounce Time
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design, not tested in production.
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7
NCP3284, NCP3284A
DETAILED DESCRIPTION
General
power MOSFETs. It provides differential voltage sense,
flexible soft−start programming, and comprehensive
The NCP3284/A, a single−phase synchronous buck
regulator, integrates power MOSFETs to provide a
high−efficiency and compact−footprint power management
solution. The NCP3284/A is able to deliver up to 30 A TDC
output current on a wide output voltage range. Operating in
high switching frequency up to 1 MHz allows employing
small size inductors and capacitors while maintaining high
efficiency due to integrated solution with high performance
protections.
Operation Modes
Operation mode and switching frequency are
programmed at MODE/FSET pin with a 1% tolerance
resistor as shown in Table 1.
Table 1. MODE AND SWITCHING FREQUENCY CONFIGURATION
Resistance @ MODE/FSET Pin (W, + 1%)
Frequency (kHz)
Operation Mode
FCCM
0
600
1000
500
2.49k
4.99k
7.5k
FCCM
Auto CCM/DCM
FCCM
500
10.5k
12.1k
14.0k
Float
600
Auto CCM/DCM
Auto CCM/DCM
Auto CCM/DCM
FCCM
800
1000
800
Current−Mode RPM Operation
inductor current is continuous and the device operates in
quasi−fixed switching frequency in medium and heavy load
range, while the inductor current becomes discontinuous
and the device automatically operates in PFM mode with an
adaptive fixed on time and variable switching frequency in
light load range.
The NCP3284/A operates with the current−mode
Ramp−Pulse−Modulation (RPM) scheme. In Forced CCM
mode, the inductor current is always continuous and the
device operates in quasi−fixed switching frequency, which
has a typical value programmed by users through a resistor
at the MODE/FSET pin. In Auto CCM/DCM mode, the
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8
NCP3284, NCP3284A
Soft Start and Shut Down
period TRST , 0.7 ms typical, after the device is enabled.
When the device is disabled or UVLO happens, the device
shuts down immediately and both high−side and low−side
MOSFETs are off. A timing diagram of power up/down is
shown in Figure 4.
The NCP3284/A has a soft start function which also
operates well under a pre−biased output condition. The
NCP3284/A’s soft start time is externally programmed at SS
pins. The output starts to ramp up following a system reset
Enable
VDRV
TRST
TBST
TSS
Vout
PGOOD
GH−SW
GL
240 ns
GL
2.0 ms
= 10 ms
TBST
Figure 4. Timing Diagram of Power Up/Down Sequence
Bootstrap Capacitor Voltage Refreshing
special care needs to be taken in applications with Vout
≥ 1.8 V and auto DCM/CCM mode enabled. To make sure
the bootstrap capacitor has an enough voltage level for
proper operation of high−side gate driver, there is a
minimum load requirement to limit the minimum switching
frequency not to go below 2 kHz. For a typical 5 V output
application with auto DCM/CCM mode enabled, the
minimum load current may need to be higher than 2 mA.
In the NCP3284/A, a bootstrap circuit is employed to
provide supply voltage for the high−side gate driver. An
external 0.22 mF/25 V ceramic capacitor is connected
between BOOT pin and PHASE pin to hold up the bootstrap
voltage. In order to charge up this capacitor just before a soft
start, 5 consecutive pulses are sent to GL, gate of the
low−side MOSFET, as shown in Figure 4.
In forced CCM mode, the bootstrap voltage is refreshed
cycle−by−cycle and always fully charged. However, a
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9
NCP3284, NCP3284A
Enable and Input UVLO
limit I
can be calculated from the programmed valley
LMT
The NCP3284/A is enabled when the voltage at EN pin is
higher than a summing voltage level of an internal threshold
current limit I
and inductor current ripple.
LMT_Valley
Vo (VIN * Vo)
2 VIn L FSW
ILMT + ILMT_Valley
)
V
EN_TH
and a hysteresis. The hysteresis can be programmed
by an external resistor R connected to EN pin as shown in
EN
Vo (VIN * Vo)
2 VIN L FSW
Figure 5. The high threshold V
in ENABLE signal is
(eq. 7)
EN_H
+ 1.5412 RIlim
)
VEN_H + VEN_TH ) VEN_HYS
(eq. 1)
where R
is resistance of the programming resistor at
Ilim
ILIM pin, V is input voltage, V is output voltage, L is
IN
O
filter inductance, and F is nominal switching frequency.
SW
OCP detection starts from the beginning of soft−start time
VEN_TH
EN_Int
T
, and it ends in shutdown, latch−off, and hiccup idle time.
SS
VEN_H
The inductor current is monitored by voltage sensing
between the SW pin and PGND pin. If over current happens
and lasts for more than 50 ms, the device turns to either
latch−off or hiccup. The device may enter into under voltage
protection before OCP latch−off/hiccup happens if the
output voltage drops down very fast.
VEN_L
EN
ENABLE
REN
RHYS
IEN_HYS
Figure 5. Enable and Hysteresis Programming
Under Voltage Protection (UVP)
UVP detection starts when PGOOD delay T
The low threshold V
in ENABLE signal is
EN_L
is
d_PGOOD
expired right after a soft start, and it ends in shutdown,
latch−off, and hiccup idle time. The NCP3284/A pulls
PGOOD low and turns off both high−side and low−side
MOSFETs once FB voltage drops below 0.2 V for more than
1.0 ms.
VEN_L + VEN_TH
(eq. 2)
(eq. 3)
The hysteresis V
is
EN_HYS
VEN_HYS + IEN_HYS (RHYS ) REN
)
A UVLO function for input power supply can be
implemented at EN pin. As shown in Figure 6, the UVLO
threshold can be programmed by two external resistors. The
Over Voltage Protection (OVP)
OVP detection starts from the beginning of soft−start time
low threshold V
in V signal is
IN_L
IN
T
, and it ends in shutdown, latch−off, and hiccup idle time.
SS
REN1
REN2
During normal operation the output voltage is monitored at
the FB pin. If FB voltage exceeds the OVP threshold for
more than 1 ms, OVP is triggered and PGOOD is pulled low.
Meanwhile, the high−side MOSFET is latched off and the
low−side MOSFET is turned on. After the OVP trips, the
DAC ramps slowly down to zero, having a negative slew rate
at the same value of soft start to reduce the negative output
voltage spike. The low−side MOSFET toggles between on
and off as the output voltage follows the DAC ramping
down. After the DAC gets to zero, the high−side MOSFET
holds off and the low−side MOSFET remains on.
+ ǒ Ǔ
VIN_L
) 1 VEN_TH
(eq. 4)
(eq. 5)
The high threshold V
in V signal is
IN_H
IN
VIN_H + VIN_L ) VIN_HYS
The hysteresis V
is
IN_HYS
REN1
REN2
ǒ ǒ1 ) Ǔ Ǔ
VIN_HYS + IEN_HYS
RHYS
) REN1
(eq. 6)
VIN_H
VIN_L
VEN_TH
VIN
EN_Int
Latch−Off or Hiccup in Protections
The NCP3284/A can be configured to have either
latch−off mode or hiccup mode, for the protections (OCP,
UVP, and OVP), by means of leaving pin 35 float or shorting
it to ground.
REN1
EN
RHYS
REN2
IEN_HYS
To restart the device after latch−off, the system needs to
cycle either VCC or EN to an off state, then restore, before
a normal power−up sequence follows including system reset
and auto calibration.
Figure 6. Enable and Input Supply UVLO Circuit
If hiccup mode is selected, the NCP3284/A starts to count
idle time of 32 ms once PGOOD is pulled low due to any of
the protections. After the end of the hiccup idle time, a
normal power up sequence occurs, including system reset
and auto calibration.
To avoid undefined operation, EN pin should not be left
floating in applications.
Over Current Protection (OCP)
The NCP3284/A protects the converter from over current
using a cycle−by−cycle current limit. The average current
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10
NCP3284, NCP3284A
Thermal Shutdown (TSD)
The NCP3284/A has an internal thermal shutdown
protection to protect the device from overheating in an
• VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC and VDRV pins. The
filter resistor at the VCC pin should not be higher than
2.2ĂW to prevent large voltage drops.
• Switching Node: SW node should be a copper pour, but
compact because it is also a noise source
• Bootstrap: The bootstrap cap and optional resistor need
to be very close and directly connected between pin 26
(BST) and pin 25 (PHASE). No need to externally
connect pin 25 to SW node because it has been
internally connected to other SW pins.
• Ground: It is good to have multiple layers of GND
planes on the PCB. Directly connect the exposed
PGND pad to GND planes through multiple vias.
Connect AGND pin to GND planes through a via close
to the AGND pin.
extreme case that the die temperature exceeds 150°C. T
SD
detection is activated when VCC and EN are valid. Once the
thermal protection is triggered, the whole chip shuts down.
If the temperature drops below 125°C, the system
automatically recovers and a normal power−up sequence
follows.
Power Good (PGOOD)
PGOOD is asserted in normal operation after soft start
ends, and it is pulled low in protections and shutdown. The
PGOOD pin is an open−drain pin and its internal pull−down
control circuit is powered by VCC. To avoid an invalid
PGOOD indication when VCC is not ready, it is
recommended to have the external pull−up resistor at the
PGOOD pin connected to VCC. If VCC is provided by an
external source, it should be applied prior to VIN to avoid
erroneous PGOOD glitches.
• Voltage Sense: Use a Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
Keep the FB trace short to minimize its capacitance to
ground.
LAYOUT GUIDELINES
Thermal Layout Considerations
Electrical Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
Good electrical layout is key to ensure proper operation,
high efficiency, and noise reduction. Electrical layout
guidelines are:
• Power Paths: Use wide and short traces for power paths
(such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance, high−frequency loop area, and
undesirable copper losses.
• Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to PVIN and PGND pins
• The exposed pads must be well soldered to the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome around the IC and
underneath the exposed pads to connect the inner
ground layers to reduce the IC thermal impedance path.
• Use large area copper pours to help thermal conduction
and radiation.
• Do not put the inductor too close to the IC, thus the heat
sources are distributed.
DEVICE ORDERING INFORMATION
†
Device
NCP3284MNTXG
NCP3284AMNTXG
Current
30 A
Package
Shipping
PQFN37
(Pb−Free)
2500 / Tape & Reel
35 A
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN37 5x6, 0.5P
CASE 483BZ
ISSUE O
DATE 13 DEC 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66497G
PQFN37 5X6, 0.5P
PAGE 1 OF 1
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