NCP1239ED65R2G [ONSEMI]
Fixed Frequency CurrentâMode Controller for Flyback Converter;
| 型号： | NCP1239ED65R2G |
| 厂家： | 
ONSEMI |
| 描述： | Fixed Frequency CurrentâMode Controller for Flyback Converter 开关 光电二极管 |
| 文件： | 总26页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1239
Fixed Frequency
Current‐Mode Controller for
Flyback Converter
The NCP1239 is a fixed-frequency current-mode controller
featuring a high-voltage start-up current source to provide a quick and
lossless power-on sequence. This function greatly simplifies the
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design of the auxiliary supply and the V capacitor by activating the
CC
internal start-up current source to supply the controller during start-up,
transients, latch, stand-by etc.
SOIC−7
With a supply range up to 35 V, the controller hosts a jittered 65 or
100-kHz switching circuitry operated in peak current mode control.
When the power on the secondary side starts to decrease, the controller
automatically folds back its switching frequency down to minimum
level of 26 kHz. As the power further goes down, the part enters skip
cycle while limiting the peak current that insures excellent efficiency
in light load condition.
NCP1239 features a timer-based fault detection circuitry that
ensures a quasi-flat overload detection, independent of the input
voltage.
CASE 751U
PIN CONNECTIONS
1
2
3
4
8
HV
Fault
FB
6
5
VCC
DRV
CS
GND
Features
• Fixed-Frequency 65-kHz or 100-kHz Current-Mode Control
Operation
• Frequency Foldback Down to 26 kHz and Skip Mode to
Maximize Performance in Light Load Conditions
• Adjustable Over Power Protection (OPP) Circuit
MARKING DIAGRAM
8
• High-Voltage Current Source with Brown-Out (BO) Detection
• Internal Slope Compensation
1239xfff
ALYWX
G
• Internal Fixed Soft-Start
• Frequency Jittering in Normal and Frequency Foldback Modes
1
• 64-ms Timer-Based Short-Circuit Protection with Auto-Recovery
or Latched Operation
1239xfff = Specific Device Code
• Pre-Short Ready for Latched OCP Versions
x = A, B, C, D, E, F, G, H or I
fff = 065 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
• Latched OVP on VCC – Autorecovery for C and E Versions
• Latched OVP/OTP Input for Improved Robustness
A
L
Y
W
G
• 35-V V Operation
CC
•
500 mA Peak Source/Sink Drive Capability
= Pb−Free Package
• Internal Thermal Shutdown
• Extremely Low No-Load Standby Power
ORDERING INFORMATION
• Pin-to-Pin Compatible with the Existing NCP1236/1247 Series
• These Devices are Pb-Free and are RoHS Compliant
See detailed ordering and shipping information on page 25 of
this data sheet.
Typical Applications
• AC-DC Converters for TVs, Set-Top Boxes and Printers
• Offline Adapters for Notebooks and Netbooks
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number
September, 2016 − Rev. 12
NCP1239/D
NCP1239
Vbulk
Vout
.
.
OVP
NCP1239
8
1
2
3
4
6
5
OPP
adjsut.
NTC
Figure 1. Application Schematic (OPP Adjustment)
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
Fault
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A
precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a latch.
2
3
FB
CS
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current but also offers an overpower compensation adjustment. When the
CS pin is brought above 1.2 V, the part is permanently latched off.
4
5
6
GND
DRV
VCC
The controller ground.
The driver’s output to an external MOSFET gate.
This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and offers a
means to latch the converter in fault conditions.
7
8
NC
HV
Non-connected for improved creepage distance.
Connected to the bulk capacitor or rectified ac line, this pin powers the internal current source to deliver a start-
up current. It is also used to provide the brown-out detection and the HV sensing for the Overpower protection.
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2
NCP1239
Table 2. DEVICE OPTION AND DESIGNATIONS
OCP
Soft−
start
OCP
V
cc
OVP
V
cc
OVP
Fault pin
BO
BO
Protection
Timer
64 ms
64 ms
Threshold
Protection
Protection
Levels
Timer
Timer
Device
Frequency
NCP1239AD65R2G
NCP1239BD65R2G
65 kHz
Latch
25.5 V
Latch
Latch
Latch
110 / 101 68 ms
110 / 101 68 ms
8 ms
8 ms
65 kHz
Auto−
25.5 V
Latch
Recovery
NCP1239CD65R2G
NCP1239DD65R2G
NCP1239ED65R2G
65 kHz
65 kHz
65 kHz
Auto−
Recovery
64 ms
64 ms
64 ms
25.5 V
25.5 V
25.5 V
Auto−
Recovery
Latch
Latch
110 / 101 68 ms
101 / 95 68 ms
110 / 101 68 ms
8 ms
8 ms
8 ms
Auto−
Recovery
Latch
Auto−
Recovery
Auto−
Recovery
Auto−
Recovery
NCP1239FD65R2G
NCP1239HD65R2G
NCP1239ID65R2G
NCP1239AD100R2G
NCP1239BD100R2G
65 kHz
65 kHz
65 kHz
100 kHz
100 kHz
Latch
Latch
Latch
Latch
64 ms
64 ms
128 ms
64 ms
64 ms
32 V
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
229 / 176 68 ms
229 / 224 68 ms
101 / 95 68 ms
110 / 101 68 ms
110 / 101 68 ms
4 ms
8 ms
4 ms
8 ms
8 ms
25.5 V
25.5 V
25.5 V
25.5 V
Auto−
Recovery
NCP1239ED100R2G
NCP1239GD100R2G
100 kHz
100 kHz
Auto−
Recovery
64 ms
64 ms
25.5 V
25.5 V
Auto−
Recovery
Auto−
Recovery
110 / 101 68 ms
95 / 86 136 ms
8 ms
8 ms
Latch
Latch
Latch
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3
NCP1239
NC
VFault(OVP)
600−ns time
constant
Vdd
Clock
IOTP
OVP/OTP
gone?
HV sample
BO
Up counter
Fault
HV detection
& sampling
HV
RST
4
BO end
Vfault(clamp)
BO
Dual HV startup
current source
VFault(OTP)
TSD
Option for
OVP_VCC
TSD
Vcc(reset)
Vcc logic
management
S
Latch
Vdd
Q
UVLO
Q
Vcc(reset)
BO end
OVP_VCC
Vcc
R
Vdd
Skip
Jitter
20us time
constant
TSD end
Rup
VCC(OVP)
Vskip
Stop
Oscillator
Clock
Foldback
FB
65 kHz / 100 kHz
/ 4
Slope
Compensation
+
Clamp
S
Drv
Q
PWM
Q
Soft−start
Ramp
HV sample
R
8 ms
Soft−start
GND
BO
SS end
OPP Current
Generation
Latch
TSD
Overcurrent
S
OCP_flag
Iopp
Q
Q
VLimit1
Skip
Vdd
LEB
300 ns
R
Ibias
PWM
OVP_VCC
(option)
LEB
Up counter
CS
Protection
Mode
120 ns
4
RST
Reset
VLimit2
Auto−recovery
OCP Fault
gone?
OCP_flag
Dmax
Timer
UVLO
OCP
Timer
1 s
64 ms
Vcc(reset)
Figure 2. Simplified Block Diagram
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4
NCP1239
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 35
−0.3 to 5.5
−0.3 to 20
−0.3 to 650
250
Unit
V
Power Supply Voltage, V Pin, Continuous Voltage
V
CC
CC
Maximum Voltage on Low Power Pins CS, FB and Fault
Maximum Voltage on DRV Pin
V
V
DRV
V
High Voltage Pin
HV
V
Thermal Resistance Junction-to-Air
R
°C/W
θ
J−A
Single Layer PCB 25 mm@, 2 Oz Cu Printed Circuit Copper Clad
Maximum Junction Temperature
T
150
°C
°C
J(max)
Storage Temperature Range
TSTG
−60 to 150
ESD Capability (Note 2)
Human Body Model – All Pins Except HV
Machine Model
ESD
ESD
4
200
kV
V
HBM
MM
Charged-Device Model ESD Capability per JEDEC JESD22−C101E
Moisture Sensitivity Level
1
1
kV
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC JESD22−A114F
ESD Machine Model tested per JEDEC JESD22−A115C
Charged-Device Model ESD Capability tested per JEDEC JESD22−C101E
Latch-up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max Values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
START-UP SECTION
Minimum Voltage for Current Source Operation
I
= 90% I
,
V
−
25
60
V
HV
START2
HV(min)
V
V
V
V
= V
− 0.5 V
CC
CC
CC
HV
CC(on)
Current Flowing Out of V Pin
= 0 V
= V
I
I
0.2
1.5
−
0.5
3
0.8
4.5
20
mA
mA
mA
CC
START1
Current Flowing Out of V Pin
– 0.5 V
CC
CC(on)
START2
HV Pin Leakage Current
= 325 V
I
8
LEAK1
SUPPLY SECTION
Start-Up Threshold
V
CC
Increasing
V
CC(on)
11.0
12.0
13.0
V
HV Current Source Stop Threshold
HV Current Source Restart Threshold
Minimum Operating Voltage
Operating Hysteresis
V
V
V
Decreasing
Decreasing
V
9.0
8.0
3.0
0.7
6.5
−
10.0
8.8
−
11.0
9.4
−
V
V
CC
CC(min)
V
CC
CC(off)
= V
V
V
CC(on)
CC(off)
CC(hys)
V
CC
V
CC
Level for I
to I
Transition
V
CC(inhibit)
1.2
7
1.7
7.5
2.2
V
START1
START2
Level where Logic Functions are Reset
V
V
Decreasing
V
V
CC
CC(reset)
Internal IC Consumption
Internal IC Consumption
Internal IC Consumption
= 3.2 V, F
L
= 65 kHz
= 65 kHz
= 100 kHz
ICC1
1.4
mA
FB
SW
SW
SW
and C = 0
V
FB
= 3.2 V, F
L
ICC2
ICC1
−
−
2.1
1.7
3.0
2.5
mA
mA
and C = 1 nF
V
FB
= 3.2 V, F
and C = 0
L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
BIAS
OPP
HV
BIAS
OPC
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5
NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values T = 25°C, for min/max Values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION
Internal IC Consumption
V
= 3.2 V, F
L
= 100 kHz
SW
ICC2
−
−
3.1
4.0
−
mA
FB
and C = 1 nF
Internal IC Consumption in Skip Cycle
V
CC
= 12 V, V = 0.775 V
ICC(stb)
500
mA
FB
Driving 8 A/650 V MOSFET
Internal IC Consumption in Fault Mode
Internal IC Consumption before Start-Up
Internal IC Consumption before Start-Up
DRIVE OUTPUT
Fault or Latch
ICC3
ICC4
ICC5
−
−
−
400
310
20
−
−
−
mA
mA
mA
V
V
< V < V
CC(on)
CC(min)
CC
< V
CC
CC(min)
Rise Time (10−90%)
V
V
from 10 to 90%
t
−
−
40
30
−
−
ns
ns
DRV
CC
R
= V
+ 0.2 V,
CC(off)
C = 1 nF
L
Fall Time (90−10%)
V
V
from 90 to 10%
t
F
DRV
CC
= V
+ 0.2 V,
CC(off)
C = 1 nF
L
Source Resistance
Sink Resistance
R
−
−
−
6
6
−
−
−
W
W
OH
R
OL
SOURCE
Peak Source Current
DRV High State,
I
500
mA
V
V
= 0 V (Note 1)
DRV
= V
+ 0.2 V,
CC
CC(off)
C = 1 nF
L
Peak Sink Current
High State Voltage
DRV Low State,
I
−
500
−
mA
SINK
V
V
= V (Note 1)
DRV
CC
= V
+ 0.2 V,
CC
CC(off)
C = 1 nF
L
V
CC
= 9 V, R
= 33 kW
V
8.8
−
−
V
V
DRV
DRV(low)
(Low V Level)
DRV High State
CC
High State Voltage
V
CC
= V
– 0.2 V,
V
DRV(clamp)
11.0
13.5
16.0
CC(OVP)
(High V Level)
DRV High State and Unloaded
CC
CURRENT COMPARATOR
Input Pull-Up Current
V
CS
= 0.7 V
I
−
1
−
mA
BIAS
Maximum Internal Current Setpoint
T from −40°C to +125°C
V
LIMIT1
0.752
0.800
0.848
V
J
(No OPP)
Abnormal Over-Current Fault Threshold
T = +25°C (No OPP)
V
1.10
−
1.20
475
1.30
−
V
J
LIMIT2
Default Internal Voltage Set Point for
Frequency Foldback Trip Point
~59% of V
V
mV
LIMIT
FOLD(CS)
Internal Peak Current Setpoint Freeze
~31% of V
V
−
−
250
50
−
mV
ns
LIMIT
FREEZE(CS)
Propagation Delay from V
Gate Off-State
Detection to
DRV Output Unloaded
t
100
LIMIT
DEL
Leading Edge Blanking Duration
t
t
−
−
300
120
−
−
ns
ns
LEB1
Abnormal Over-Current Fault Blanking
LEB2
Duration for V
LIMIT3
Number of Clock Cycles before Fault
Confirmation
t
−
4
−
COUNT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
BIAS
OPP
HV
BIAS
OPC
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6
NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values T = 25°C, for min/max Values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
CURRENT COMPARATOR
Internal Soft-Start Duration
Activated upon startup or
auto−recovery
t
SS
ms
A, B, C, D, E, G, H versions
F and I versions
−
−
8
4
−
−
INTERNAL OSCILLATOR
Oscillation Frequency
(65-kHz Version)
f
f
60
92
65
70
kHz
kHz
OSC
Oscillation Frequency
(100-kHz Version)
100
108
OSC
Maximum Duty-Cycle
Frequency Jittering
D
76
−
80
5
84
−
%
%
MAX
In Percentage of f
Kept even in Foldback Mode
– Jitter is
f
OSC
JITTER
Swing Frequency
f
−
240
−
Hz
SWING
FEEDBACK SECTION
Equivalent AC Resistor from FB to GND
Internal Pull-Up Voltage on FB Pin
(Note 1)
FB open
R
−
4.1
−
25
4.3
4
−
−
−
−
kW
EQ
V
FB(ref)
V
V
FB
to Current Setpoint Division Ratio
K
FB
FREEZE
Feedback Voltage below which the Peak
Current is Frozen
V
−
1.0
V
FREQUENCY FOLDBACK
Frequency Foldback Level on FB Pin
≈ 59% of Maximum Peak
V
−
1.90
26
−
V
FOLD
Current
Transition Frequency below which Skip-Cycle
Occurs
V
FB
= V
+ 0.5 V
f
TRANS
22
30
kHz
SKIP
End of Frequency Foldback Feedback Level
Skip-Cycle Level Voltage on FB Pin
Hysteresis on the Skip Comparator
INTERNAL RAMP COMPENSATION
Compensation Ramp Slope
f
= f
V
V
−
−
−
1.50
0.80
30
−
−
−
V
V
SW
MIN
FOLD(end)
V
SKIP
SKIP(hyst)
(Note 1)
mV
F
F
= 65 kHz, R = 30 kW
S
65
−
−
−29
−45
−
−
mV/ms
SW
SW
UP
S
100
= 100 kHz, R = 30 kW
UP
OVERPOWER COMPENSATION (OPP)
V
to I
Conversion Ratio
K
OPP
−
0.54
−
mA/V
mA
HV
OPP
Current Flowing Out of CS Pin
(Note 2)
V
HV
V
HV
V
HV
V
HV
= 125 V
= 162 V
= 328 V
= 365 V
I
I
I
I
−
−
−
0
20
110
130
−
−
−
OPP(125)
OPP(162)
OPP(328)
OPP(365)
105
150
Percentage of Applied OPP Current
Percentage of Applied OPP Current
Clamped OPP Current
V
FB
V
FB
V
HV
< V
> V
I
I
I
−
−
0
−
−
%
%
FOLD
FOLD
OPP1
OPP2
OPP3
+ 0.7 V (V
)
100
130
32
OPP
> 365 V
105
−
150
−
mA
ms
Watchdog Timer for DC Operation
BROWN-OUT (BO)
t
WD(OPP)
Brown-Out Thresholds (A, B, C & E versions)
Brown-Out Thresholds (A, B, C & E versions)
V
V
Increasing
Decreasing
V
V
100
93
110
101
120
109
V
V
HV
BO(on)
HV
BO(off)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
BIAS
OPP
HV
BIAS
OPC
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7
NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values T = 25°C, for min/max Values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
BROWN-OUT (BO)
Brown-Out Thresholds (D and I versions)
Brown-Out Thresholds (D and I versions)
Brown-Out Thresholds (F version only)
Brown-Out Thresholds (F version only)
Brown-Out Thresholds (G version only)
Brown-Out Thresholds (G version only)
Brown-Out Thresholds (H version only)
Brown-Out Thresholds (H version only)
V
Increasing
Decreasing
Increasing
Decreasing
Increasing
Decreasing
Increasing
Decreasing
Decreasing
V
V
V
V
V
V
V
V
92
87
101
95
110
103
247
188
104
93
V
V
HV
HV
HV
HV
HV
HV
HV
HV
HV
BO(on)
BO(off)
BO(on)
BO(off)
BO(on)
BO(off)
BO(on)
BO(off)
V
V
V
V
V
V
V
V
211
164
86
229
176
95
V
V
V
79
86
V
221
208
54
229
224
68
247
240
82
V
V
Brown-Out Timer Duration
t
ms
BO
(A, B, C, D, E, F, H and I versions)
Brown-Out Timer Duration (G version only)
FAULT INPUT (OTP/OVP)
V
HV
Decreasing
t
110
136
162
ms
BO
Over-Voltage Protection Threshold
Over-Temperature Protection Threshold
NTC Biasing Current
V
V
V
V
Increasing
Decreasing
= 0 V
V
V
2.8
0.37
39
3.0
0.40
45
3.2
0.43
51
V
V
FAULT
FAULT
FAULT
FAULT
FAULT(OVP)
FAULT(OTP)
I
mA
mA
OTP
Additional NTC Biasing Current during
Soft-Start Only
= 0 V − During
I
38
44
50
OTP_boost
Soft-Start Only
Latch Clamping Voltage
I
I
= 0 mA
= 1 mA
V
V
1.1
2.2
−
1.35
2.7
1
1.6
3.2
−
V
V
FAULT
FAULT
FAULT(clamp)0
Latch Clamping Voltage
FAULT(clamp)1
Blanking Time after Drive Turn Off
t
ms
LATCH(blank)
Number of Clock Cycles before Latch
Confirmation
t
−
4
−
LATCH(count)
OVER-CURRENT PROTECTION (OCP)
Internal OCP Timer Duration
A, B, C, D, E, F, G and H
versions
t
t
51
64
77
ms
OCP
Internal OCP Timer Duration
Auto-Recovery Timer
I version only
102
128
1
154
ms
s
OCP
t
0.85
1.35
AUTOREC
V
CC
OVER-VOLTAGE (V OVP)
CC
Latched Over Voltage Protection on V Pin
A, B, C, D, E, G and H versions
F version only
V
24.0
30.0
−
25.5
32.0
20
27.0
34.0
−
V
V
CC
CC(OVP)
V
CC(OVP)
Latched Over Voltage Protection on V Pin
CC
Delay before OVP on V Confirmation
t
ms
CC
OVP(delay)
THERMAL SHUTDOWN (TSD)
Temperature Shutdown
T Increasing (Note 1)
T
135
−
150
20
165
−
°C
°C
J
SHDN
Temperature Shutdown Hysteresis
T Decreasing (Note 1)
J
T
SHDN(hys)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
BIAS
OPP
HV
BIAS
OPC
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8
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
13.0
12.5
12.0
11.5
11.0
11.0
10.5
10.0
9.5
9.0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(min) vs. Junction Temperature
1.7
9.2
8.8
1.5
1.3
1.1
8.4
0.9
0.7
8.0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 5. VCC(off) vs. Junction Temperature
Figure 6. VCC(inhibit) vs. Junction Temperature
4.0
3.6
3.2
2.8
2.4
3.0
2.6
2.2
1.8
1.4
2.0
1.6
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 7. ICC2 (65-kHz Version) vs. Junction
Temperature
Figure 8. ICC2 (100-kHz Version) vs. Junction
Temperature
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9
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
0.8
0.7
4.5
4.0
3.5
3.0
2.5
0.6
0.5
0.4
0.3
0.2
2.0
1.5
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 9. ISTART1 vs. Junction Temperature
Figure 10. ISTART2 vs. Junction Temperature
0.84
24
20
16
12
8
0.82
0.80
0.78
0.76
4
0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 11. ILEAK1 vs. Junction Temperature
Figure 12. VLIMIT1 vs. Junction Temperature
40
35
30
25
20
1.30
1.25
1.20
1.15
1.10
15
10
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 13. VLIMIT2 vs. Junction Temperature
Figure 14. tDEL vs. Junction Temperature
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10
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
380
340
120
100
300
260
220
180
140
80
60
40
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 15. tLEB1 vs. Junction Temperature
Figure 16. tLEB2 vs. Junction Temperature
70
10
9
68
66
8
64
62
60
7
6
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 18. fOSC (65-kHz Version) vs. Junction
Temperature
Figure 17. tSS vs. Junction Temperature
84
108
104
100
96
82
80
78
76
92
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 19. fOSC (100-kHz Version) vs. Junction
Temperature
Figure 20. DMAX vs. Junction Temperature
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11
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
26
25
24
150
140
130
120
23
22
21
110
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 21. REQ vs. Junction Temperature
Figure 22. IOOP3 vs. Junction Temperature
109
120
116
112
108
105
101
97
104
100
93
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 23. VBO(on) vs. Junction Temperature
Figure 24. VBO(off) vs. Junction Temperature
82
78
74
3.2
3.1
3.0
70
66
62
58
54
2.9
2.8
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 25. tBO vs. Junction Temperature
Figure 26. VFAULT(OVP) vs. Junction Temperature
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12
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
0.43
0.42
0.41
0.40
0.39
0.38
0.37
51
49
47
45
43
41
39
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 27. VFAULT(OTP) vs. Junction Temperature
Figure 28. IOTP vs. Junction Temperature
1.3
73
69
1.2
1.1
1.0
65
61
57
0.9
0.8
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 29. tOCP vs. Junction Temperature
Figure 30. tAUTOREC vs. Junction Temperature
27.0
26.5
26.0
25.5
25.0
24.5
24.0
−40
−20
0
20
40
60
80
100 120
Temperature (5C)
Figure 31. VCC(OVP) vs. Junction Temperature
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13
NCP1239
DEFINITION
General
this domain, the controller observes the feedback pin and
The NCP1239 implements a standard current mode
when it reaches a level of 1.9 V, the oscillator starts to reduce
its switching frequency as the feedback level continues to
decrease. When the feedback level reaches 1.5 V, the
frequency hits its lower stop at 26 kHz. When the feedback
pin goes further down and reaches 1.0 V, the peak current
setpoint is internally frozen. Below this point, if the power
continues to drop, the controller enters classical skip-cycle
mode at a 31% frozen peak current.
architecture where the switch-off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part-count and cost effectiveness are
the key parameters, particularly in low-cost ac-dc adapters,
open-frame power supplies etc. The NCP1239 packs all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non-dissipative over power protection (OPP),
a brown-out protection or HV start-up current source.
Internal Soft-Start
A soft-start precludes the main power switch from being
stressed upon start-up. In this controller, the soft-start is
internally fixed to 8 ms. Soft-start is activated when a new
start-up sequence occurs or during an auto-recovery hiccup.
Current-Mode Operation with Internal Ramp
Compensation
Implementing peak current mode control operating at a 65
or 100-kHz switching frequency, the NCP1239 offers
a fixed internal compensation ramp that can easily by
summed up to the sensed current. The controller can be used
in CCM applications with wide input voltage range thanks
to its fixed ramp compensation that prevents the appearance
of sub-harmonic oscillations
Fault Input
The NCP1239 includes a dedicated fault input accessible
via its fault pin (pin 1). It can be used to sense an
over-voltage condition on the adapter. The circuit can be
latched off by pulling the pin above the upper fault threshold,
V , typically 3.0 V. The controller is also disabled
FAULT(OVP)
Internal Brown-Out Protection
if the fault pin voltage, V , is pulled below the lower
FAULT
A portion of the bulk voltage is internally sensed via the
high-voltage pin monitoring (pin 8). When the voltage on
this pin is too low, the part stops pulsing. No re-start attempt
is made until the controller senses that the voltage is back
within its normal range. When the brown-out comparator
senses the voltage is acceptable, de-latch occurs and the
fault threshold, V
threshold is normally used for detecting an over-temperature
fault (by the means of an NTC).
, typically 0.4 V. The lower
FAULT(OTP)
OVP Protection on VCC
It is sometimes interesting to implement a circuit
protection by sensing the V
controller does by monitoring its V pin. When the voltage
level. This is what this
CC
controller authorizes a re-start synchronized with V
.
CC(on)
CC
Adjustable Overpower Compensation
on this pin exceeds V
threshold, the pulses are
cc(ovp)
The high input voltage sensed on the HV pin is converted
into a current. This current builds an offset superimposed on
the current sense voltage which is proportional to the input
voltage. By choosing the resistance value in series with the
CS pin, the amount of compensation can be adjusted to the
application.
immediately stopped and the part enters in an endless hiccup
or auto-recovery mode depending on controller options.
Short-Circuit/Overload Protection
Short-circuit and especially overload protections are
difficult to implement when a strong leakage inductance
between auxiliary and power windings affects the
transformer (the aux winding level does not properly
collapse in presence of an output short). Here, every time the
internal 0.8-V maximum peak current limit is activated, an
error flag is asserted and a time period starts, thanks to the
64-ms timer. When the fault is validated, all pulses are
stopped and the controller enters an auto-recovery burst
mode, with a soft-start sequence at the beginning of each
cycle. An internal timer keeps the pulses off for 1 s typically
which, associated to the 64-ms pulsing re-try period, ensures
a duty-cycle in fault mode less than 10%, independent from
the line level. As soon as the fault disappears, the SMPS
resumes operation. Please note that some version offers an
auto-recovery mode (B, C, D and E versions) as we just
described, some do not and latch off in case of a short-circuit
(A, F, G, H and I versions).
High-Voltage Start-Up
Low standby power results cannot be obtained with the
classical resistive start-up network. In this part,
a high-voltage current-source provides the necessary
current at start-up and turns off afterwards.
EMI Jittering
An internal low-frequency modulation signal varies the
pace at which the oscillator frequency is modulated. This
helps spreading out energy in conducted noise analysis. To
improve the EMI signature at low power levels, the jittering
will not be disabled in frequency foldback mode (light load
conditions).
Frequency Foldback Capability
A continuous flow of pulses is not compatible with
no-load/light-load standby power requirements. To excel in
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14
NCP1239
HV CURRENT SOURCE PIN
The NCP1239 HV circuitry provides three features:
• Over Power Protection: HV Pin Voltage is Sensed to
Determine the Amount of OPP Current Flowing Out
the CS Pin
• Start-Up Current Source to Charge the V Capacitor
CC
at Power On
• Brown-Out Protection: when the HV Pin Voltage is
The HV pin can be connected either to the bulk capacitor
or to the input line terminals through a diode. It is further
recommended to implement one or two resistors (in the
range of 2.2 kW) to reduce the noise that can be picked-up
by the HV pin.
below V
for the 68-ms Blanking Time (136 ms
BO(off)
for G version), the NCP1239 Stops Operating and
Recovers whenthe HV Pin Voltage Exceeds V
BO(on)
START-UP SEQUENCE
The start-up time of a power supply largely depends on the
• Charge from V
to V
:
CC(inhibit)
CC(min)
time necessary to charge the V capacitor to the controller
CC
ǒ
Ǔ
VCC(min) * VCC(inhibit) @ CVCC
start-up threshold (V
NCP1239 high-voltage current-source provides the
necessary current for a prompt start-up and turns off
which is 12 V typically). The
CC(on)
(eq. 2)
(eq. 3)
tSTART2
+
ISTART2 * ICC5
• Charge from V
to V
:
CC(min)
CC(on)
afterwards. The delivered current (I
) is reduced to
START1
less than 0.5 mA when the V voltage is below V
ǒV
Ǔ @ C
CC(on) * VCC(min)
ISTART2 * ICC4
CC
CC(inhibit)
V
CC
(1.2 V typically). This feature reduces the die stress if the
pin happens to be accidentally grounded. When V
tSTART3
+
V
CC
CC
exceeds V
a 3-mA current (I
) is provided
CC(inhibit),
START2
Assuming a 22-mF V capacitor is selected and replacing
CC
and charges the V capacitor. Please note that the internal
IC consumption is increased from few mA to 310 mA (ICC4)
CC
I
, I
, ICC4, ICC5, V
and V
by
START1 START2
CC(inhibit)
CC(on)
their typical values, it comes:
when V crosses V
in order to have internal logic
CC
CC(min)
12 @ 22 u
wake-up when V reaches V
.
(eq. 4)
CC
CC(on)
tSTART1
tSTART2
tSTART3
+
+
+
+ 55 ms
500 u * 20 u
The V
charging time is then the total of the three
CC
following durations:
• Charge from 0 V to V
(
)
10 * 1.2 @ 22 u
(eq. 5)
+ 65 ms
:
CC(inhibit)
3 m * 20 u
VCC(inhibit) @ CVCC
ISTART1 * ICC5
(
12 * 10) @ 22 u
3 m * 310 u
(eq. 1)
tSTART1
+
(eq. 6)
(eq. 7)
+ 16 ms
tSTART + tSTART1 ) tSTART2 ) tSTART3 + 136 ms
V
cc(on)
V
cc(min)
V
cc(inhibit)
vcc(t)
tstart1
tstart2
tstart3
Figure 32. The VCC at Start-Up is Made of Two Segments Given the Short-Circuit Protection
Implemented on the HV Source
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15
NCP1239
If the V capacitor is first dimensioned to supply the
a key feature since it allows keeping short start-up times with
CC
controller for the traditional 5 to 50 ms until the auxiliary
large V capacitors (the total start-up sequence duration is
CC
winding takes over, no-load standby requirements usually
cause it to be larger. The HV start-up current source is then
often required to be less than 1 s).
BROWN-OUT CIRCUITRY
For the vast majority of controllers, input line sensing is
performed via a resistive network monitoring the bulk
voltage or the incoming ac signal. When in the quest of low
standby power, the external network adds a consumption
burden and deteriorates the power supply standby power
performance. Owing to its proprietary high-voltage
technology, ON Semiconductor now offers onboard line
sensing without using an external network. The system
includes a 90-MW resistive network that brings a minimum
start-up threshold and an auto-recovery brown-out
protection. Both levels are independent from the input
voltage ripple. The brown-out thresholds are fixed (see
levels in the electrical characteristics table), but they are
designed to fit most of standard ac-dc converter
applications. The simplified internal schematic appears in
Figure 33 while typical operating waveforms are drawn in
Figure 34 and Figure 35.
Vbulk
HV
Rbo_H
N
BO_OK
EMI
Filter
Rbo_L
L1
GND
VBO
Figure 33. A Simplified View of the Brown-Out Circuitry
When the HV pin voltage drops below the V
V
CC(on)
, BO signal is again sensed. If V > V
, the
BO(on)
BO(off)
HV
threshold, the brown-out protection trips: the controller
stops generating DRV pulses once the BO timer elapses.
parts restarts. If the condition is not met, no drive pulse is
delivered and internal IC consumption brings V down
CC
V
CC
is discharged to
V
CC(min)
by the controller
again. As a result, V operates in hiccup mode during a BO
CC
consumption itself. When this level is reached, the HV
current source is activated to lifts V up again. At new
event.
CC
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16
NCP1239
BO_OK = "0"
vcc(t)
è Drive pulse stops
Vcc(on)
Vcc(min)
Vcc hiccup waiting
BO signal
Vcc(off)
vDRV(t)
No pulse area
t
t
BO(t)
BO_OK = "1"
BO_OK = "1"
BO_OK = "0"
Figure 34. BO Event during Normal Operation
BO no OK
vcc(t)
First drive pulse
è No drive pulse
Vcc(on)
Vcc(min)
Vcc(off)
Vcc hiccup waiting
BO signal
BO_OK = "1"
è Wait the next Vcc(on) for
fresh start-up sequence
Vcc(inhibit)
t
t
BO(t)
BO_OK = "1"
BO_OK = "0"
Figure 35. BO Event before Start-Up
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17
NCP1239
OVER POWER PROTECTION
Over Power Protection (OPP) is a known means to limit
placed in series from the sense resistor to the CS pin will
create an offset voltage proportional to the input voltage
variation. An added current sink will ensure a zero OPP
current at low line (125 V dc), leaving the converter power
capability intact in the lowest operating voltage. Figure 36
presents the internal simplified architecture of this OPP
circuitry.
the output power runaway at high mains. Several elements
such as propagation delays and operating mode explain why
a converter operated at high line delivers more power than
at low line. NCP1239 senses the input voltage via HV pin.
This line voltage is transformed into a current information
further applied to the current sense pin (CS). A resistor
HV
Vbulk
HV detection
& sampling
N
HV sample
EMI
Filter
L1
Vfb
OPP current
generation
Iopp
CS
ROPP
To CS
comparator
offset
Rsense
Figure 36. Over Power Protection is Provided via the Bulk Voltage Present on HV Pin
250 m
The HV voltage will be transformed into a current equal
to 67.5 mA when the HV pin is biased to 125 V. However,
there is an internal fixed sink of 67.5 mA. Therefore, the net
(eq. 9)
+ 192 kW
130 u
A small 100−220-pF capacitor closely connected between
the CS and GND pins will form an effective noise filter and
nicely improves the converter immunity. Now, with this
1.92-kW resistance, the low-line 20-mA offset current will
incur a 38-mV drop, which, in relationship to a 800-mV
maximum peak, generates a small 5% reduction. Assuming
current flowing into R
is 0 at this low-voltage input
OPP
(≤ 125 V dc), ensuring an almost non-compensated
converter at low line: at a 115-V rms input (162 V dc), the
current from the OTA block will induce a 87.5-mA current,
turning into a 20-mA offset current flowing into R . Now,
OPP
2
assume a 260-V rms input voltage (365 V dc), the controller
will generate an offset current of:
a full DCM operation, the power would be reduced by 0.95
or 9.75% only. Please note that the OPP current is clamped
for a HV pin voltage greater than 365 V dc. Should you lift
the pin above this voltage, there will be no increase of the
OPP current.
The offset voltage can affect the standby power
performance by reducing the peak current setpoint in
light-load conditions. For this reason, it is desirable to cancel
(eq. 8)
365 @ 0.54 u * 67.5 u + 130 mA
Assume we need to reduce the maximum peak current
setpoint by 250 mV to limit the maximum power at the
considered 260-V rms input. In that case, we will need to
generate a 250-mV offset across R . With a 130-mA
OPP
current, R
should be equal to:
OPP
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18
NCP1239
its action as soon as frequency folback occurs. A typical
through the CS pin. When feedback increases again and
reaches the frequency foldback point, as the frequency goes
up, OPP starts to build up and reaches its full value at
curve variation is shown in Figure 37. At low power, below
the frequency folback starting point, 100% of the OPP
current is internally absorbed and no offset is created
V
FOLD
+ 0.7 V.
vFB(t)
max
Fsw
Fsw
decreases
increases
+ 0.7 V
Vfold
t
IOPP(%)
100
0
t
Figure 37. The OPP Current is Applied when the Feedback Voltage Exceeds the Folback Point. It is 0 below it
FAULT INPUT
The NCP1239 includes a dedicated fault input accessible
via the fault pin. Figure 38 shows the architecture of the fault
input. The controller can be latched by pulling up the pin
where V is the Zener diode Voltage.
Z
The controller can also be latched off if the fault pin
voltage, V , is pulled below the lower fault threshold,
FAULT
above the upper fault threshold, V , typically
FAULT(OVP)
V
, typically 0.4 V. This capability is normally
FAULT(OTP)
3.0 V. An active clamp prevents the Fault pin voltage from
reaching the V if the pin is open. To reach the
used for detecting an over-temperature fault by means of an
NTC thermistor. A pull up current source I , (typically
45 mA) generates a voltage drop across the thermistor. The
resistance of the NTC thermistor decreases at higher
temperatures resulting in a lower voltage across the
thermistor. The controller detects a fault once the thermistor
FAULT(OVP)
OTP
upper threshold, the external pull-up current has to be higher
than the pull-down capability of the clamp.
VFAULT(OVP) * VFAULT(clamp)
3 V * 1.35 V
1.35 kW
(eq. 10)
+
,
RFAULT(clamp)
voltage drops below V
The circuit detects an over-temperature situation when:
.
FAULT(OTP)
i.e. approximately 1.2 mA
(eq. 12)
RNTC @ IOTP + VFAULT(OTP)
This function is typically used to detect a V or auxiliary
CC
winding over-voltage by means of a Zener diode generally
in series with a small resistor (see Figure 38).
Neglecting the resistor voltage drop, the OVP threshold is
then:
Hence, the OTP protection trips when
VFAULT(OTP)
(eq. 13)
RNTC
+
+ 8.9 kW (Typically)
IOTP
(eq. 11)
VAUX(OVP) + VZ ) VFAULT(OVP)
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19
NCP1239
The controller bias current is reduced during power up by
its steady state value once I
is enabled. Therefore, the
OTP
disabling most of the circuit blocks including I
.
.
lower fault comparator (i.e. over-temperature detection) is
FAULT(OTP)
This current source is enabled once V reaches V
ignored during soft-start. In addition, in order to speed up
this fault pin capacitor, OTP current is doubled during the
soft-start period.
CC
CC(min)
A bypass capacitor is usually connected between the Fault
and GND pins. It will take some time for V
to reach
FAULT
Vaux
Up counter
600 ns
4
Time constant
RST
S
Latch
VFault(OVP)
Vdd
1 ms
Blanking Time
Q
Q
DRV
Falling edge
OVP/OTP gone
IOTP
Fault
R
Rfault(clamp)
Vfault(clamp)
NTC
Power on
reset
VFault(OTP)
Figure 38. Fault Detection Schematic
As a matter of fact, the controller operates normally while
the fault pin voltage is maintained within the upper and
lower fault thresholds. Upper and lower fault detectors have
blanking delays to prevent noise from triggering them. Both
OVP and OTP comparator output are validated only if its
high-state duration lasts a minimum of 600 ns. Below this
value, the event is ignored. Then, a counter ensures that
OVP/OTP events occurred for 4 successive drive clock
pulses before actually latching the part.
When the part is latched-off, the drive is immediately
turned off and V goes in endless hiccup mode. The power
CC
supply needs to be un-plugged to reset the part (V
or
CC(reset)
BO event). Please note that this protection on the Fault pin
is autorecovery for the E version.
AUTO-RECOVERY SHORT-CIRCUIT PROTECTION
In case of output short-circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than the timer’s programmed value, the
driving pulses are stopped and a 1-s auto-recovery timer
pulses are missing and the controller waits that V
crossed to enable the stat-up current source. During the timer
count down, the controller purposely ignores the re-start
is
CC(min)
when V crosses V
and waits for another V cycle.
CC
CC(on)
CC
By lowering the duty cycle in fault condition, it naturally
reduces the average input power and the rms current in the
output cable. Illustration of such principle appears in
Figure 39. Please note that soft-start is activated upon
re-start attempt.
starts. If V voltage is below V
, HV current source
CC(min)
CC
is activated to build up the voltage to V
. On the
CC(on)
contrary, if V voltage is above V
, HV current
CC(min)
CC
source is not activated, V falls down as the auxiliary
CC
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20
NCP1239
vcc(t)
Overload on the
output voltage
Vcc(on)
Vcc(min)
OCP timer
Autorecovery timer
OCP timer
Autorecovery timer
Vcc(off)
t
vDRV(t)
No pulse area
t
Figure 39. An Auto-Recovery Hiccup Mode is Entered in Case a Faulty Event Longer than 64 ms
is Acknowledged by the Controller
The hiccup is operating regardless of the brown-out level.
waveform: the controller is protecting the converter against
an overload. The mains suddenly went down, and then back
again at a normal level. Right at this moment, the hiccup
logic receives a reset signal and ignores the next hiccup to
immediately initiate a re-start signal.
However, when the internal comparator toggles indicating
that the controller recovers from a brown-out situation (the
input line was ok, then too low and back again to normal),
the hiccup is interrupted and the controller re-starts to the
next available V . Figure 40 displays the resulting
CC(on)
vcc(t)
Overload on the
output voltage
Vcc(on)
Vcc(min)
OCP timer
Autorecovery timer
Vcc(off)
t
vDRV(t)
No pulse area
t
BO(t)
BO_OK = "1"
BO_OK = "1"
BO_OK = "0"
t
Figure 40. BO Event in Auto-Recovery or Latch Mode
www.onsemi.com
21
NCP1239
LATCHED SHORT CIRCUIT PROTECTION WITH PRE-SHORT
In some applications, the controller must be fully latched
temporarily raised until regulation is met. If during the time
the flag is raised an UVLO event is detected, the part latches
in case of an output short circuit presence. When the error
flag is asserted, meaning the controller is asked to deliver its
full peak current, upon timer completion, the controller
off immediately. When latched, V hiccups between the
CC
two levels, V
and V
until a reset occurs
CC(on)
CC(min)
latches off: all pulses are immediately stopped and V
(Brown-out event or V cycled down below V
). In
CC
CC
CC(reset)
hiccups between the two levels, V
and V
.
normal operation, if a UVLO event is detected for any
reason while the error flag is not asserted, the controller will
naturally resume operations. Please also note that this
pre-short protection is activated only during start-up
sequence. In normal operation, even if an UVLO event
occurs while the error flag is asserted, the controller will
enters in auto-recovery mode. Details of this behavior are
given in Figure 41.
CC(on)
CC(min)
However, in presence of a small V capacitor, it can very
CC
well be the case where the stored energy does not give
enough time to let the timer elapse before V touches the
CC
V . When this happens, the latch is not acknowledged
CC(off)
since the timer countdown has been prematurely aborted. To
avoid this problem, NCP1239 combines the error flag
assertion together with the UVLO flag: upon start up, as
maximum power is asked to increase V , the error flag is
OUT
Fb
OK
vcc(t)
reset
resumed
latched
Vcc(on)
Vcc(min)
Vcc(off)
Glitch or
overload
New sequence
vDRV(t)
t
UVLO
AND
OCP flag
at start−up
t
1
OCP flag
0
t
Figure 41. UVLO Event during Start-Up Sequence and in Normal Operation
LATCHING OR AUTO-RECOVERY MODE
The B, C, D and E versions are auto-recovery. When an
overload fault is detected, they stop generating drive pulses
has reached 10-V
level, the circuit charged up V
CC(min) CC
to V
. The controller enters in an endless hiccup mode.
CC(on)
and V hiccups between V
and V
during the
The device cannot recover operation until V drops below
CC
CC(min)
CC(on)
CC
auto-recovery timer before initiate a fresh start-up sequence
with soft-start.
The A, F, G, H and I versions latch off when they detect
an overload situation. In this condition, the circuit stops
V
or brownout recovery signal is applied.
CC(reset)
Practically, the power supply must be unplugged to be reset
(V < V ). Please note that the controller always
enters in auto-recovery mode when the UVLO event occurs
without internal error flag signal (ie: without overload).
CC
CC(reset)
generating drive pulses and let V drop down. When V
CC
CC
www.onsemi.com
22
NCP1239
FREQUENCY FOLDBACK
The reduction of no-load standby power associated with
1.5 V, the frequency is fixed and cannot go further down.
The peak current setpoint is free to follow the feedback
voltage from 3.2 V (full power) down to 1 V. At 1 V, as both
frequency and peak current are frozen (250 mV or ≈31% of
the maximum 0.8-V setpoint) the only way to further reduce
the transmitted power is to enter skip cycle. This is what
happens when the feedback voltage drops below 0.8 V
typically. Figure 42 depicts the adopted scheme for the part.
the need for improving the efficiency, requires to change the
traditional fixed-frequency type of operation. This
controller implements a switching frequency folback when
the feedback voltage passes below a certain level, V
,
FOLD
set at 1.9 V. At this point, the oscillator turns into
a Voltage-Controlled Oscillator (VCO) and reduces
switching frequency down to a feedback voltage of 1.5 V
where switching frequency is 26 kHz typically. Below
Frequency
Peak current setpoint
FSW
VCS
Vfold(end)
max
FB
65 kHz
max
0.8 V
0.47 V
[
min
min
26 kHz
0.25 V
[
skip
VFB
VFB
0.8 V 1.5 V
1.9 V
3.2 V
0.8 V
1.0 V
1.9 V
3.2 V
Vfold
Vskip
Vskip Vfreeze
Vfold
Figure 42. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an
Improved Performance at Light Load
SLOPE COMPENSATION
Slope compensation is a known means to fight
sub-harmonic oscillations in peak-current mode controlled
power converters (flyback in our case). By adding an
artificial ramp to the current sense information or
subtracting it from the feedback voltage, you implement
slope compensation. How much compensation do you need?
The simplest way is to consider the primary-side inductor
downslope and apply 50% of its value for slope
compensation. For instance, assume a 65-kHz/19-V output
flyback converter whose transformer turns ratio 1:N is
1:0.25. The primary inductor is 600 mH. As such, assuming
a 1-V forward drop of the output rectifier, the downslope is
evaluated to:
If we have a 0.33-W sense resistor, then the current
downslope turns into a voltage downslope whose value is
simply:
SȀOFF + SOFF @ RSENSE
+
(eq. 15)
+ 133 m @ 0.33 [ 44 mVńms
50% of this value is 22 mV/ms. The internal slope
compensation level is typically 29 mV/ms (for the 65-kHz
version) so it will nicely compensate this design example.
What if my converter is under compensated? You can still
add compensation ramp via a simple RC arrangement
showed in Figure 43. Please look at AND8029 available
from www.onsemi.com regarding calculation details of this
configuration.
VOUT ) Vf
19 ) 1
(eq. 14)
SOFF
+
+
+
NLp
0.25 @ 600 u
+ 133 kAńs or 133 mAńms
www.onsemi.com
23
NCP1239
DRV
D1
1N4148
R1
C1
R4
R3
CS
Rsense
Figure 43. An Easy Means to Add Slope Compensation is by Using an Extra RC Network Building a Ramp
from the Drive Signal
ND
A 2 OVER-CURRENT COMPARATOR FOR ABNORMAL OVER-CURRENT FAULT DETECTION
A severe fault like a winding short-circuit can cause the
switch current to increase very rapidly during the on-time.
threshold of the comparator, V
, typically 1.2 V, is set
ILIM2
50 % higher than V
, to avoid interference with normal
LIMIT1
The current sense signal significantly exceeds V
. But,
operation. Four consecutive abnormal over-current faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Over-Current Comparator.
Please note that like timer-based short-circuit protection,
A, F, G, H and I versions are latching off compared to B, C,
D and E versions that are auto-recovery.
ILIM1
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can become huge causing system damage.
The NCP1239 protects against this fault by adding an
additional comparator for abnormal over-current fault
detection. The current sense signal is blanked with a shorter
LEB duration, t
, typically 120 ns, before applying it to
LEB2
the abnormal over-current fault comparator. The voltage
OVER-VOLTAGE PROTECTION ON V PIN
CC
The NCP1239 hosts a dedicated comparator on the V
auto-recovery or latched. For latching-off versions, the part
CC
pin. When the voltage on this pin exceeds 25.5 V typically
(32.0 V for F versions) for more than 20 ms, a signal is sent
to the internal latch and the controller immediately stops the
driving pulses while remaining in a lockout state. Depending
can be reset by cycling down its V , for instance by pulling
CC
off the power plug but also if a brown-out recovery is sensed
by the controller. This technique offers a simple and cheap
means to protect the converter against optocoupler.
controller options, this OVP on V
pin can be
CC
PROTECTING FROM A FAILURE OF THE CURRENT SENSING
A 1-mA (typically) pull-up current source, I , pulls up the
voltage is low or if the CS pin is grounded. In this case, the
CS
CS pin to disable the controller if the pin is left open.
OCP timer is activated. If the timer elapses, the controller
enters in auto-recovery or endless hiccup mode depending
on the controller option. This unexpected operation can lead
to deep CCM with destructive consequences.
In addition the maximum duty ratio limit (80% typically)
avoids that the MOSFET stays permanently on if the switch
current cannot reach the setpoint when for instance, the input
www.onsemi.com
24
NCP1239
SOFT-START
Soft-start is achieved by ramping up an internal reference,
, and comparing it to current sense signal. V
gradual increase of the power switch current during start-up.
The soft-start duration (that is, the time necessary for the
V
SSTART
SSTART
ramps up from 0 V once the controller powers up. The
setpoint rise is then limited by the V ramp so that a
ramp to reach the V
is typically 8 ms.
steady state current limit), t
,
ILIM1
SSTART
SSTART
DRIVER
, is limit the gate voltage on the external MOSFETs. The DRV
The NCP1239 maximum supply voltage, V
CC(max)
25.5 V (32.0 V for F versions). Typical high-voltage
MOSFETs have a maximum gate-source voltage rating of
20 V. The DRV pin incorporates an active voltage clamp to
voltage clamp, V is typically 13.5 V with a
maximum limit of 16 V.
DRV(high)
THERMAL SHUTDOWN
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
temperature drops below below T
by the thermal
SHDN
shutdown hysteresis, T
, typically 20_C.
SHDN(HYS)
The thermal shutdown is also cleared if V drops below
CC
threshold, T
, typically 150_C. A continuous V
V
or a brown-out fault is detected. A new power up
SHDN
CC
CC(reset)
hiccup is initiated after a thermal shutdown fault is detected.
sequences commences at the next V
once all the faults
CC(on)
The controller restarts at the next V
once the IC
are removed.
CC(on)
Table 5. ORDERING INFORMATION
OCP
Protection
V
OVP
Fault Pin
Protection
BO
Levels
CC
†
Protection
Device
Marking
Freq.
Package Shipping
NCP1239AD65R2G
NCP1239BD65R2G
NCP1239CD65R2G
NCP1239DD65R2G
NCP1239ED65R2G
NCP1239FD65R2G
NCP1239HD65R2G
NCP1239ID65R2G
1239A065 65 kHz
1239B065 65 kHz
1239C065 65 kHz
1239D065 65 kHz
1239E065 65 kHz
Latch
Latch
Latch
Latch
Latch
Latch
110/101
110/101
110/101
101/95
Auto-Recovery
Latch
Auto-Recovery Auto-Recovery
Auto-Recovery Latch
Auto-Recovery Auto-Recovery Auto-Recovery 110/101
2500 /
SOIC−7
1239F065
1239H065 65 kHz
1239I065 65 kHz
65 kHz
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
229/176
229/224
101/95
Tape &
(Pb-Free)
Reel
NCP1239AD100R2G 1239A100 100 kHz
110/101
110/101
NCP1239BD100R2G 1239B100 100 kHz Auto-Recovery
NCP1239ED100R2G 1239E100 100 kHz Auto-Recovery Auto-Recovery Auto-Recovery 110/101
NCP1239GD100R2G 1239G100 100 kHz Latch Latch Latch 95/86
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
25
NCP1239
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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