NCN4555MNG [ONSEMI]
1.8V / 3V SIM Card Power Supply and Level Shifter; 1.8V / 3V SIM卡电源和电平转换器
| 型号： | NCN4555MNG |
| 厂家： | 
ONSEMI |
| 描述： | 1.8V / 3V SIM Card Power Supply and Level Shifter |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCN4555
1.8V / 3V SIM Card Power
Supply and Level Shifter
The NCN4555 is a level shifter analog circuit designed to translate
the voltages between a SIM Card and an external microcontroller or
MPU. A built−in LDO−type DC−DC converter makes the NCN4555
useable to drive 1.8 V and 3.0 V SIM card. The device fulfills the
ISO7816−3 smart card interface standard as well as GSM 11.11 and
related (11.12 and 11.18) and 3G mobile requirements (IMT−2000/3G
TS 31.101). With the STOP pin a low current shutdown mode can be
activated making the battery life longer. The Card power supply
http://onsemi.com
QFN−16
MN SUFFIX
CASE 488AK
voltage (SIM_V ) is selected using a single pin (MOD_V ).
CC
CC
1
Features
• Supports 1.8 V or 3.0 V Operating SIM Card
• The LDO is able to Supply More than 50 mA under 1.8 V and 3.0 V
• Built−in Pullup Resistor for I/O Pin in Both Directions
MARKING DIAGRAM
• All Pins are Fully ESD Protected According to ISO−7816
Specifications – ESD Protection on SIM Pins in Excess of 7 kV
(Human Body Model)
16
1
• Supports up to More than 5 MHz Clock
• Low−Profile 3x3 QFN−16 Package
• Pb−Free Packages are Available*
NCN
4555
ALYWG
G
Typical Applications
• SIM Card Interface Circuit for 2G, 2.5G and 3G Mobile Phones
• Identification Module
• Smart Card Readers
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Wireless PC Cards
1.8 V to 5.5 V 2.7 V to 5.5 V
0.1mF 0.1mF
(Note: Microdot may be in either location)
GND
V
5
ORDERING INFORMATION
BB
†
Device
Package
Shipping
3
1
2
3
4
5
6
7
8
V
DD
V
GND
7
CC
SIM_V
1
2
CC
NCN4555MN
NCN4555MNG
QFN−16
123 Units / Rail
123 Units / Rail
STOP
MOD_V
RST
RST
CLK
C4
I/O
C8
P3
P2
P1
P0
CC
QFN−16
(Pb−Free)
14
13
15
9
SIM_RST
SIM_CLK
SIM_I/O
11
8
CLK
I/O
DET
DET
NCN4555MNR2
QFN−16
3000/Tape & Reel
3000/Tape & Reel
1mF
NCN4555MNR2G
QFN−16
(Pb−Free)
GND
10
GND
SIM Card
Detect
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
GND
Figure 1. Typical Interface Application
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 1
NCN4555/D
NCN4555
NC I/O
RST CLK
14 13
Exposed Pad (EP)
16
15
STOP
NC
11 SIM_CLK
1
2
3
4
12
MOD_V
CC
DD
NCN4555
GND
V
10
9
NC
SIM_RST
5
6
7
8
V
NC SIM_V SIM_I/O
BAT
CC
Figure 2. QFN−16 Pinout (Top View)
V
(2.7 V to 5.5 V)
5
BAT
STOP
1
7
SIM_V
50 mA LDO
1.8 V/3.0 V
CC
MOD_V
2
3
CC
DD
GND
V
(1.8 V to 5.5 V)
RST
SIM_RST
9
14
GND
GND
CLK 13
11 SIM_CLK
GND
14 kW
18 kW
I/O
I/O
15
DATA
DATA
8
SIM_I/O
GND
I/O
GND
10
GND
Figure 3. NCN4555 Block Diagram
http://onsemi.com
2
NCN4555
PIN DESCRIPTIONS
PIN
Name
Type
Description
1
STOP
INPUT
Power Down Mode pin:
STOP = Low ³ Low current shutdown mode activated
STOP = High ³ Normal Operation
A Low level on this pin resets the SIM interface, switching off the SIM_V
.
CC
2
3
MOD_V
INPUT
The signal present on this pin programs the SIM_V value:
CC
CC
MOD_V = Low ³ SIM_V = 1.8 V
CC
CC
MOD_V = High ³ SIM_V = 3 V
CC
CC
V
POWER
This pin is connected to the system controller power supply. It configures the level shifter input
DD
stage to accept the signals coming from the microprocessor. A 0.1 mF capacitor shall be used to
bypass the power supply voltage. When V is below 1.1 V typical the SIM_V is disabled. The
DD
CC
NCN4555 comes into a shutdown mode.
4
5
NC
No Connect
V
POWER
POWER
DC−DC converter supply input. The input voltage ranges from 2.7V up to 5.5V. This pin has to be
bypass by a 0.1 mF capacitor.
BAT
6
7
NC
No Connect
SIM_V
This pin is connected to the SIM card power supply pin. An internal LDO converter is
CC
programmable by the external MPU to supply either 1.8 V or 3.0 V output voltage. An external
1.0 mF minimum ceramic capacitor recommended must be connected across SIM_V and GND.
CC
During a normal operation, the SIM_V voltage can be set to 1.8 V followed by a 3.0 V value, or
CC
can start directly to any of these two values.
8
SIM_I/O
INPUT/
OUTPUT
This pin handles the connection to the serial I/O of the card connector. A bidirectional level
translator adapts the serial I/O signal between the card and the micro controller. A 14 kW (typical)
pullup resistor provides a High impedance state for the SIM card I/O link.
9
SIM_RST
GND
OUTPUT
GROUND
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator adapts the
external Reset (RST) signal to the SIM card.
10
11
This pin is the GROUND reference for the integrated circuit and associated signals. Care must be
taken to avoid voltage spikes when the device operates in a normal operation.
SIM_CLK
This pin is connected to the CLOCK pin of the card connector. The CLOCK (CLK) signal comes
from the external clock generator, the internal level shifter being used to adapt the voltage defined
for the SIM_V
.
CC
12
13
NC
No Connect
CLK
INPUT
INPUT
The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max
values defined by the specification (typically 50%). The built−in level shifter translates the input
signal to the external SIM card CLK input.
14
15
RST
I/O
The RESET signal present at this pin is connected to the SIM card through the internal level
shifter which translates the level according to the SIM_V programmed value.
CC
INPUT/
OUTPUT
This pin is connected to an external microcontroller or cellular phone management unit. A
bidirectional level translator adapts the serial I/O signal between the smart card and the external
controller. A built−in constant 18 kW (typical) resistor provides a high impedance state when not
activated.
16
NC
No Connect
http://onsemi.com
3
NCN4555
ATTRIBUTES
Characteristics
Values
ESD protection
HBM, SIM card pins (7, 8, 9, 10 & 11) (Note 1)
HBM, All other pins (Note 1)
> 7 kV
> 2 kV
MM, SIM card pins (7, 8, 9, 10 & 11) (Note 2)
MM, All other pins (Note 2)
CDM, SIM card pins (7, 8, 9, 10 & 11) (Note 3)
CDM , All other pins (Note 3)
> 600 V
> 200 V
> 2 kV
> 600 V
Moisture sensitivity (Note 4) QFN−16
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model, R =1500 W, C = 100 pF.
2. Machine Model.
3. CDM, Charged Device Model.
4. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 5)
Rating
Symbol
Value
Unit
V
LDO Power Supply Voltage
Power Supply from Microcontroller Side
External Card Power Supply
Digital Input Pins
V
−0.5 ≤ V
≤ 6
BAT
BAT
V
−0.5 ≤ V ≤ 6
V
DD
DD
SIM_V
−0.5 ≤ SIM_V ≤ 6
V
CC
CC
V
in
−0.5 ≤ V ≤V + 0.5
in
DD
but < 6.0
5
V
mA
I
in
Digital Output Pins
V
−0.5 ≤ V ≤ V + 0.5
out
out
out
but < 6.0
10
DD
V
mA
I
SIM card Output Pins
QFN−16 Low Profile package
V
−0.5 ≤ V ≤ SIM_V + 0.5
out
out
but < 6.0
CC
V
mA
I
15 (internally limited)
out
Power Dissipation @ T = + 85°C
P
440
90
mW
°C/W
A
D
Thermal Resistance Junction−to−Air
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
R
q
JA
T
−25 to +85
−25 to +125
+125
°C
°C
°C
°C
A
T
J
T
Jmax
T
stg
−65 to + 150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = +25°C
A
http://onsemi.com
4
NCN4555
POWER SUPPLY SECTION (−25°C to +85°C)
Pin
5
Symbol
Rating
Min
Typ
Max
5.5
30
Unit
V
V
Power Supply
Operating current – I = 0 mA (Note 6)
2.7
BAT
5
I
22
mA
mA
V
VBAT
VBAT_SD
CC
5
I
Shutdown current – STOP= Low (Note 7)
Operating Voltage
3.0
5.5
12
3
V
1.8
DD
3
I
Operating Current – f
= 1 MHz (Note 8)
CLK
7.0
mA
mA
V
VDD
3
I
Shutdown Current – STOP = Low
Undervoltage Lockout
1.0
1.5
VDD_SD
3
V
DD
0.6
7
SIM_V
MOD_V = High, V
= 3.0 V, I = 50 mA
SIM_VCC
2.8
3.0
1.8
V
V
V
CC
CC
BAT
BAT
BAT
MOD_V = High, V
= 3.3 V to 5.5 V, I
= 0 mA to 50 mA
= 0 mA to 50 mA
2.8
1.7
3.2
1.9
CC
SIM_VCC
MOD_V = Low, V
= 2.7 V to 5.5 V, I
CC
SIM_VCC
7
I
Short –Circuit Current – SIM_V shorted to ground , T =25°C
175
mA
SIM_VCC_SC
CC
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. As long as V
7. As long as V
– V
– V
2.5 V. For V
2.5 V.
– V > 2.5 V the maximum value increases up to 35 mA (typical being in the +25 mA range).
BAT DD
v
v
BAT
DD
DD
BAT
8. Guaranteed by design over the operating temperature range specified.
DIGITAL INPUT/OUTPUT SECTION CLOCK, RESET, I/O, STOP, MOD_VCC
Pin
Symbol
Rating
Input Voltage Range (STOP, MOD_V , RST, CLK, I/O)
Min
Typ
Max
Unit
1,2, 13,
14, 15
V
in
0
V
DD
V
CC
I
& I
Input Current (STOP, MOD_V , RST, CLK)
−100
100
nA
IH
IL
CC
13, 14
1, 2
V
V
High Level Input Voltage (RST, CLK)
Low Level Input Voltage (RST, CLK)
0.7 * V
V
DD
V
V
IH
IL
DD
DD
DD
0.2 * V
DD
V
V
High Level Input Voltage (STOP, MOD_V
Low Level Input Voltage (STOP, MOD_V
)
CC
0.7 * V
0
V
V
V
IH
IL
DD
)
CC
0.4
15
V
V
High Level Output Voltage (SIM_I/O = SIM_V , I
Low Level Output Voltage (SIM_I/O = 0 V, I
High Level Input Current (I/O)
= −20 mA)
= 200 mA)
0.7 * V
0
V
V
V
mA
mA
OH_I/O
OL_I/O
CC OH_I/O
DD
0.4
20
1.0
OH_I/O
I
−20
IH
I
Low Level Input Current (I/O)
IL
15
R
pu_I/O
I/0 Pullup Resistor
12
18
24
kW
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
http://onsemi.com
5
NCN4555
SIM INTERFACE SECTION (Note 9)
Pin
Symbol
Rating
Min
Typ
Max
Unit
9
SIM_RST
SIM_V = +3.0 V (MOD_V = High)
CC
CC
Output RESET V
@ I
= −20 mA
= +200 mA
0.9 * SIM_V
0
SIM_V
V
V
ms
ms
OH
sim_rst
CC
CC
CC
0.4
1
1
Output RESET V @ I
OL
sim_rst
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
SIM_V = +1.8 V (MOD_V = Low)
CC
CC
0.9 * SIM_V
0
SIM_V
Output RESET V
@ I
= −20 mA
= +200 mA
CC
OH
sim_rst
V
V
ms
ms
0.4
1
1
Output RESET V @ I
OL
sim_rst
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
11
SIM_CLK
SIM_V = +3.0 V (MOD_V = High)
CC CC
Output Duty Cycle
Max Output Frequency
40
60
%
MHz
V
5
0.9 * SIM_V
0
Output V
@ I
= −20 mA
SIM_V
0.4
OH
sim_clk
CC
CC
V
Output V @ I
= +200 mA
OL
sim_clk
18
18
ns
ns
Output SIM_CLK Rise Time @ Cout = 30 pF
Output SIM_CLK Fall Time @ Cout = 30 pF
SIM_V = +1.8 V (MOD_V = Low)
CC
CC
40
60
%
MHz
V
V
ns
Output Duty Cycle
Max Output Frequency
5
0.9 * SIM_V
0
SIM_V
0.4
Output V
@ I
= −20 mA
CC
CC
CC
CC
OH
sim_clk
Output V @ I
= +200 mA
OL
sim_clk
18
18
Output SIM_CLK Rise Time @ Cout = 30 pF
Output SIM_CLK Fall Time @ Cout = 30 pF
ns
8
SIM_I/O
SIM_V = +3.0 V (MOD_V = High)
CC CC
Output V
Output V @ I
@ I
= −20 mA, V = V
0.8 * SIM_V
0
SIM_V
V
V
ms
ms
OH
OL
SIM_IO
I/O
DD
= +1 mA, V = 0 V
0.4
1
1
SIM_IO
I/O
SIM_I/O Rise Time @ C = 30 pF
out
SIM_I/O Fall Time @ C = 30 pF
out
SIM_V = +1.8 V (MOD_V = High)
CC
CC
0.8 * SIM_V
0
SIM_V
Output V
Output V @ I
@ I
= −20 mA, V =V
V
V
CC
CC
OH
OL
SIM_IO
I/O
DD
0.3
1
= +1.0 mA, V = 0 V
SIM_IO
I/O
SIM_I/O Rise Time @ C = 30 pF
ms
ms
out
1
SIM_I/O Fall Time @ C = 30 pF
out
8
R
Card I/O Pullup Resistor
10
14
18
kW
pu_SIM_I/O
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. All the dynamic specifications (AC specifications) are guaranteed by design over the operating temperature range.
http://onsemi.com
6
NCN4555
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
100
90
80
70
60
50
V
= 5.5 V
V
= 5.5 V
BAT
BAT
V
= 3.3 V
BAT
V
= 2.7 V
BAT
−50
−30
−10
10
30
50
70
90
−50
−30
−10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. Short Circuit Current IVCC_SC vs
Temperature at SIM_VCC = 1.8 V (MOD_VCC = LOW)
Figure 5. Short Circuit Current IVCC_SC vs
Temperature at SIM_VCC = 3.0 V (MOD_VCC = HIGH)
30
30
25
20
15
10
V
= 3.3 V
BAT
25
V
= 2.7 V
BAT
V
= 5.5 V
BAT
V
= 5.5 V
BAT
20
15
10
−50
−30
−10
10
30
50
70
90
−50
−30
−10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. IBAT vs temperature at 3.0 V
Figure 7. IVBAT vs Temperature at 1.8 V
http://onsemi.com
7
NCN4555
APPLICATION INFORMATION
CARD SUPPLY CONVERTER
In order to guarantee a stable and satisfying operating of
the LDO the SIM_V output will be connected to a 1.0 mF
The NCN4555 interface DC−DC converter is a
Low Dropout Voltage Regulator capable of suppling a
current in excess of 50 mA under 1.8 V or 3.0 V. This device
features a very low quiescent current typically lower than
CC
bypass ceramic capacitor to the ground. At the input, V
BAT
will be bypassed to the ground with a 0.1 mF ceramic
capacitor.
25 mA (Figure 6 and 7). MOD_V
is a select input
CC
LEVEL SHIFTERS
allowing a logic level signal to select a regulated voltage of
1.8 V (MOD_V = LOW) or 3.0 V (MOD_V = HIGH).
The level shifters accommodate the voltage difference
that might exist between the microcontroller and the smart
card. The RESET and CLOCK level shifters are
monodirectional and feature both the same architecture.
The bidirectional I/O line provides a way to automatically
adapt the voltage difference between the MCU and the SIM
card in both directions. In addition with the pullup resistor,
an active pullup circuit (Figure 8, Q1 and Q2) provides a fast
charge of the stray capacitance, yielding a rise time fully
within the ISO7816 specifications.
CC
CC
Additionally, the NCN4555 has a shutdown input allowing
it to turn off or turn on the regulator output. The shutdown
mode power consumption is typically in the range of a few
tens of nA (30 nA Typical). Figure 8 shows a simplified
view of the NCN4555 voltage regulator. The SIM_V
output is internally current limited and protected against
short circuits. The short−circuit current IV is constant
CC
CC
over the temperature and SIM_V . It varies with V
CC
BAT
typically in the range of 60 mA to 90 mA (Figure 4 and 5).
SIM_V
V
CC
BAT
I
lim
R1
Q1
−
+
C
IN
= 0.1 mF
C
OUT
= 1.0 mF
+
R2
MOD_V
CC
V
STOP
REF
GND
Figure 8. Simplified Block Diagram of the LDO Voltage Regulator
V
DD
SIM_V
CC
Q1
Q2
18 k
14 k
200 ns
200 ns
I/O
SIM_I/O
GND
Q3
GND
IO/CONTROL
LOGIC
Figure 9. Basic I/O Line Interface
http://onsemi.com
8
NCN4555
ESD PROTECTION
The NCN4555 SIM interface features an HBM ESD
voltage protection in excess of 7 kV for all the SIM pins
The typical waveform provided in Figure 10 shows how
the accelerator operates. During the first 200 ns (typical),
the slope of the rise time is solely a function of the pullup
resistor associated with the stray capacitance. During this
period, the PMOS devices are not activated since the input
(SIM_IO, SIM_CLK, SIM_RST, SIM_V and GND). All
CC
the other pins (microcontroller side) sustain at least 2 kV.
These values are guaranteed for the device in its full integrity
without considering the external capacitors added to the
circuit for a proper operating. Consequently in the operating
conditions it is able to sustain much more than 7 kV on its
SIM pins making it perfectly protected against electrostatic
discharge well over the HBM ESD voltages required by the
ISO7816 standard (4 kV).
voltage is below their V threshold. When the input slope
gs
crosses the V , the opposite one shot is activated,
gsth
providing a low impedance to charge the capacitance, thus
increasing the rise time as depicted in Figure 10. The same
mechanism applies for the opposite side of the line to make
sure the system is optimum.
INPUT SCHMITT TRIGGERS
PRINTED CIRCUIT BOARD LAYOUT
All the Logic input pins (excepted I/O and SIM_I/O, See
Figure 3) have built−in Schmitt trigger circuits to prevent
the NCN4555 against uncontrolled operation. The typical
dynamic characteristics of the related pins are depicted
Figure 11.
Careful layout routing will be applied to achieve a good
and efficient operating of the device in its mobile or portable
environment and fully exploit its performance.
The bypass capacitors have to be connected as close as
possible to the device pins (SIM_V , V
or V
) in
The output signal is guaranteed to go High when the input
CC
DD
BAT
order to reduce as much as possible parasitic behaviors
(ripple and noise). It is recommended to use
ceramic capacitors.
voltage is above 0.7 x V , and will go Low when the input
DD
voltage is below 0.2 x V or 0.4 V depending on the input
DD
considered (see the Digital Input Table on page 5).
The exposed pad of the QFN−16 package will be
connected to the ground as well as the unconnected pins
(NC). A relatively large ground plane is recommended.
Figures 12 and 13 shows an example of PCB device
implementation in an evaluation environment.
SHUTDOWN OPERATING
In order to save power or for other purpose required by the
application it is possible to put the NCN4555 in a shutdown
mode by setting Low the pin STOP. On the other hand the
device enters automatically in a shutdown mode when V
becomes lower than 1.1 V typically.
DD
OUTPUT
V
DD
ON
OFF
INPUT
0.2 x V
0.7 x V
DD
DD
or 0.4 V
Figure 10. SIM_IO Typical Rise and Fall Times with
Stray Capacitance > 30 pF
Figure 11. Typical Schmitt Trigger Characteristics
(33 pF Capacitor Connected on the Board)
http://onsemi.com
9
NCN4555
EVALUATION BOARD AND PCB GUIDELINES
2.2 k
R5
J8
SENSE_SIM_V
CC
100 nF
C1
GND
MBRA140T3
MBRA140T3
MOD_V
CC
S2
STOP
GND
S1
12
11
10
9
NC
NC
NC
NC
8
7
6
NC
NC
5
4
3
2
NC
1
GND
GND
GND
GND
GND
Figure 12. NCN4555 engineering test board schematic diagram
http://onsemi.com
10
NCN4555
EVALUATION BOARD AND PCB GUIDELINES
Top Layer
Bottom Layer
Figure 13. NCN4555 Printed Circuit Board Layout
(Engineering board)
http://onsemi.com
11
NCN4555
PACKAGE DIMENSIONS
QFN−16 3*3*0.75 MM, 0.5 P
CASE 488AK−01
ISSUE O
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
E
SPACING BETWEEN LEAD TIP AND FLAG.
MILLIMETERS
DIM MIN
MAX
0.80
0.05
A
A1
A3
b
0.70
0.00
0.20 REF
0.15
C
TOP VIEW
0.18
0.30
0.15
C
D
3.00 BSC
D2
E
1.65
3.00 BSC
1.85
E2
e
K
1.65
0.50 BSC
0.20
0.30
1.85
(A3)
0.10
0.08
C
C
−−−
0.50
A
L
SEATING
PLANE
16 X
SIDE VIEW
A1
C
D2
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
E2
16X K
12
1
16
13
16X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NCN4555/D
相关型号：
©2020 ICPDF网 联系我们和版权申明