NCN49597_技术文档

NCN49597

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Power Line Carrier Modem

ON Semiconductor’s NCN49597 is an IEC 61334−5−1 compliant

power line carrier modem using spread−FSK (S−FSK) modulation for

robust low data rate communication over power lines. NCN49597 is

built around an ARM processor core, and includes the MAC layer.

With this robust modulation technique, signals on the power lines can

pass long distances. The half−duplex operation is automatically

synchronized to the mains, and can be up to 4800 bits/sec.

The product configuration is done via its serial interface, which

allows the user to concentrate on the development of the application.

The NCN49597 is implemented in ON Semiconductor mixed signal

technology, combining both analog circuitry and digital functionality

on the same IC.

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1

52

QFN52 8x8, 0.5P

CASE 485M

Features

• Power Line Carrier Modem for 50 and 60 Hz Mains

• Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1

• Complete Handling of Protocol Layers Physical to MAC

• Programmable Carrier Frequencies in CENELEC A-Band from 9 to

95 kHz; B−Band from 95 to 125 kHz, in 10 Hz Steps

• Half Duplex

MARKING DIAGRAMS

52

1

ARM

ON

• Data Rate Selectable:

300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz)

360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz)

• Synchronization on Mains

• Repetition Algorithm Boost the Robustness of Communication

• SCI Port to Application Microcontroller

• SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb

• Power Supply 3.3 V

• Ambient Temperature Range: −40°C to +80°C

• These Devices are Pb−Free and are RoHS Compliant*

XXXXYZZ

NCN 49597

C597−901

e3

XXXX = Date Code

Y

= Plant Identifier

ZZ

= Traceability Code

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 27 of this data sheet.

Typical Applications

• ARM: Automated Remote Meter Reading

• Remote Security Control

• Streetlight Control

• Transmission of Alerts (Fire, Gas Leak, Water Leak)

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

1

Publication Order Number:

December, 2011 − Rev. P0

NCN49597/D

NCN49597

APPLICATION

Application Example

3V3_A

3V3_D

C₈

R₆

C₆

R₈

R₇

C₁₇

C₁₆

12V

3V3_D

U₁

C₉

C₇

R₁₂

12V

VCC

T_REQ

U₂

−B

Vuc

19

OutA

D₁

C₃

6

12

5

7

MAINS

R₄

C₄

TXD

RXD

Appli

&

Metering

mC

R₅

TX_OUT

4

R₁₀

−A

8

NCS5650

OutB

9

3

+A

D₂

BR0

10

11

1

13

2

20

14

15

Vcom

+B

Rlim

BR1

3V3_D

VEE

C₁₀

GNDuC

Vwarn

R₉

RESB

R₁₄

C₅

PC20111120 .1

NCN49597

C₁₁

Tr

TX_ENB

RX_OUT

R₂

C₁

1:2

C₂

R₃

D₃

VDD1V8

SEN

RX_IN

REF_OUT

ZC_IN

D₄

R₁

C_DREF

C₁₅

3V3_A

D₅

R₁₁

EXT_CLK_E

C₁₂

Y₁

C₁₃

C₁₄

Figure 1. Typical Application for the NCN49597S−FSK Modem

Figure 1 shows an S−FSK PLC modem build around

NCN49597. For synchronization the line frequency is

The filter components are tuned for a space and mark

frequency of 63.3 and 74 kHz respectively. The output of the

coupled in via a 1 MW resistor. The Schottky diode pair D

amplifier is coupled via a DC blocking capacitor C to a 2:1

5

10

clamps the voltage within the input range of the zero cross

detector. In the receive path a 2 order high pass filter

pulse transformer Tr. The secondary of this transformer is

nd

coupled to the mains via a high voltage capacitor C . High

11

blocks the mains frequency. The corner point defined by C ,

energetic transients from the mains are clamped by the

1

C , R and R is designed at 10 kHz. In the transmit path a

protection diode combination D , D together with D , D .

Because the mains is not galvanic isolated care needs to be

taken when interfacing to a microcontroller or a PC!

2

1

2

3 4 1 2

th

3

order low pass filter build around the NCS5650 power

nd

rd

operational amplifier suppresses the 2 and 3 harmonics

to be in line with the CENELEC EN 50065−1 specification.

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

C , C

Function − Remark

High pass receive filter

; V decoupling cap − ceramic

Typ Value

Tolerance

10%

Unit

nF

mF

nF

pF

mF

1.5

1

2

C , C

V

−20 +80%

20%

5

DREF

REF_OUT

C , C , C , C

17

Decoupling block capacitor

TX_OUT coupling capacitor

Low pass transmit filter

100

470

68

7

9

16

C

3

10%

4

6

8

Low pass transmit filter

10%

Low pass transmit filter

3

10%

C

TX coupling cap; 1 A rms ripple @ 70 kHz

10

20%

10

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NCN49597

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

Function − Remark

High Voltage coupling capacitor; 630 V

Zero Cross noise suppression

X−tal load capacitor

Typ Value

Tolerance

20%

−20 +80%

1%

Unit

nF

pF

mF

kW

W

C

11

C

12

220

100

C

, C

22

13

14

C

Decoupling block capacitor 1.8 V internal supply

High pass receive filter

1

15

R

22

1

2

R

High pass receive filter

11

1%

R , R , R R

12, 13

High pass receive filter; Alarm current ; Pull up

Low pass transmit filter

10

1%

3

9

R

3,3

1%

4

5

6

7

8

Low pass transmit filter

10

1%

Low pass transmit filter

8,2

1%

Low pass transmit filter

500

3

1%

Low pass transmit filter

1%

kW

W

R

TX Coupling resistor ; 0.5 W

Zero Cross coupling HiV

0,47

1%

10

11

R

1

5%

MW

D , D

High current Schottky Clamp diodes

TVS diodes

MBRA430

P6SMB6.8AT3G

BAS70−04

48 MHz

1

2

D , D

3

4

D

Double low current Schottky clamp diode

X−tal

5

Y1

Tr

2:1 Pulse transformer

U1

U2

PLC modem

NCN49597

NCS5650

Power Operational Amplifier

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Min

Max

Unit

ABSOLUTE MAXIMUM RATINGS SUPPLY

Power Supply Pins VDD, VDDA, VSS, VSSA

Absolute max. digital power supply

Absolute max. analog power supply

V

− 0.3

3.9

V

DD_ABSM

SS

V

−

DDA_ABSM

SSA

0.3

Absolute max. difference between digital and analog power supply

Absolute max. difference between digital and analog ground

ABSOLUTE MAXIMUM RATINGS NON 5V SAFE PINS

V

− V

−0.3

0.3

V

DD

DDA_ABSM

V

SS

SSA_ABSM

Non 5V Safe Pins: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, TDO, TDI, TCK, TMS, TRSTB, TEST

Absolute maximum input for normal digital inputs and analog inputs

Absolute maximum voltage at any output pin

V

SS

V

SS

− 0.3

V

DD

V

DD

+ 0.3

V

IN_ABSM

V

OUT_ABSM

ABSOLUTE MAXIMUM RATINGS 5V SAFE PINS

5V Safe Pins: TX_ENB, TXD, RXD, BR0, BR1, IO3 .. IO11, RESB

Absolute maximum input for digital 5V safe inputs

Absolute maximum voltage at 5V safe output pin

V

− 0.3

6.0

3.9

V

5VS_ABSM

SS

V

OUT5V_ABSM

SS

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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NCN49597

Normal Operating Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the

Normal Operating Conditions section and for the reliability specifications as listed in Detailed Hardware Description section.

Functionality outside these limits is not implied.

Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be

less than 0.1% of the useful life as defined in Detailed Hardware Description section.

Table 3. OPERATING RANGES

Rating

Symbol

Min

3.0

Max

3.6

80

Unit

V

Power supply voltage range

Ambient Temperature

V

DD

T

A

−25

−40

°C

Extended Ambient Temperature on special request

T

A

80

PIN DESCRIPTION

QFN Packaging

1

2

3

4

5

6

7

8

9

39

38

37

36

35

34

33

32

31

30

29

28

27

NC

TX_EN

TEST

RES

IO11

CRC

BR0

BR1

SEN

T_REQ

CSB

SDO

M50Hz_IN

NC

IO3

IO4

IO5

IO0/RX_DATA

TDO

AMIS49597

TDI

TCK

TMS

TRST

IO6

10

11

12

13

IO7

Figure 2. QFN Pin−out of NCN49597 (Top view)

Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

ZC_IN

I/O

In

Type

A

Description

1

50/60 Hz input for mains zero cross detection

General Purpose I/O

3..5, 12..15,

23, 34

IO3 .. IO11

In/Out

D, 5V Safe

6

7

RX_DATA

TDO

Out

In

D, 5V Safe

Data reception indication (open drain output)

Test data output

8

TDI

Test data input (internal pull down)

Test clock (internal pull down)

9

TCK

In

10

11

TMS

In

Test mode select (internal pull down)

Test reset bar (internal pull down, active low)

TRSTB

In

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NCN49597

Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

I/O

Type

Description

16

TXD/PRES

Out

D, 5V Safe

Output of transmitted data (TXD) or PRE_SLOT signal

(PRES)

17

18

XIN

In

A

Xtal input (can be driven by an internal clock)

XOUT

Out

Xtal output (output floating when XIN driven by external

clock)

19

20

21

22

24

25

26

27

28

29

30

31

32

33

35

36

37

42

43

46

47

48

49

51

VDD1V8

VSS

P

1V8 regulator output. Foresee a decoupling capacitor

Digital ground

P

VDD

P

3.3V digital supply

TXD

Out

In

D, 5V Safe

SCI transmit output (open drain)

SCI receive input (Schmitt trigger output)

SPI interface external Flash

RXD

D, 5V Safe

SCK

Out

In

D

SDI

D

SPI interface external Flash

SDO

Out

In

D

SPI interface external Flash

CSB

D

SPI interface external Flash

T_REQ

SEN

In

D, 5V Safe

Transmit Request input

In

D

Boot option

BR1

In

D, 5V Safe

SCI baud rate selection

BR0

In

D, 5V Safe

SCI baud rate selection

CRC

Out

In

D, 5V Safe

Correct frame CRC indication (open drain output)

Master reset bar (Schmitt trigger input, active low)

Hardware Test enable (internal pull down)

TX enable bar (open drain)

RESB

TEST

TX_ENB

TX_OUT

ALC_IN

VDDA

VSSA

RX_OUT

RX_IN

REF_OUT

NC

D, 5V Safe

In

D

Out

In

D, 5V Safe

A

P

A

Transmitter output

Automatic level control input

3.3V analog supply

Analog ground

Out

In

Output of receiver low noise operational amplifier

Positive input of receiver low noise operational amplifier

Reference output for stabilization

Out

2, 38..41, 44,

45,50, 52

Pins 2, 38..41, 44, 45, 50, 52 are not connected. These

pins need to be left open or connected to the GND plane.

P:

A:

D:

Power pin

5V Safe:

IO that support the presence of 5V on bus line

Analog pin

Digital pin

Out:

In:

Output signal

Input signal

Detailed Pin Description

VDDA

REF_OUT

VDDA is the positive analog supply pin. Nominal voltage

REF_OUT is the analog output pin which provides the

voltage reference used by the A/D converter. This pin must

be decoupled to the analog ground by a 1 mF ceramic

is 3.3 V. A ceramic decoupling capacitor C = 100 nF must

DA

be placed between this pin and the VSSA. Connection path

of this capacitance to the VSSA on the PCB should be kept

as short as possible in order to minimize the serial resistance.

capacitance C . The connection path of this capacitor to

DREF

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5

NCN49597

the VSSA on the PCB should be kept as short as possible in

order to minimize the serial resistance.

This information is used, after filtering with the internal

PLL, to synchronize frames with the mains frequency. In

case of direct connection to the mains it is advised to use a

series resistor of 1 MW in combination with two external

clamp diodes in order to limit the current flowing through

the internal protection diodes.

VSSA

VSSA is the analog ground supply pin.

VDD

VDD is the 3.3 V digital supply pin. A ceramic decoupling

RX_DATA

capacitor C = 100 nF must be placed between this pin and

DD

RX_DATA is a 5 V compliant open drain output. An

external pull−up resistor defines the logic high level as

illustrated in Figure 4. A typical value for the pull−up

resistance “R” is 10 kW. The signal on this output depends

on the status of the data reception. If NCN49597waits for

configuration RX_DATA outputs a pulse train with a 10 Hz

frequency. After Synchronization Confirm Time out

the VSS. Connection path of this capacitance to the VSS on

the PCB should be kept as short as possible in order to

minimize the serial resistance.

VSS

VSS is the digital ground supply pin.

RX_DATA

=

0. If NCN49597is searching for

synchronization RX_DATA = 1.

+5V

R

Output

V_SSD

PC20090722.2

Figure 3: Recommended Layout of the Placement of

Decoupling Capacitors

Figure 4. Representation of 5V Safe Output

TDO, TDI, TCK, TMS, and TRSTB

VDD1V8

All these pins are part of the JTAG bus interface. The

JTAG interface is used during production test of the IC and

will not be described here. Input pins (TDI, TCK, TMS, and

TRSTB) contain internal pull−down resistance. TDO is an

output. When not used, the JTAG interface pins may be left

floating.

This is an additional power supply pin to decouple an

internal LDO regulator. The decoupling capacitor should be

placed as close as possible to this output pin as illustrated in

Figure 4.

RX_OUT

RX_OUT is the output analog pin of the receiver low

noise input op−amp. This op−amp is in a negative feedback

configuration.

TXD/PRES

TXD/PRES is the output for either the transmitting data

(TX_DATA) or a synchronization signal with the time−slots

(PRE_SLOT). TXD/PRES. More information can be found

in paragraph Local Port.

RX_IN

RX_IN is the positive analog input pin of the receiver low

noise input op−amp. Together with RX_OUT and

REF_OUT, an active high pass filter is realized. This filter

removes the main frequency (50 or 60 Hz) from the received

signal. The filter characteristics are determined by external

capacitors and resistors. A typical application schematic can

be found in paragraph 50/60 Hz Suppression Filter.

XIN

XIN is the analog input pin of the oscillator. It is connected

to the interval oscillator inverter gain stage. The clock signal

can be created either internally with the external crystal and

two capacitors or by connecting an external clock signal to

XIN. For the internal generation case, the two external

capacitors and crystal are placed as shown in Figure 5. For

the external clock connection, the signal is connected to XIN

and XOUT is left unused.

ZC_IN

ZC_IN is the mains frequency analog input pin. The signal

is used to detect the zero cross of the 50 or 60 Hz sine wave.

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NCN49597

account after a reset, hardware or software. Modification of

the baud rate during function is not possible. BR0 and BR1

are 5 V safe.

CRC

XTAL_IN

XTAL_OUT

PC20111118.1

CRC is a 5 V compliant open drain output. An external

pull−up resistor defines the logic high level as illustrated in

Figure 4. A typical value for this pull−up resistance “R” is

10 kW. The signal on this output depends on the cyclic

redundancy code result of the received frame. If the cyclic

redundancy code is correct CRC = H during the pause

between two time slots.

48 MHz

C_X

V_SSA

Figure 5. Placement of the Capacitors and Crystal

with Clock Signal Generated Internally

RESB

RESB is a digital input pin. It is used to perform a

hardware reset of the NCN49597. This pin supports a 5 V

voltage level. The reset is active when the signal is low

(0 V).

The crystal is a classical parallel resonance crystal of

48 MHz. The values of the capacitors C are given by the

X

manufacturer of the crystal. A typical value is 36 pF. The

crystal has to fulfill impedance characteristics specified in

the NCN49597data sheet. As an oscillator is sensitive and

precise, it is advised to put the crystal as close as possible on

the board and to ground the case.

TEST

TEST is a digital input pin with internal pull down resistor

used to enable the Hardware Test Mode of the chip. When

TEST is left open or forced to ground Normal Mode is

enabled. When TEST is forced to VDD the Hardware Test

Mode is enabled. This mode is used during production test

of the IC and will not be described here. TEST pin is not 5 V

safe.

XOUT

XOUT is the analog output pin of the oscillator. When the

clock signal is provided from an external generator, this

output must be floating. When working with a crystal, this

pin cannot be used directly as clock output because no

additional loading is allowed on the pin (limited voltage

swing).

TX_ENB

TX_ENB is a digital output pin. It is low when the

transmitter is activated. The signal is available to turn on the

line driver. TX_ENB is a 5 V safe with open drain output,

hence a pull−up resistance is necessary achieve the

requested voltage level associated with a logical one. See

also Figure 4 for reference.

TXD

TXD is the digital output of the asynchronous serial

communication (SCI) unit. Only half−duplex transmission

is supported. It is used to realize the communication between

the NCN49597and the application microcontroller. The

TXD is an open drain IO (5 V safe). External pull−up

resistances (typically 10 kW) are necessary to generate the

5 V level. See Figure 4 for the circuit schematic.

TX_OUT

TX_OUT is the analog output pin of the transmitter. The

provided signal is the S−FSK modulated frames. A filtering

operation must be performed to reduce the second and third

order harmonic distortion. For this purpose an active filter

is suggested. See also paragraph Transmitter Output

TX_OUT.

RXD

This is the digital input of the asynchronous SCI unit.

Only half−duplex transmission is supported. This pin

supports a 5 V level. It is used to realize the communication

between the NCN49597and the application microcontroller.

RXD is a 5 V safe input.

ALC_IN

ALC_IN is the automatic level control analog input pin.

The signal is used to adjust the level of the transmitted

signal. The signal level adaptation is based on the AC

component. The DC level on the ALC_IN pin is fixed

internally to 1.65 V. Comparing the peak voltage of the AC

signal with two internal thresholds does the adaptation of the

gain. Low threshold is fixed to 0.4 V. A value under this

threshold will result in an increase of the gain. The high

threshold is fixed to 0.6 V. A value over this threshold will

result in a decrease of the gain. A serial capacitance is used

to block the DC components. The level adaptation is

performed during the transmission of the first two bits of a

new frame. Eight successive adaptations are performed. See

T_REQ

T_REQ is the transmission request input of the Serial

Communication Interface. When pulled low its initiate a

local communication from the application micro controller

to NCN49597. T_REQ is a 5 V safe input. See also

paragraph Error! Reference source not found..

BR1, BR0

BR0 and BR1 are digital input pins. They are used to select

the baud rate (bits/second) of the Serial Communication

Interface unit. The rate is defined according to Error!

Reference source not found.. The values are taken into

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NCN49597

SCK, SDI, SDO, CSB

These signals from the SPI interface to an optional

external Flash. See Reference 1.

also paragraph Amplifier with Automatic Level Control

(ALC).

ELECTRICAL CHARACTERISTICS

DC and AC Characteristics

Oscillator: Pin XIN, XOUT

In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on

the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.

Table 5. OSCILLATOR

Parameter

Crystal frequency

Test Conditions

(Note 1)

Symbol

Min

−100 ppm

40

Typ

Max

+100 ppm

60

Unit

MHz

%

f

48

CLK

Duty cycle with quartz connected

Start−up time

(Note 1)

T

50

ms

pF

startup

Load capacitance external crystal

Series resistance external crystal

(Note 1)

C

18

40

L

(Note 1)

R

20

80

50

W

S

Maximum Capacitive load on

XOUT

XIN used as clock input

CL

pF

XOUT

Low input threshold voltage

High input threshold voltage

Low output voltage

XIN used as clock input

VIL

0.3 V

V

XOUT

DD

VIH

0.7 V

DD

XOUT

XIN used as clock input,

XOUT = 2 mA

VOL

0.3

XOUT

High input voltage

XIN used as clock input

VOH

V

DD

− 0.3

V

XOUT

1. Guaranteed by design. Maximum allowed series loss resistance is 80 W

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NCN49597

Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN

Table 6. ZERO CROSS DETECTOR AND 50/60 HZ PLL

Parameter

Test Conditions

Symbol

Imp

Min

−20

−2

Typ

Max

20

Unit

mA

V

Maximum peak input current

Maximum average input current

Mains voltage (ms) range

ZC_IN

During 1 ms

Imavg

2

ZC_IN

With protection resistor at

ZC_IN

V

MAINS

90

550

Rising threshold level

Falling threshold level

Hysteresis

(Note 2)

VIR

VIF

1.9

V

ZC_IN

(Note 2)

0.9

0.4

45

ZC_IN

(Note 2)

VHY

V

ZC_IN

Lock range for 50 Hz (Note 3)

Lock range for 60 Hz (Note 3)

Lock time (Note 3)

MAINS_FREQ = 0 (50 Hz)

MAINS_FREQ = 0 (60 Hz)

MAINS_FREQ = 0 (50 Hz)

MAINS_FREQ = 0 (60 Hz)

MAINS_FREQ = 0 (50 Hz)

Flock

Tlock

55

66

15

20

0.1

Hz

s

50Hz

60Hz

50Hz

60Hz

54

Lock time (Note 3)

s

Frequency variation without going

out of lock (Note 3)

DF

Hz/s

60Hz

Frequency variation without going

out of lock (Note 3)

MAINS_FREQ = 0 (60 Hz)

DF

0.1

25

Hz/s

50Hz

Jitter of CHIP_CLK (Note 3)

2. Measured relative to VSS

Jitter

−25

ms

CHIP_CLK

3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed

by the digital test patterns.

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NCN49597

Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB

To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz 100 ppm.

Table 7. TRANSMITTER EXTERNAL PARAMETERS

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Maximum peak output level

f

= 23 – 75 kHz

TX_OUT

V

0.85

0.76

1.15

1.22

Vp

TX_OUT

f

= 95 kHz

Level control at max. output

Second order harmonic distortion

Third order harmonic distortion

f

= 95 kHz

HD2

HD3

−54

−53

30

dB

Hz

pF

kW

TX_OUT

Level control at max. output

f

= 95 kHz

TX_OUT

Level control at max. output

Frequency accuracy of the gener-

ated sine wave

(Notes 4 and 6)

Df

TX_OUT

Capacitive output load at pin

TX_OUT

(Note 4)

(Note 5)

CL

TX_OUT

20

Resistive output load at pin

TX_OUT

RL

TX_OUT

5

Turn off delay of TX_ENB output

Td

0.25

2.9

0.5

3.1

ms

dB

TX_ENB

Automatic level control attenuation

step

ALC

step

Maximum attenuation

ALC

20.3

−0.46

−0.68

111

21.7

−0.36

−0.54

189

dB

V

range

ALC_IN

Low threshold level on ALC_IN

High threshold level on ALC_IN

Input impedance of ALC_IN pin

VTL

VTH

V

R

kW

dB

Power supply rejection ration of the

transmitter section

PSRR

10

(Note 7)

35

(Note 8)

TX_OUT

4. This parameter will not be tested in production.

5. This delay corresponds to the internal transmit path delay and will be defined during design.

6. Taking into account the resolution of the DDS and an accuracy of 100ppm of the crystal.

7. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The

signal level at TX_OUT is measured to determine the parameter.

8. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The

signal level at TX_OUT is measured to determine the parameter.

The LPF filter + amplifier must have a frequency characteristic between the limits listed below. The absolute output level

depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB

reference value is measured at 50 kHz with a signal amplitude of 100 mV.

Table 8. TRANSMITTER FREQUENCY CHARACTERISTICS

Attenuation

Min

−0.5

−1.3

−4.5

Max

0.5

Frequency (kHz)

Unit

dB

10

95

0.5

130

165

330

660

1000

2000

−2.0

−3.0

−18.0

−36.0

−50

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NCN49597

Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT

Table 9. RECEIVER EXTERNAL PARAMETERS

Parameter

Input offset voltage 42 dB

Input offset voltage 0 dB

Test Conditions

Symbol

Min

Typ

Max

5

Unit

mV

Vp

AGC gain = 42 dB

AGC gain = 0 dB

V

OFFS_RX_IN

50

Max. peak input voltage (corres-

ponding to 62.5% of the SD full

scale)

AGC gain = 0 dB (Note 9)

V

0.85

1.15

MAX_RX_IN

Input referred noise of the analog

receiver path

AGC gain = 42 dB

(Notes 9 and 10)

NF

150

1

nV/ǠHz

mA

RX_IN

Input leakage current of receiver

input

I

−1

LE_RX_IN

Max. current delivered by

REF_OUT

I

−300

300

mA

Max_REF_OUT

Power supply rejection ratio of the

receiver input section

AGC gain = 42 dB (Note 11)

AGC gain = 42 dB (Note 12)

PSRR

10

35

dB

LPF_OUT

AGC gain step

AGC range

AGC

5.7

6.3

dB

V

step

AGC

39.9

1.52

44.1

1.78

range

Analog ground reference output

voltage

V

REF_OUT

Signal to noise ratio at 62.5 % of

the SD full scale

(Notes 9 and 13)

SN

54

dB

Vp

AD_OUT

Clipping level at the output of the

gain stage (RX_OUT)

V

1.15

1.65

CLIP_AGC_IN

9. Input at RX_IN, no other external components.

10.Characterization data only. Not tested in production.

11. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and

REF_OUT output is measured to determine the parameter.

12.A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is

measured to determine the parameter.

13.These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT

with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB.

The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below.

The absolute output level depends on the operating condition.

Table 10. RECEIVER FREQUENCY CHARACTERISTICS

Attenuation

Min

−0.5

−1.3

−4.5

Max

0.5

Frequency (kHz)

Unit

dB

10

95

0.5

130

165

330

660

1000

2000

−2.0

−3.0

−18.0

−36.0

−50

−55

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NCN49597

Power−on−Reset (POR)

Table 11. POWER−ON−RESET

Parameter

Test Conditions

Symbol

Min

1.7

1

Typ

Max

Unit

V

POR threshold

V

POR

2.7

Power supply rise time

0 to 3V

T

RPOR

ms

Digital Outputs: TDO, CLK_OUT

Table 12. DIGITAL OUTPUTS: TDO, CLK_OUT

Parameter

Low output voltage

High output voltage

Test Conditions

Symbol

Min

Typ

Max

Unit

V

I

= 4 mA

V

OL

0.4

XOUT

I

= −4 mA

V

OH

0.85 V

DD

V

XOUT

Digital Outputs with Open Drain: TX_ENB, TXD

Table 13. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, RX_DATA, CRC, T_REQ

Parameter

Low output voltage

Test Conditions

= 4 mA

Symbol

Min

Typ

Max

Unit

I

V

OL

0.4

V

XOUT

Digital Inputs: BR0, BR1

Table 14. DIGITAL INPUTS: BR0, BR1

Parameter

Test Conditions

Symbol

Min

Max

Unit

V

Low input level

V

IL

0.2 V

DD

High input level

0 to 3 V

V

IH

0.8 V

V

DD

Input leakage current

I

−10

10

mA

LEAK

Digital Inputs with Pull Down: TDI, TMS, TCK, TRSTB, TEST

Table 15. DIGITAL INPUTS WITH PULL DOWN: TDI, TMS, TCK, TRSTB, TEST

Parameter

Low input level

Test Conditions

Symbol

Min

Typ

Max

Unit

V

0.2 V

IL

IH

DD

High input level

V

0.8 V

7

V

DD

Pull down resistor

(Note 14)

R

50

kW

PU

14.Measured around a bias point of V /2.

DD

Digital Schmitt Trigger Inputs: RXD, RESB

Table 16. DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB

Parameter

Rising threshold level

Falling threshold level

Input leakage current

Test Conditions

Symbol

Min

Typ

Max

Unit

V

T+

0.80 V

DD

V

T−

0.2 V

V

DD

I

−10

10

mA

LEAK

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NCN49597

Current Consumption

Table 17. CURRENT CONSUMPTION

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Current consumption in receive

mode

Current through V and V

I

RX

60

80

mA

DD

DDA

(Note 15)

Current consumption in transmit

mode

Current through V and V

I

TX

60

80

4

mA

DD

(Note 15)

Current consumption when RESB

= 0

Current through V and V

I

RESET

DD

(Note 15)

15.f

= 48 MHz.

CLK

INTRODUCTION

General Description

digital. At the back−end side, the interface to the application

is done through a serial interface. The digital processing of

the signal is partitioned between hardwired blocks and a

microprocessor block. The microprocessor is controlled by

firmware. Where timing is most critical, the functions are

implemented with dedicated hardware. For the functions

where the timing is less critical, typically the higher level

functions, the circuit makes use of the ARM microprocessor

core.

The processor runs DSP algorithms and, at the same time,

handles the communication protocol. The communication

protocol, in this application, contains the MAC = Medium

Access Control Layer. The program running on the

microprocessor is stored into ROM. The working data

necessary for the processing is stored in an internal RAM. At

the back−end side the link to the application hardware is

provided by a Serial Communication Interface (SCI). The

SCI is an easy to use serial interface, which allows

communication between an external processor used for the

application software and the NCN49597 modem. The SCI

works on two wires: TXD and RXD. Baud rate is

programmed by setting 2 bits (BR0, BR1).

Because the low protocol layers are handled in the circuit,

the NCN49597 provides an innovative architectural split.

Thanks to this, the user has the benefit of a higher level

interface of the link to the PLC medium. Compared to an

interface at the physical level, the NCN49597 allows faster

development of applications. The user just needs to send the

raw data to the NCN49597 and no longer has to take care of

the protocol detail of the transmission over the specific

medium. This last part represents usually 50% of the

software development costs.

The NCN49597 is a single chip half duplex S−FSK

modem dedicated to power line carrier (PLC) data

transmission on low− or medium−voltage power lines. The

device offers complete handling of the protocol layers from

the physical up to the MAC. NCN49597 complies with the

CENELEC EMC standard EN 50065−1 and the

IEC 61334−5−1 standards. It operates from a single 3.3 V

power supply and is interfaced to the power line by an

external power driver and transformer. An internal PLL is

locked to the mains frequency and is used to synchronize the

data transmission at data rates of 300, 600, 1200, 2400 and

4800 baud for a 50 Hz mains frequency, or 360, 720, 1440,

2880 and 5760 baud for a 60 Hz mains frequency. In both

cases this corresponds to 3, 6, 12 or 24 data bits per half cycle

of the mains period.

S−FSK is a modulation and demodulation technique that

combines some of the advantages of a classical spread

spectrum system (e.g. immunity against narrow band

interferers) with the advantages of the classical FSK system

(low complexity). The transmitter assigns the space

frequency f^Sto “data 0” and the mark frequency fM to

“data 1”. The difference between S−FSK and the classical

FSK lies in the fact that f^Sand fM are now placed far from

each other, making their transmission quality independent

from each other (the strengths of the small interferences and

the signal attenuation are both independent at the two

frequencies). The frequency pairs supported by the

NCN49597 are in the range of 9 − 150 kHz with a typical

separation of 10 kHz.

The conditioning and conversion of the signal is

performed at the analog front−end of the circuit. The further

processing of the signal and the handling of the protocol is

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NCN49597

CLIENT

Application

SERVER

Application

SERVER

Application

SPY

Application

TEST

Application

NCN49597in

MASTER mode

NCN49597 in

SLAVE mode

NCN49597in

SLAVE mode

NCN49597in

MONITOR mode

NCN49597in

TEST mode

Major User Type

Minor User Type

PC201111 12.2

Figure 6. Application Examples

NCN49597 is intended to connect equipment using

Distribution Line Carrier (DLC) communication. It serves

two major and two minor types of applications:

• Major types:

• Minor type:

♦ Spy or Monitor:

Spy or Monitor mode is used to only listen to the

data that comes across the power line. Only the

physical layer frame correctness is checked. When

the frame is correct, it is passed to the external

processor.

♦ Master or Client:

A Master is a client to the data served by one or

many slaves on the power line. It collects data from

and controls the slave devices. A typical application

is a concentrator system

♦ Test Mode:

The Software Test Mode is used to test the

compliance of a PLC modem conforms to

CENELEC. EN 50065−1 by a continuous broadcast

♦ Slave or Server:

A Slave is a server of the data to the Master. A

typical application is an electricity meter equipped

with a PLC modem.

of f or f .

S

M

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NCN49597

Functional Description

The block diagram below represents the main functional units of the NCN49597:

VDD1V8

Transmitter (S−FSK Modulator)

Communication Controller

TX_ENB

TxD

RxD

T_REQ

BR0

LP

Filter

Transmit Data

& Sine Synthesizer

Serial

Comm.

Interface

D/A

TX_OUT

ALC_IN

TO Power Amplifier

FROM Line Coupler

TO Application

Micro Controller

BR1

5

IO[9:3]

RX_DATA

CRC

Receiver(S−FSK Demodulator)

RX_OUT

RX_IN

Local Port

ARM

Risc

Core

TX_DATA / PRE_SLOT

S−FSK

Demodulator

AAF

AGC

A/D

5

JTAG I/F

TEST

Test

Control

REF

REF_OUT

M50Hz_IN

RESB

POR

Watchdog

Timer 1 & 2

Clock and Control

5

Zero

crossing

Clock Generator

& Timer

SPI

SPI I/F

PLL

OSC

Data

RAM

Program

ROM

Interrupt

Control

NCN49597

VDDA

VSSA

VDDD VSSD

XIN XOUT

PC20111019.2

Figure 7. S−FSK Modem NCN49597 Block Diagram

Transmitter

Clock and Control

The NCN49597 Transmitter function block prepares the

communication signal which will be sent on the

transmission channel during the transmitting phase. This

block is connected to a power amplifier which injects the

output signal on the mains through a line−coupler.

According to the IEC 61334−5−1 standard, the frame data

is transmitted at the zero cross of the mains voltage. In order

to recover the information at the zero cross, a zero cross

detection of the mains is performed. A phase−locked loop

(PLL) structure is used in order to allow a more reliable

reconstruction of the synchronization. This PLL permits as

well a safer implementation of the ”repetition with credit”

function (also known as chorus transmission). The clock

generator makes use of a precise quartz oscillator master.

The clock signals are then obtained by the use of a

programmed division scheme. The support circuits are also

contained in this block. The support circuits include the

necessary blocks to supply the references voltages for the

AD and DA converters, the biasing currents and power

supply sense cells to generate the right power off and startup

conditions.

Receiver

The analog signal coming from the line−coupler is low

pass filtered in order to avoid aliasing during the conversion.

Then the level of the signal is automatically adapted by an

automatic gain control (AGC) block. This operation

maximizes the dynamic range of the incoming signal. The

signal is then converted to its digital representation using

sigma delta modulation. From then on, the processing of the

data is done in a digital way. By using dedicated hardware,

a direct quadrature demodulation is performed. The signal

demodulated in the base band is then low pass filtered to

reduce the noise and reject the image spectrum.

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NCN49597

t

48 bit @ 2400 baud

PC20100609.1

20 ms

Figure 8. Data Stream is in Sync with Zero Cross of the Mains (example for 50 Hz)

Communication Controller

Local Port

The Communication Controller block includes the

micro−processor, its peripherals: RAM, ROM, UART,

TIMER, and the Power on reset. The processor uses the

ARM Reduced Instruction Set Computer (RISC)

architecture optimized for IO handling. For most of the

instructions, the machine is able to perform one instruction

per clock cycle. The microcontroller contains the necessary

hardware to implement interrupt mechanisms, timers and is

able to perform byte multiplication over one instruction

cycle. The microcontroller is programmed to handle the

physical layer (chip synchronization), and the MAC layer

conform to IEC 61334−5−1. The program is stored in a

masked ROM. The RAM contains the necessary space to

store the working data. The back−end interface is done

through the Serial Communication Interface block. This

back−end is used for data transmission with the application

micro controller (containing the application layer for

concentrator, power meter, or other functions) and for the

definition of the modem configuration.

The controller uses 3 output ports to inform about the

actual status of the PLC communication. RX_DATA

indicates if Receiving is in progress, or if NCN49597 is

waiting for synchronization, or of it configures. CRC

indicates if the received frames are valid (CRC = OK).

TXD/PRES is the output for either the transmitting data

(TX_DATA) or a synchronization signal with the time−slots

(PRE_SLOT).

Serial Communication Interface

The local communication is a half duplex asynchronous

serial link using a receiving input (RxD) and a transmitting

output (TxD). The input port T_REQ is used to manage the

local communication with the application micro controller

and the baud rate can be selected depending on the status of

two inputs BR0, BR1. These two inputs are taken in account

after an NCN49597 reset. Thus when the application micro

controller wants to change the baud rate, it has to set the two

inputs and then provoke a reset.

DETAILED HARDWARE DESCRIPTION

Clock and Control

block is the clock signal CHIP_CLK, 8 times over sampled

with the bit rate. The oscillator makes use of precise 48 MHz

quartz. This clock signal together with CHIP_CLK is fed

into the Clock Generator and time block. Here several

internal clock signals and timings are obtained by the use of

a programmed division scheme.

According to the IEC 61334−5−1 standard, the frame data

is transmitted at the zero cross of the mains voltage. In order

to recover the information at the zero cross, a zero cross

detection of the mains is performed. A phase−locked loop

(PLL) structure is used in order to allow a more reliable

reconstruction of the synchronization. The output of this

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NCN49597

Clock and Control

CHIP_CLK

Zero

crossing

Clock Generator

& Timer

PLL

OSC

ZC_IN

XIN

XOUT

PC20090619.4

Figure 9. Clock and Control Block

Zero Cross Detector

case of direct connection to the mains it is advised to use a

series resistor of 1 MW in combination with two external

Schottky clamp diodes in order to limit the current flowing

through the internal protection diodes.

ZC_IN is the mains frequency analog input pin. The signal

is used to detect the zero cross of the 50 or 60 Hz sine wave.

This information is used, after filtering with the internal

PLL, to synchronize frames with the mains frequency. In

Clock & Control

3V3_A

BAS70−04

FROM

MAINS

ZC_IN

1 MW

ZeroCross

CHIP_CLK

Debounce

PLL

Filter

100 pF

PC20100608.1

Figure 10. Zero Cross Detector with Falling Edge De−bounce Filter

The zero cross detector output is logic zero when the input

is lower than the falling threshold level and a logic one when

the input is higher than the rising threshold level. The falling

edges of the output of the zero cross detector are de−bounced

by a period between 0.5 ms and 1 ms. The Rising edges are

not de−bounced.

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NCN49597

V_MAINS

VIR_{ZC_IN}

VIF_{ZC_IN}

t

ZeroCross

t_ZCD

t_DEBOUNCE= 0,5 .. 1 ms

10 ms

PC20090620.1

Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz)

50/60 Hz PLL

crossings. The PLL locks on the zero cross from negative to

positive phase. The bit rate is always an even multiple of the

mains frequency, so following combinations are possible:

The output of the zero cross detector is used as an input for

a PLL. The PLL generates the clock CHIP_CLK which is 8

times the bit rate and which is in phase with the rising edge

Table 18. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY

BAUD[1:0]

MAINS_FREQ

Baudrate

300

CHIP_CLK

2400 Hz

4800 Hz

9600 Hz

19200 Hz

2880 Hz

5760 Hz

11520 Hz

23040 Hz

00

01

10

11

00

01

10

11

600

50 Hz

1200

2400

360

720

60 Hz

1440

2880

In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.

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NCN49597

V_MAINS

VIR_{ZC _IN}

t

6 bit @ 300 baud

ZeroCross

t_ZCD

PLL in lock

CHIP _CLK

Start of Physical PreFrame (*)

10 ms

PC20090 619 .3

*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = t

to compensate for the zero cross delay.

ZCD

Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)

The phase difference between the zero cross of the mains

and CHIP_CLK can be tuned. This opens the possibility to

a number value stored in register R_ZC_ADJUST[7:0]. The

adjustment period or granularity is 26 ms. The maximum

adjustment is 255 x 26 ms = 6.6 ms which corresponds with

1/3rd of the 50 Hz mains sine period.

compensate for external delay t

(e.g. opto coupler) and

ZCD

for the 1.9 V positive threshold VIR

of the zero cross

ZC_IN

detector. This is done by pre−loading the PLL counter with

Table 19. ZERO CROSS DELAY COMPENSATION

R_ZC_ADJUST[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

…

Compensation

0 ms

26 ms

52 ms

78 ms

…

1111 1101

1111 1110

1111 1111

6589 ms

6615 ms

6641 ms

Oscillator

The oscillator works with a standard parallel resonance

crystal of 48 MHz. XIN is the input to the oscillator inverter

gain stage and XOUT is the output.

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NCN49597

The oscillator output f

= 48 MHz is the base frequency

CLK

for the complete IC. The clock frequency for the ARM f

ARM

= f

The clock for the transmitter, f

is equal to

CLK.

TX_CLK

f

/ 4 or 12 MHz. All the transmitter internal clock signals

CLK

will be derived from f

. The clock for the receiver,

XTAL_IN

XTAL_OUT

TX_CLK

PC20111118.1

f

is equal to f

/ 8 or 6 MHz. All the receiver

RX_CLK

CLK

internal clock signals will be derived from f

RX_CLK.

48 MHz

Clock Generator and Timer

C_X

The CHIP_CLK and f

are used to generate a number

CLK

of timing signals used for the synchronization and interrupt

generation. The timing generation has a fixed repetition rate

which corresponds to the length of a physical subframe. (see

paragraph Error! Reference source not found.)

V_SSA

Figure 13. Placement of the Capacitors and Crystal

with Clock Signal Generated Internally

The timing generator is the same for transmit and receive

mode. When NCN49597 switches from receive to transmit

and back from transmit to receive, the R_CHIP_CNT

counter value is maintained. As a result all timing signals for

receive and transmit have the same relative timing. The

following timing signals are defined as:

For correct functionality the external circuit illustrated in

Figure 13 must be connected to the oscillator pins. For a

crystal requiring a parallel capacitance of 18 pF C must be

X

around 36 pF. (Values of capacitors are indicative only and

are given by the crystal manufacturer). To guarantee startup

the series loss resistance of the crystal must be smaller than

60 W.

Start of the physical subframe

2871 2872

2879

0

1

2

3

4

5

6

7

8

9

63

64

65

R_CHIP_CNT

CHIP_CLK

BIT_CLK

BYTE_CLK

FRAME_CLK

PRE_BYTE_CLK

PRE_FRAME_CLK

PRE_SLOT

PC20090619.1

Figure 14. Timing Signals

CHIP_CLK: is the output of the PLL and 8 times the bit rate

on the physical interface. See also paragraph 50/60 Hz PLL.

BYTE_CLK: is active at counter values 0, 64, 128, .. 2816

and inactive at all other counter values. This signal is used

to indicate the transmission of a new byte.

BIT_CLK: is active at counter values 0, 8, 16, .. 2872 and

inactive at all other counter values. This signal is used to

indicate the transmission of a new bit.

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NCN49597

FRAME_CLK: is active at counter values 0 and inactive at

all other counter values. This signal is used to indicate the

transmission or reception of a new frame.

R_CONF_TXD_PRES_SEL) and can be used by the external

host controller to synchronize its software with the

FRAME_CLK of NCN49597.

PRE_BYTE_CLK is a signal which is 8 CHIP_CLK

sooner than BYTE_CLK. This signal is used as an interrupt

for the internal microcontroller and indicates that a new byte

for transmission must be generated.

Transmitter Path Description (S−FSK Modulator)

For the generation of the space and mark frequencies, the

direct digital synthesis (DDS) of the sine wave signals is

performed under the control of the microprocessor. After a

signal conditioning step, a digital to analog conversion is

performed. As for the receive path, a sigma delta modulation

technique is used. In the analog domain, the signal is low

pass filtered, in order to remove the high frequency

quantization noise, and passed to the automatic level

controller (ALC) block, where the level of the transmitted

signal can be adjusted. The determination of the signal level

is done through the sense circuitry.

PRE_FRAME_CLK is a signal which is 8 CHIP_CLK

sooner than FRAME_CLK. This signal is used as an

interrupt for the internal microcontroller and indicates that

a new frame will start at the next FRAME_CLK.

PRE_SLOT is logic 1 between the rising edge of

PRE_FRAME_CLK and the rising edge of FRAME_CLK.

This signal can be provided at the digital output pin

TXD/PRES when R_CONF[7] = 0 (See paragraph Local

Port and Error! Reference source not found., field

Transmitter(S−FSK Modulato)r

TX_EN

ALC

control

ARM

Interface

&

ALC_IN

Control

LP

Filter

Transmit Data

& Sine Synthesizer

TX_OUT

D/A

f_MIf_MQ

f_SI

f_SQ

TO RECEIVER

PC20091019.1

Figure 15. Transmitter Block Diagram

Sine Wave Generator

ARM Interface and Control

The interface with the ARM consists in a 8−bit data

registers R_TX_DATA, 2 control registers R_TX_CTRL

and R_ALC_CTRL, a flag TX_RXB defining transmit and

receive and 2 16−bit wide frequency step registers R_FM

A sine wave is generated with a direct digital synthesizer

DDS. The synthesizer generates in transmission mode a sine

wave either for the space frequency (f , data 0) or for the

S

mark frequency (f , data1). In reception the synthesizer

M

and R_FS defining f (mark frequency = data 1) and f

generates the sine and cosine waves for the mixing process,

M

S

(space frequency = data 0). All these registers are memory

mapped. Some of them are for internal use only and cannot

be accessed by the user.

f , f , f , f

quadrature). The space and mark frequencies are defined in

an individual step 16 bit wide register.

(space and mark signals in phase and

SI SQ MI MQ

Processing of the physical frame (preamble, MAC

address, CRC) is done by the ARM.

Table 20. FS AND FM STEP REGISTERS

ARM Register

R_FS[15:0]

Hard Reset

0000h

Soft Reset

0000h

Description

Step register for the space frequency f

S

R_FM[15:0]

0000h

Step register for the mark frequency f

M

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NCN49597

The space and mark frequency can be calculated as:

When NCN49597 goes into receive mode (when

TX_RXB goes from 1 to 0) the sine wave generator must

make sure to complete the active sine period.

The control logic for the transmitter generates a signal

TX_ENB to enable the external power amplifier. TX_ENB

is 1 when the NCN49597 is in receive mode. TX_ENB is 0

when NCN49597is in transmit mode. When going from

transmit to receive mode (TX_RXB goes from 1 to 0) the

18

• f = R_FS[15:0]_dec x f

/2

S

DDS

18

• f = R_FM[15:0]_dec x f

/2

DDS

M

Or the content of both R_FS[15:0] and R_FM[15:0] are

defined as:

18

• R_FS[15:0]_dec = Round(2 x f /f

)

S

DDS

18

• R_FM[15:0]_dec = Round(2 x f /f

)

M

DDS

♦ Where f

= 3 MHz is the direct digital

TX_ENB signal is kept active for a short period of t

.

DDS

dTX_ENB

synthesizer clock frequency.

The control logic for the transmitter generates a signal

After a hard or soft reset or at the start of the transmission

(when TX_RXB goes from 0 to 1) the phase accumulator

must start at it’s 0 phase position, corresponding with a 0 V

output level. When switching between f and f the phase

accumulator must give a continuous phase and not restart

from phase 0

TX_DATA which corresponds to the transmitted S−FSK

signal. When transmitting f TX_DATA is logic 1. When

M

transmitting f TX_DATA is logic 0. When the transmitter

S

is not enabled (TX_RXB = 0) TX_DATA goes to logic 1 at

the next BIT_CLK.

M

S

BIT_CLK

TX_DATA

TX_RXB

TX_ENB

TX_OUT

PC20090610.1

t_{dTX_ENB}

Figure 16. TX_ENB Timing

DA Converter

detection is used to control the setting of the level of

TX_OUT. The level of TX_OUT can be attenuated in 8 steps

of 3 dB typical.

After hard or soft reset the level is set at minimum level

(maximum attenuation) When going to reception mode

(when TX_RXB goes from 1 to 0) the level is kept in

memory so that the next transmit frame starts with the old

level. The evaluation of the level is done during 1

CHIP_CLK period.

A digital to analog SD converter converts the sine wave

digital word to a pulse density modulated (PDM) signal. The

PDM signal is converted to an analog signal with a first order

switched capacitor filter.

Low Pass Filter

rd

A 3 order continuous time low pass filter in the transmit

path filters the quantization noise and noise generated by the

ΣΔ DA converter. The typical corner frequency f

kHz and is internally trimmed to compensate for process

variation. This filter can be tuned to f

described in reference [1].

= 138

−3dB

Depending on the value of peak level on ALC_IN the

attenuation is updated:

= 1508 kHz as

−3dB

• Vp

< VTL

: increase the level with one 6 dB

ALC

ALC_IN

step

• VTL

level

Amplifier with Automatic Level Control (ALC)

≤ Vp

≤ VTH : don’t change the

ALC

ALC_IN

The pin ALC_IN is used for level control of the

transmitter output level. First peak detection is done. The

peak value is compared to two thresholds levels:

• Vp

> VTH : decrease the level with one 6 dB

ALC

ALC_IN

step

VTL

and VTH

. The result of the peak

ALC_IN

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22

NCN49597

The gain changes in the next CHIP_CLK period.

The automatic level control can be disabled by setting

register R_ALC_CTRL[3] = 1. In this case the transmitter

output level is fixed to the programmed level in the register

R_ALC_CTRL[2:0]. See Reference 1.

An evaluation phase and a level adjustment take 2

CHIP_CLK periods. ALC operation is enabled only during

the first 16 CHIP_CLK cycles after a hard or soft reset or

after going into transmit mode.

Table 21. FIXED TRANSMITTER OUTPUT ATTENUATION

ALC_CTRL[2:0]

Attenuation

0 dB

000

001

−3 dB

010

−6 dB

011

−9 dB

100

−12 dB

−15 dB

−18 dB

−21 dB

101

110

111

Remark:

Transmitter Output TX_OUT

external circuitry working with another ground. To suppress

The transmitter output is DC coupled to the TX_OUT pin.

Because the complete analog part of NCN49597 is

referenced to the analogue ground REF_OUT, a decoupling

the second and third order harmonic of the generated S−FSK

nd

th

signal it is recommended to use a 2 or 4 order low pass

nd

filter. In Figure 17 a MFB topology of a 2 order filter is

capacitor C is needed when connecting NCN49597 to

illustrated.

1

Transmitter (S−FSK Modulator )

ALC_IN

C₄

ALC

control

FROM LINE

DRIVER

R₃

ARM

Interface

C₃

C₁

R₂

R₁

C₂

&

TX_OUT

TX_EN

LP

Filter

Control

TO TX POWER

OUTPUT STAGE

V_SSA

R₄

PC20091216.1

Figure 17. TX_OUT Filter

Receiver Path Description

Receiver Block Diagram

pass active filter to attenuate the mains frequency. This high

pass filter output is followed by a gain stage which is used

in an automatic gain control loop. This block also performs

a single ended input to differential output conversion. This

gain stage is followed by a continuous time low pass filter

The receiver takes in the analog signal from the line

coupler, conditions it and demodulates it in a data−stream to

the communication controller. The operation mode and the

baud rate are made according to the setting in R_CONF,

R_FS and R_FM. The receive signal is applied first to a high

pass filter. Therefore NCN49597 has a low noise operational

amplifier at the input stage which can be used to make a high

th

to limit the bandwidth. A 4 order sigma delta converter

converts the analog signal to digital samples. A quadrature

demodulation for f and f is than performed by an internal

S

M

DSP, as well the handling of the bits and the frames.

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23

NCN49597

RX_OUT

RX_IN

Receiver(Analog Path)

FROM

LOW NOISE

OPAMP

DIGITAL

4th

TO

order

SDAD

Gain

LPF

DIGITAL

REF_OUT

REF

1,65 V

PC20090610.2

Figure 18. Analog Path of the Receiver

FROM TRANSMITTER

Receiver (Digital Path)

Quadrature Demodulator

f_MQf_SIf_SQ

f_MI

f_MQ

f_SI

2^nd

Decimator

I_M

FROM

ANALOG

Sliding

Filter

f_M

Noise

Shaper

1^st

Compen−

sator

2^nd

Decimator

Q_M

Decimator

Sliding

Filter

2^nd

I_S

Sliding

Filter

TO

GAIN

Abs

value

accu

Decimator

f_S

AGC

Control

f_SQ

2^nd

Decimator

Q_S

Sliding

Filter

PC20110610.3

Figure 19. Digital Path of the Receiver ADC and Quadrature Demodulation

50/60 Hz Suppression Filter

noise operational amplifier. REF_OUT is the analog output

pin which provides the voltage reference (1.65 V) used by

the A/D converter. This pin must be decoupled from the

NCN49597 receiver input provides a low noise input

operational amplifier in a follower configuration which can

be used to make a 50/60 Hz suppression filter with a

minimum number of external components. Pin RX_IN is the

positive input and RX_OUT is the output of the input low

analog ground by a 1 mF ceramic capacitance (C

). It is

DREF

not allowed to load this pin.

R₂

RX_OUT

RX_IN

2

Receiver (S−FSK Demodulator)

LOW NOISE

OPAMP

C₂

C₁

V_IN

3

Received

Signal

TO AGC

R₁

REF_OUT

4

REF

1,65 V

C_DREF

PC20090722.1

V_SSA

Figure 20. External Component Connection for 50/60 Hz Suppression Filter

RX_IN is the positive analog input pin of the receiver low

noise input op−amp. Together with the output RX_OUT an

active high pass filter is realized. This filter removes the

main frequency (50 or 60 Hz) from the received signal. The

filter characteristics are determined by external capacitors

and resistors. Typical values are given in Table 27. For these

values and after this filter, a typical attenuation of 85 dB at

50 Hz is obtained. Figure 21 represents external

components connection. In a typical application the

coupling transformer in combination with a parallel

capacitance forms a high pass filter with a typical

attenuation of 60 dB. The combined effect of the two filters

http://onsemi.com

24

NCN49597

decreases the voltage level of 230 Vrms at the mains

frequency well below the sensitivity of the NCN49597.

T

20

−20

−60

−100

−140

10

100

1k

10k

100k

Frequency (Hz)

Figure 21. Transfer Function of 50 Hz Suppression Circuit

Table 22. VALUE OF THE RESISTORS AND CAPACITORS

Component

Value

1.5

1

Unit

nF

C

1

2

nF

C

mF

DREF

R

22

kW

1

2

11

Remark: The analog part of NCN49597 is referenced to the

internal analog ground REF_OUT = 1.65 V (typical value).

If the external circuitry works with a different analogue

reference level one must be sure to place a decoupling

capacitor.

NCN49597works in half duplex mode. The typical corner

frequency f = 138 kHz and is internally trimmed to

compensate for process variation.

−3dB

A/D Converter

The output of the low pass filter is input for an analog 4

th

order sigma−delta converter. The DAC reference levels are

supplied from the reference block. The digital output of the

converter is fed into a noise shaping circuit blocking the

quantization noise from the band of interest, followed by a

decimation and a compensation step.

Auto Gain Control (AGC)

The receiver path has a gain stage which is used for

automatic gain control. The gain can be changed in 8 steps

of 6 dB. The control of the AGC is done by a digital circuit

which measures the signal level after the AD converter, and

regulates the average signal in a window around a

percentage of the full scale. The AGC works in 2 cycles: a

measurement cycle at the rising edge of the CHIP_CLK and

an update cycle starting at the next CHIP_CLK.

Quadrature Demodulator

The quadrature demodulation block takes the AD signal

and mixes it with the in−phase and quadrature phase of the

f and f carrier frequencies. After a low pass filter and

S

M

rectification the mixer output signals are further processed

in software. There the accumulation over a period of

CHIP_CLK is done which results in the discrimination of

data 0 and data 1.

Low Noise Anti Aliasing Filter

The receiver has a 3 order continuous time low pass filter

in the signal path. This filter is in fact the same block as in

the transmit path which can be shared because

rd

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25

NCN49597

Bit Sync

cross detector and loop delay in the Rx−filter circuitry will

cause a shift between the physical transmitted bit and the

received S−FSK signal as illustrated in Figure 23.

At the transmit side the data−stream is in sync and in phase

with the zero crossing of the mains. The complex impedance

of the power line together with propagation delay in the zero

Mains

t

Transmitted

bit stream

Bit 0

Bit1

Bit 2 Bit 3 Bit 4

Bit 5

Bit 6 Bit 7 Bit 8

Modulation

Transmission over the Power Line

PC20101119 .1

Bit delay

Figure 22. Bit Delay Cause by Transmission Over a Power Line

To compensate for this delay between physical and

Communication Controller

demodulated bit a synchro bit value is introduced. It shifts

forward the Hardware Demodulating process up to 7 chip

clocks. See Figure 24.

The Communication Controller block includes the ARM

CORTEX M0 32 bit RISC processor, its peripherals: Data

RAM, Program ROM, TIMERS 1 and 2, Interrupt Control,

TEST−Control, Watchdog and Power On Reset (POR), I/O

ports and the Serial Communication Interface (SCI). The

micro−processor is programmed to handle the physical layer

(chip synchronization), and the MAC layer conform to

IEC 61334−5−1. The program is stored in a masked ROM.

The RAM contains the necessary space to store the working

data. The back−end interface is done through the Local Port

and Serial Communication Interface block. This back−end

is used for data transmission with the application micro

controller (containing the application layer for concentrator,

power meter, or other functions) and for the definition of the

modem configuration.

SBV[2:0] = 0

SBV[2:0] = 3

CHIP_CLK

Bit 0

Bit1

Bit 2

PC20101119 .2

Figure 23. Compensation for Bit Delay by Shifting

Forward the Start of the Demodulating Process

The synchro bit value can be set using register SBV [2:0].

More details can be found in Reference 1.

Table 23. SYNCHRO BIT VALUE

SBV[2:0]

000

Bit Delay

0 CHIP_CLK

1 CHIP_CLK

2 CHIP_CLK

3 CHIP_CLK

4 CHIP_CLK

5 CHIP_CLK

6 CHIP_CLK

7 CHIP_CLK

001

010

011

100

101

110

111

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26

NCN49597

TX _ENB

Communication Controller

TxD

RxD

T_REQ

BR 0

Data

RAM

Serial

Comm.

Interface

Program

ROM

BR 1

ARM

Risc

Core

RX _DATA

CRC

TXD /PRES

Local Port

Timer 1 & 2

TO

TRANSMIT

POR

RESB

FROM

RECEIVER

Watchdog

Test

Control

Interrupt

Control

TEST

PC20091111.1

Figure 24. Communication Controller

REFERENCE

In this document references are made to:

1. Design Manual NCN49597

4. DLMS UA 1000−2 Ed. 7.0 DLMS/COSEM

Architecture and Protocols

http://www.onsemi.com

http://www.dlms.com/documentation/dlmsuacolou

redbookspasswordprotectedarea/index.html

5. IEC 61334−5−1 Lower layer S−FSK Profile.

http://webstore.iec.ch/preview/info_iec61334−5−1

%7Bed2.0%7Db.pdf

6. IEC 61334−5−1 Lower layer S−FSK Profile.

http://webstore.iec.ch/preview/info_iec61334−5−1

%7Bed2.0%7Db.pdf

2. EN 50065−1: Signaling on low−voltage electrical

installations in the frequency range 3 kHz to

148.5 kHz

http://connect.nen.nl/~/Preview.aspx?artfile=4257

28&RNR=66840

3. [3] ERDF−CPT−Linky−SPEC−FONC−CPL

version V1.0 Linky PLC profile functional

specification

http://www.erdfdistribution.fr/medias/Linky/ERD

F−CPT−Linky−SPEC−FONC−CPL.pdf

Table 24. ORDERING INFORMATION

†

Device

Temperature Range

Package

Shipping

NCN49597C5972G

−25°C – 80°C

QFN−52

(Pb−Free)

Tube

NCN49597C5972RG

−25°C – 80°C

QFN−52

(Pb−Free)

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

http://onsemi.com

27

NCN49597

PACKAGE DIMENSIONS

QFN52 8x8, 0.5P

CASE 485M−01

ISSUE C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30

MM FROM TERMINAL.

D

A

B

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

MILLIMETERS

DIM MIN

MAX

1.00

0.05

0.80

A

A1

A2

A3

b

0.80

0.00

0.60

E

0.20 REF

0.18

0.30

6.80

2X

D

8.00 BSC

0.15

C

D2

E

6.50

8.00 BSC

2X

E2

e

6.80

0.50 BSC

0.15

C

K

0.20

0.30

---

L

0.50

A2

0.10

0.08

C

A

RECOMMENDED

SOLDERING FOOTPRINT

A3 REF

26

A1

SEATING PLANE

8.30

C

52X

0.62

D2

6.75

14

27

13

L

52 X

E2

8.30

6.75

39

1

52

40

52X

0.30

PKG

OUTLINE

K

52 X

b

NOTE 3

52 X

0.50

PITCH

e

0.10 C A

0.05

B

DIMENSIONS: MILLIMETERS

C

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCN49597/D

http://onsemi.com

28


型号：	NCN49597
厂家：	ONSEMI
描述：	Power Line Carrier Modem 电力线载波调制解调器调制解调器
文件：	总28页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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