NCD57001FDWR2G [ONSEMI]
Isolated High Current IGBT Gate Driver;
| 型号： | NCD57001FDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | Isolated High Current IGBT Gate Driver 栅 双极性晶体管 |
| 文件： | 总12页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Isolated High Current IGBT
Gate Driver
1
NCD57001F
SOIC−16 WB
CASE 751G−03
NCD57001F is a variant of NCD57001 with reduced
Soft−Turn−Off time suited to drive large IGBTs or power modules.
NCD57001F is a high−current single channel IGBT driver with
internal galvanic isolation, designed for high system efficiency and
reliability in high power applications. Its features include
complementary inputs, open drain FAULT and Ready outputs, active
Miller clamp, accurate UVLOs, DESAT protection, and soft turn−off
at DESAT. NCD57001F accommodates both 5 V and 3.3 V signals on
the input side and wide bias voltage range on the driver side including
negative voltage capability. NCD57001F provides >5 kVrms
MARKING DIAGRAM
XXXXXXXXX
AWLYYWWG
(UL1577 rating) galvanic isolation and >1200 V
(working
iorm
XXXXXXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
voltage) capabilities. NCD57001F is available in the wide−body
SOIC−16 package with guaranteed 8 mm creepage distance between
input and output to fulfill reinforced safety insulation requirements.
= Pb−Free Package
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delays with Accurate Matching
• Active Miller Clamp to Prevent Spurious Gate Turn−on
• DESAT Protection with Programmable Delay
• Typ 550 ns Soft Turn Off during IGBT Short Circuit
• IGBT Gate Clamping during Short Circuit
• IGBT Gate Active Pull Down
PIN CONNECTIONS
VEE2A
DESAT
GND2
N/C
GND1
VDD1
RST
FLT
VDD2
OUT
RDY
IN−
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range including Negative VEE2
• 3.3 V to 5 V Input Supply Voltage
CLAMP
VEE2
IN+
GND1A
• 5000 V Galvanic Isolation (to meet UL1577 requirements)
• 1200 V Working Voltage (per VDE0884−10 requirements)
• High transient immunity
• High electromagnetic immunity
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
• Automotive Power Supplies
• HEV/EV Powertrain
• BSG Inverter
• PTC Heater
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
November, 2022 − Rev. 2
NCD57001F/D
NCD57001F
VDD1
VDD2
VDD1
UVLO2
UVLO1
VCLAMP−THR
+
−
CLAMP
IN−
IN+
VEE2
STO
VDD1
RDY
OUT
Logic
Logic
1
VDD2
IDESAT−CHG
VDD1
+
DESAT
GND2
RST
RS
−
VDD1
VDESAT−THR
2
GND1
1
VEE2
GND1A
VEE2A
Figure 1. Simplified Block Diagram
+V2
V1
VDD1
IN+
VDD2
DESAT
IN−
OUT
RDY
CLAMP
VEE2
FLT
RST
−V2
GND1
GND2
GND1
GND2
Figure 2. Simplified Application Schematics
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2
NCD57001F
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
1
I/O
Description
V
EE2A
Power
Output side negative power supply. A good quality bypassing capacitor is
required from these pins to GND2 and should be placed close to the pins for
best results. Connect it to GND2 for unipolar supply application.
V
EE2
8
DESAT
2
I/O
Input for detecting the desaturation of IGBT due to a short circuit condition.
An internal constant current source I
charging an external capacitor
−
DESAT CHG
connected to this pin allows a programmable blanking delay every ON cycle
before DESAT fault is processed, thus preventing false triggering. When the
DESAT voltage goes up and reaches V
, the output is driven low.
−
DESAT THR
Further, the FLT output is activated, please refer to Figure 5.
A 5 ms mute time apply to IN+ and IN− once DESAT occurs.
Output side gate drive reference connecting to IGBT emitter or FET source.
Not connected.
GND2
N/C
3
4
5
Power
−−
V
DD2
Power
Output side positive power supply. The operating range for this pin is from
UVLO2 to its maximum allowed value. A good quality bypassing capacitor is
required from this pin to GND2 and should be placed close to the pins for best
results.
OUT
6
7
O
Driver output that provides the appropriate drive voltage and source/sink current
to the IGBT/FET gate. OUT is actively pulled low during start−up and under
Fault conditions.
CLAMP
I/O
Provides clamping for the IGBT/FET gate during the off period to protect it from
parasitic turn−on. Its internal N FET is turned on when the voltage of this pin falls
below V
+ V
. It is to be tied directly to IGBT/FET gate with
−
EE2
CLAMP THR
minimum trace length for best results.
GND1
IN+
9
Power
I
Input side ground reference.
16
10
Non inverted gate driver input. It is internally clamped to V
and has
DD1
a pull−down resistor of 50 kW to ensure that output is low in the absence of an
input signal. A minimum positive going pulse−width is required at IN+ before
OUT responds.
IN−
11
12
I
Inverted gate driver input. It is internally clamped to V
resistor of 50 kW to ensure that output is low in the absence of an input signal.
A minimum negative going pulse−width is required at IN− before OUT responds.
and has a pull−up
DD1
RDY
O
Power good indication output, active high when V
is good. There is
DD2
an internal 50 kW pull−up resistor connected to this pin. Multiple of them from
different drivers can be “OR”ed together.
If a low RDY event is triggered by UVLO2, the maximum low duration for RDY is
200 ns.
OUT remains low when RDY is low. Short time delay may apply. See Figure 4
for details.
FLT
13
O
Fault output (active low) that allows communication to the main controller that
the driver has encountered a desaturation condition and has deactivated the
output.
RST
14
15
I
Reset input with an internal 50 kW pull−up resistor, active low to reset fault latch.
V
DD1
Power
Input side power supply (3.3 V to 5 V).
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3
NCD57001F
SAFETY AND INSULATION RATINGS
Symbol
Parameter
Value
I − IV
I − IV
I − IV
I − IV
I − III
600
Unit
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
< 1000 V
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
−
Polution Degree (DIN VDE 0110/1.89)
−
V
Input−to−Output Test Voltage, Method b, V
x 1.875 = V , 100% Production Test
2250
V
V
V
PR
IORM
PR
pk
pk
pk
with tm = 1 s, Partial Discharge < 5 pC
Input−to−Output Test Voltage, Method a, V
x 1.6 = V , Type
−
IORM
PR
and Sample Test with tm = 10 s, Partial Discharge < 5 pC
V
IORM
Maximum Repetitive Peak Voltage
1200
870
8400
8.0
V
IOWM
Maximum Working Insulation Voltage
V
RMS
V
IOTM
Highest Allowable Over Voltage
V
pk
E
CR
External Creepage
mm
mm
um
°C
E
External Clearance
8.0
CL
DTI
Insulation Thickness
17.3
150
36
T
Case
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
P
mW
mW
W
S,INPUT
P
1364
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
10
IO
IO
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4
NCD57001F
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Parameter
Symbol
Minimum
−0.3
−0.3
−10
Maximum
Unit
V
Supply voltage, input side
V
V
−GND1
6
DD1
DD2
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
−GND2
−GND2
−V
25
0.3
25
V
V
V
EE2
V
0
V
DD2
MAX2
EE2
(V
)
Gate−driver output voltage
V
V
EE2
− 0.3
V + 0.3
DD2
V
A
OUT
Gate−driver output sourcing current (maximum pulse
width = 10 ms, maximum duty cycle = 0.2%, V
I
7.8
−
PK SRC
= 20 V)
MAX2
Gate−driver output sinking current (maximum pulse
width = 10 ms, maximum duty cycle = 0.2%, V
I
7.1
2.5
10
A
A
−
PK SNK
= 20 V)
MAX2
Clamp sinking current (maximum pulse width = 10 ms,
maximum duty cycle = 0.2%, V = 3 V)
I
−
PK CLAMP
CLAMP
Maximum Short Circuit Clamping Time
(I = 500 mA)
t
ms
CLP
OUT_CLAMP
Voltage at IN+, IN−, RST, FLT, RDY
Output current of FLT, RDY
Desat Voltage
V
I
−GND1
−GND1
−GND2
−GND2
PD
−0.3
V
+ 0.3
V
mA
V
LIM
DD1
10
LIM
V
V
−0.3
− 0.3
EE2
V
DD2
V
DD2
+ 0.3
DESAT
Clamp Voltage
V
+ 0.3
V
CLAMP
Power Dissipation
mW
SOIC−16 wide package
Maximum Junction Temperature
TJ(max)
TSTG
−40
−65
150
°C
°C
kV
kV
−
Storage Temperature Range
150
2
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Moisture Sensitivity Level
ESDHBM
ESDCDM
MSL
2
1
Lead Temperature Soldering Reflow, Pb−Free Versions
(Note 3)
T
SLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
150
84
Unit
2
RJA
Thermal Resistance,
Junction−to−Air
100 mm , 1 oz Copper, 1 Surface Layer
°C/W
2
650 mm , 1 oz Copper, 2 Surface Layers and
2 Internal Power Plane Layers
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
5. Values based on copper area of 100 mm (or 0.16 in ) of 1 oz copper thickness and FR4 PCB substrate.
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5
NCD57001F
Table 4. OPERATING RANGES (Note 6)
Parameter
Symbol
Min
UVLO1
UVLO2
−10
Max
5.5
24
0
Unit
V
Supply voltage, input side
V
V
−GND1
−GND2
−GND2
DD1
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
V
DD2
V
V
EE2
V
−V
MAX2
0
24
V
DD2
EE2
(V
)
Low level input voltage at IN+, IN−, RST
High level input voltage at IN+, IN−, RST
Common Mode Transient Immunity (1500 V)
Ambient Temperature
V
0
0.3 × V
V
V
IL
DD1
V
DD1
V
IH
0.7 × V
DD1
|dV /dt|
100
kV/ms
°C
ISO
TA
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
T = 25°C, Relative Humidity < 50%, t = 1.0
Min
Typ
Max
Unit
V
Input−Output
Isolation Voltage
5000
−
−
V
RMS
ISO, input−output
A
minute, I
10 A, 50 Hz (See Note 7, 8, 9)
I−O
11
R
Isolation
Resistance
V
I−O
= 500 V (See Note 7)
−
10
−
W
ISO
7. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together
8. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
9. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table
Table 5. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VOLTAGE SUPPLY
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
V
3.0
V
V
UVLO1−OUT−ON
V
2.4
0.125
13.2
12.2
UVLO1−OUT−OFF
V
V
UVLO1−HYST
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
V
13.5
12.5
1
13.8
12.8
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
V
V
V
UVLO2−HYST
Input Supply Quiescent Current
Output Low
IN+ = Low, IN− = Low
I
1
2
6
4
mA
DD1−0
RDY = High, FLT = High
IN+ = High, IN− = Low
Input Supply Quiescent Current
Output High
I
4.8
3.3
mA
mA
DD1−100
RDY = High, FLT = High
IN+ = Low, IN− = Low
Output Positive Supply
Quiescent Current,
Output Low
I
DD2−0
RDY = High, FLT = High, no load
IN+ = High, IN− = Low
Output Positive Supply
Quiescent Current,
Output High
I
I
4
5
mA
DD2−100
RDY = High, FLT = High, no load
IN+ = High, IN− = Low, no load
Output Negative Supply
Quiescent Current, Output Low
I
0.4
0.2
2
2
mA
mA
EE2−0
Output Negative Supply
Quiescent Current, Output High
IN+ = High, IN− = Low, no load
EE2−100
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NCD57001F
Table 5. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.) (continued)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LOGIC INPUT AND OUTPUT
IN+, IN−, RST Low Input
V
0.3 ×
V
DD1
V
V
V
IL
Voltage
IN+, IN−, RST High Input
Voltage
V
IH
0.7 ×
V
DD1
Input Hysteresis Voltage
V
0.15
IN−HYST
×
V
DD1
IN−, RST Input current
(50 kW pull−up resistor)
V
V
V
/V
= 0 V
I
, I
−100
mA
mA
mA
V
IN− RST
IN−L RST−L
IN+ Input Current
(50 kW pull−down resistor)
= 5 V
I
100
100
IN+
IN+H
RDY, FLT Pull−up Current
(50 kW pull−up resistor)
/V
= Low
I
, I
RDY FLT
RDY−L FLT−L
RDY, FLT Low Level Output
Voltage
I
/I
= 5 mA
V
, V
FLT−L
0.3
10
RDY FLT
RDY−L
Input Pulse Width of IN+, IN− for
No Response at Output
t
t
ns
ns
ns
ON−MIN1
ON−MIN2
Input Pulse Width of IN+, IN− for
Guaranteed Response at Output
30
Pulse Width of RST for
Resetting FLT
t
800
RST−MIN
DRIVER OUTPUT
Output Low State
I
I
I
I
= 200 mA
V
V
0.1
0.5
0.3
0.8
7.1
0.2
0.8
0.5
1
V
V
SINK
SINK
SRC
SRC
OUTL1
OUTL3
OUTH1
OUTH3
(V
– V
)
OUT
EE2
= 1.0 A, T = 25°C
A
Output High State
(V – V
= 200 mA
V
V
)
OUT
DD2
= 1.0 A, T = 25°C
A
Peak Driver Current, Sink
(Note 10)
V
= 7.9 V
I
A
A
OUT
PK−SNK1
Peak Driver Current, Source
(Note 10)
V
= −5 V
I
7.8
OUT
PK−SRC1
MILLER CLAMP
Clamp Voltage
I
I
= 2.5 A, T = 25°C
V
CLAMP
1.3
1.7
2.5
V
CLAMP
A
= 2.5 A, T = −40°C to
CLAMP
125°C
A
Clamp Activation Threshold
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
V
1.5
2
2.5
1
V
V
CLAMP−THR
IN+ = Low, IN− = High,
= 500 mA
V
0.9
CLAMP−OUT
I
OUT
(V
OUT
– V
)
DD2
(pulse test, t
= 10 ms)
CLPmax
Clamping Voltage, Clamp
(V − V
IN+ = High, IN− = Low,
I = 500 mA
CLAMP−CLAMP
V
1.4
1.5
V
CLAMP−CLAMP
)
CLAMP
DD2
(pulse test, t
= 10 ms)
CLPmax
DESAT PROTECTION
DESAT Threshold Voltage
Blanking Charge Current
Blanking Discharge Current
DYNAMIC CHARACTERISTIC
V
8.5
9
9.5
V
DESAT−THR
V
DESAT
= 7 V
I
0.45
0.5
50
0.55
mA
mA
DESAT−CHG
I
DESAT−DIS
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NCD57001F
Table 5. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.) (continued)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTIC
IN+, IN− to Output High
Propagation Delay
C
= 10 nF
t
40
60
90
ns
LOAD
PD−ON
V
IH
to 10% of output change for PW
> 150 ns. OUT and CLAMP pins are
connected together
IN+, IN− to Output Low
C
= 10 nF
t
40
66
90
ns
ns
LOAD
PD−OFF
Propagation Delay
V
IL
to 90% of output change for PW
> 150 ns. OUT and CLAMP pins are
connected together
Propagation Delay Distortion
T = 25°C, PW >150 ns
A
t
−15
−25
−30
−6
15
25
30
DISTORT
(= t
− t
)
PD−ON
PD−OFF
T = −40°C to 125°C, PW > 150 ns
A
Prop Delay Distortion between
Parts
PW > 150 ns
t
0
ns
ns
ns
ns
ns
ns
DISTORT_TOT
Rise Time (see Figure 3)
C
= 1 nF, 10% to 90% of
t
t
14
LOAD
RISE
Output Change
Fall Time (see Figure 3)
C
= 1 nF, 90% to 10% of
19
LOAD
FALL
Output Change
DESAT Leading Edge Blanking
Time (See Figure 5)
t
450
370
550
LEB
DESAT Threshold Filtering Time
(see Figure 5)
t
FILTER
Soft Turn Off Time (see Figure 5)
t
C
= 10 nF, R = 10 W.
G
= 0 V
STO
LOAD
V
EE2
C
= 10 nF, R = 10 W
750
450
5
LOAD
G
Delay after t
to FLT
t
1000
ns
ms
ns
ns
FILTER
FLT
Input Mute Time after t
t
MUTE
FILTER
RST Rise to FLT Rise Delay
t
23
55
100
100
RST
RDY High to Output High Delays
(see Figure 4)
t
t
RDY1O
RDY2O
V
to RDY Low
t
t
6
8
15
ms
UVLO2−OUT−OFF
RDY1F
Delays (see Figure 4)
RDY2F
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Values based on design and/or characterization.
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NCD57001F
V
IH
IL
IN+
V
t
t
t
MIN
FALL
RISE
90%
t
PD−ON
t
MIN
t
PD−OFF
10%
Figure 3. Simplified Block Diagram
RDY
RDY
t
t
RDY1F
RDY2F
IN+
IN+
V
UVLO2−OUT−ON
V
UVLO2−OUT−OFF
V
V
UVLO1−OUT−ON
V
DD1
UVLO1−OUT−OFF
V
DD2
V
t
t
UVLO2−OUT−ON
RDY2O
RDY1O
OUT
V
UVLO2−OUT−OFF
OUT
Figure 4. Simplified Block Diagram
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NCD57001F
IN+
t
MUTE
t
PD−ON
t
FILTER
V
EE2
+ 2V
V
OUT
t
STO
V
DESAT−THR
t
LEB
DESAT
t
FLT
FLT
t
RST
RST
t
RST−MIN
Figure 5. UVLO Waveform
Package
ORDERING INFORMATION
Device
†
Shipping
NCD57001FDWR2G
1,000 / Tape & Reel
SOIC−16 Wide Body
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
DATE 08 OCT 2021
1
SCALE 1:1
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
PAGE 1 OF 1
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