NBXDBB018_0910 [ONSEMI]
3.3 V, 155.52 MHz / 311.04MHz LVPECL Clock Oscillator; 3.3 V ， 155.52兆赫/ 311.04 ？ MHz的LVPECL时钟振荡器
| 型号： | NBXDBB018_0910 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V, 155.52 MHz / 311.04MHz LVPECL Clock Oscillator |
| 文件： | 总7页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBXDBB018, NBXDBA018
3.3 V, 155.52 MHz /
311.04ꢀMHz LVPECL Clock
Oscillator
The NBXDBB018 dual frequency crystal oscillator (XO) is
designed to meet today’s requirements for 3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 155.52
MHz or 311.04 MHz, ultra low jitter and phase noise LVPECL
differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000. Frequency stability options available as
either 50 PPM NBXDBA018 (Industrial Temperature Range) or
20 PPM NBXDBB018 (Commercial Temperature Range).
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6 PIN CLCC
LN SUFFIX
CASE 848AB
MARKING DIAGRAM
NBXDBA018
155.52/311.04
AAWLYYWWG
NBXDBB018
155.52/311.04
AAWLYYWWG
Features
• LVPECL Differential Output
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)
• Selectable Output Frequency − 155.52 MHz (default) / 311.04 MHz
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
NBXDBA018 = NBXDBA018 ( 50 PPM)
NBXDBB018 = NBXDBB018 ( 20 PPM)
155.52/311.04 = Output Frequency (MHz)
AA
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Operating Range 3.3 V 10%
• Total Frequency Stability − 20 PPM or 50 PPM
• This is a Pb−Free Device
ORDERING INFORMATION
Applications
• Networking
• SONET
• SDH
†
Device
Package
Shipping
NBXDBB018LN1TAG CLCC−6
(Pb−Free)
1000/
Tape & Reel
NBXDBA018LN1TAG CLCC−6
(Pb−Free)
1000/
Tape & Reel
NBXDBB018LNHTAG CLCC−6
(Pb−Free)
100/
Tape & Reel
V
CLK CLK
DD
6
5
4
NBXDBA018LNHTAG CLCC−6
(Pb−Free)
100/
Tape & Reel
PLL
Clock
Multiplier
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
1
2
3
OE
FSEL
GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. 3
NBXDBB018/D
NBXDBB018, NBXDBA018
1
2
3
6
5
4
OE
FSEL
GND
V
DD
CLK
CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
Control Input See OE pin description Table 2.
2
FSEL
LVTTL/LVCMOS Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Control Input
Power Supply
LVPECL Output
Frequency Select pin description Table 3.
3
4
GND
CLK
Ground 0 V
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
V
= V − 2 V.
TT
DD
5
6
CLK
LVPECL Output
Power Supply
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
= V − 2 V.
V
TT
DD
V
DD
Positive power supply voltage. Voltage should not exceed 3.3 V 10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
Table 3. OUTPUT FREQUENCY SELECT
OE Pin
Open
Output Pins
Active
FSEL Pin
Output Frequency (MHz)
Open
(pin will float high)
155.52
HIGH Level
LOW Level
Active
HIGH Level
LOW Level
155.52
311.04
High Z
Table 4. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Value
170 kW
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
Condition 2
Rating
Units
V
V
GND = 0 V
4.6
DD
out
I
LVPECL Output Current
Continuous
Surge
25
50
mA
T
Operating Temperature Range
Storage Temperature Range
Wave Solder
−40 to +85
−55 to +120
260
°C
°C
°C
A
T
stg
T
sol
See Figure 6
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXDBB018, NBXDBA018
Table 6. DC CHARACTERISTICS (V = 3.3 V 10%, GND = 0 V, T = −40°C to +85°C) (Note 2)
DD
A
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
mA
I
Power Supply Current (Note 2)
OE and FSEL Input HIGH Voltage
OE and FSEL Input LOW Voltage
78
100
DD
V
IH
2000
V
DD
mV
V
IL
GND − 300
800
mV
I
IH
Input HIGH Current
OE
FSEL
−100
−100
+100
+100
mA
I
IL
Input LOW Current
OE
FSEL
−100
−100
+100
+100
mA
V
Output HIGH Voltage (Note 2)
V
−1195
2105
V
−945
2355
mV
mV
mV
OH
DD
DD
V
V
= 3.3 V
DD
V
Output LOW Voltage (Note 2)
V
DD
−1945
1355
V
DD
−1600
1700
OL
= 3.3 V
DD
V
Output Voltage Amplitude (Note 2)
670
OUTPP
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 W to V − 2.0 V.
DD
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3
NBXDBB018, NBXDBA018
Table 7. AC CHARACTERISTICS (V = 3.3 V 10%, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
f
Output Clock Frequency
FSEL = HIGH
FSEL = LOW
155.52
MHz
CLKOUT
311.04
Df
Frequency Stability − NBXDBB018
− NBXDBA018
0°C to +70°C
−40°C to +85°C
(Note 4)
20
50
ppm
F
Phase−Noise Performance
CLKout
(See Figures 3 and 4)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
12 kHz to 20 MHz
1000 Cycles
−105/−102
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
NOISE
f
= 155.52 MHz/311.04 MHz
−122/−115
−129/−122
−129/−122
−137/−131
−160/−156
t (F)
jit
RMS Phase Jitter
0.4
2
0.9
8
t
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
ps
jitter
1000 Cycles
13
1
30
4
ps
10000 Cycles
ps
Period, Peak−to−Peak
Output Enable/Disable Time
10000 Cycles
9
20
200
52
ps
t
ns
OE/OD
t
Output Clock Duty Cycle
(Measured at Cross Point)
48
50
%
DUTY_CYCLE
t
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Startup Time
250
250
1
400
400
5
ps
ps
R
t
F
t
ms
start
st
Aging
1
Year
3
ppm
ppm
st
Every Year After 1
1
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 W to V − 2.0 V.
DD
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
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4
NBXDBB018, NBXDBA018
Figure 3. Typical Phase Noise Plot at 155.52 MHz
Figure 4. Typical Phase Noise Plot at 311.04 MHz
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5
NBXDBB018, NBXDBA018
Table 8. RELIABILITY COMPLIANCE
Parameter
Standard
Method
Shock
Mechanical
MIL−STD−833, Method 2002, Condition B
MIL−STD−833, Method 2003
Solderability
Mechanical
Mechanical
Mechanical
Environment
Environment
Vibration
MIL−STD−833, Method 2007, Condition A
MIL−STD−202, Method 215
Solvent Resistance
Thermal Shock
Moisture Level Sensitivity
MIL−STD−833, Method 1011, Condition A
MSL1 260°C per IPC/JEDEC J−STD−020D
NBXDBB018/NBXDBA018
Z = 50 W
CLK
CLK
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
D
50 W
50 W
V
TT
V
TT
= V − 2.0 V
DD
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
temp. 260°C
20 − 40 sec. max.
Temperature (°C)
6°C/sec. max.
peak
260
3°C/sec. max.
217
ramp−up
cooling
175
150
pre−heat
reflow
Time
60ꢀ 180 sec.
60ꢀ 150 sec.
Figure 6. Recommended Reflow Soldering Profile
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6
NBXDBB018, NBXDBA018
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB−01
ISSUE C
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D1
4X
0.15 C
2. CONTROLLING DIMENSION: MILLIMETERS.
MILLIMETERS
DIM
A
A1
A2
A3
b
MIN
1.70
NOM
1.80
0.70 REF
0.36 REF
0.10
MAX
1.90
E
E2
H E1
TERMINAL 1
INDICATOR
0.08
1.30
0.12
1.50
1.40
D
7.00 BSC
6.20
6.81
5.08 BSC
5.00 BSC
4.40
D1
D2
D3
E
E1
E2
E3
e
6.17
6.66
6.23
6.96
D2
TOP VIEW
A3
A2
4.37
4.65
4.43
4.95
0.10
C
4.80
3.49 BSC
2.54 BSC
1.80 REF
1.27
A
H
L
1.17
1.37
R
0.70 REF
SIDE VIEW
SEATING
PLANE
A1
C
SOLDERING FOOTPRINT*
D3
e
2
3
1
6X
1.50
R
E3
5.06
0.10
0.05
C
C
A
B
6
5
4
6X b
6X L
6X
1.50
BOTTOM VIEW
2.54
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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NBXDBB018/D
相关型号：
NBXDPA017LU1TAG
CRYSTAL OSCILLATOR, CLOCK, 156.25MHz, LVDS OUTPUT, HALOGEN FREE, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, CLCC, SMD, 6 PIN
ONSEMI
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