NBXDDA016LN1TAG [ONSEMI]
Clock Oscillator; 时钟振荡器
| 型号： | NBXDDA016LN1TAG |
| 厂家： | 
ONSEMI |
| 描述： | Clock Oscillator |
| 文件： | 总6页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBXDDA016, NBXDDB016
3.3 V, 133.33 MHz
/137.93 MHz Dual
Frequency CML Clock
Oscillator
The NBXDDB016/NBXDDA016 dual frequency crystal oscillator
(XO) is designed to meet today’s requirements for 3.3 V CML clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable
133.33 MHz or 137.93 MHz, ultra low jitter and phase noise CML
differential output.
http://onsemi.com
6 PIN CLCC
LN SUFFIX
CASE 848AB
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000. Frequency stability options available as
either 50 PPM NBXDDB016 or 20 PPM NBXDDA016.
MARKING DIAGRAMS
NBXDDB016
133.33/137.93
AWLYYWWG
NBXDDA016
133.33/137.93
AWLYYWWG
Features
• CML Differential Output
NBXDDA016 = NBXDDA016 ( 50 PPM)
NBXDDB016 = NBXDDB016 ( 20 PPM)
133.33/137.93 = Output Frequency (MHz)
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)
• Selectable Output Frequency − 133.33 MHz (default)/137.93 MHz
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Operating Range 3.3 V 10%
• Total Frequency Stability − 20 PPM or 50 PPM
ORDERING INFORMATION
Applications
Device
NBXDDB016LN1TAG* CLCC−6
(Pb−Free) Tape & Reel
Package Shipping†
• High−End Servers
1000/
• Basestation
• General Purpose Clock Generation and Margining
NBXDDA016LN1TAG CLCC−6
1000/
(Pb−Free) Tape & Reel
V
DD
CLK CLK
6
5
4
NBXDDA016LNHTAG CLCC−6
100/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
PLL
Clock
Multiplier
Crystal
* Please contact sales office for availability
1
2
3
OE
FSEL
GND
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
March, 2009 − Rev. 3
NBXDDA016/D
NBXDDA016, NBXDDB016
1
2
3
6
5
4
OE
FSEL
GND
V
DD
CLK
CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2
FSEL
Control Input
Output Frequency Select Pin. Pin will default LOW when left open. See Output Fre-
quency Select Table 3.
3
4
GND
CLK
Power Supply
CML Output
Ground 0 V.
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
V
TT
= V
.
DD
5
6
CLK
CML Output
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
= V
V
TT
.
DD
V
DD
Power Supply
Positive power supply voltage. Voltage should not exceed 3.3 V 10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
Table 3. OUTPUT FREQUENCY SELECT
OE Pin
Open
Output Pins
Active
FSEL Pin
Output Frequency (MHz)
Open
(pin will float Low)
133.33
High Level
Low Level
Active
High Level
Low Level
137.93
133.33
High Z
Table 4. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Value
170 kW
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
Condition 2
Rating
Units
V
V
DD
GND = 0 V
4.6
T
Operating Temperature Range
Storage Temperature Range
Wave Solder
−40 to +85
−55 to +120
260
°C
A
T
stg
°C
T
sol
See Figure 6
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXDDA016, NBXDDB016
Table 6. DC CHARACTERISTICS (V = 3.3 V 10%, GND = 0 V, T = −40°C to +85°C) (Note 2)
DD
A
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
I
Power Supply Current (Note 2)
OE Input HIGH Voltage
OE Input LOW Voltage
Input HIGH Current
70
100
mA
DD
V
2000
V
DD
mV
mV
mA
IH
V
GND − 300
800
IL
I
OE
−100
−100
+100
+100
IH
FSEL
I
IL
Input LOW Current
OE
FSEL
−100
−100
+100
+100
mA
V
FSEL Input HIGH Voltage
FSEL Input LOW Voltage
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
2000
0
V
mV
mV
mV
mV
mV
IH
DD
V
800
IL
V
OH
V −40
DD
V
DD
V
OL
V
−450
DD
V
−380
V
−300
DD
DD
V
Output Voltage Amplitude (Note 2)
380
OUTPP
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to V . See Figure 5.
DD
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3
NBXDDA016, NBXDDB016
Table 7. AC CHARACTERISTICS (V = 3.3 V 10%, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
f
Output Clock Frequency
MHz
FSEL = HIGH
FSEL = LOW
(Note 4)
137.93
133.33
CLKOUT
Df
Frequency Stability − NBXDDB016
Frequency Stability − NBXDDA016
20
50
ppm
F
Phase−Noise Performance
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
12 kHz to 20 MHz
1000 Cycles
−102
−120
−126
−126
−134
−162
0.4
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
NOISE
f
= 133.33 MHz/137.93 MHz
CLKout
(See Figures 3 and 4)
t (F)
jit
RMS Phase Jitter
0.9
8
t
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
1.5
ps
jitter
1000 Cycles
10
30
4
ps
10,000 Cycles
0.8
ps
Period, Peak−to−Peak
Output Enable/Disable Time
10,000 Cycles
7
20
200
52
ps
t
ns
OE/OD
t
Output Clock Duty Cycle
(Measured at Cross Point)
48
50
%
DUTY_CYCLE
t
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start−up Time
160
160
1
300
300
5
ps
ps
R
t
F
t
ms
start
st
Aging
1
Year
3
ppm
ppm
st
Every Year After 1
1
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to V . See Figure 5.
DD
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
Figure 3. Typical Phase Noise Plot @ 133.33 MHz
Figure 4. Typical Phase Noise Plot @ 137.93 MHz
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4
NBXDDA016, NBXDDB016
Table 8. RELIABILITY COMPLIANCE
Parameter
Standard
Method
Shock
Mechanical
MIL−STD−833, Method 2002, Condition B
MIL−STD−833, Method 2003
Solderability
Mechanical
Mechanical
Mechanical
Environment
Environment
Vibration
MIL−STD−833, Method 2007, Condition A
MIL−STD−202, Method 215
Solvent Resistance
Thermal Shock
Moisture Level Sensitivity
MIL−STD−833, Method 1011, Condition A
MSL1 260°C per IPC/JEDEC J−STD−020D
V
TT
= V
DD
NBXDDB016/NBXDDA016
CLK
50 W
Z = 50 W
50 W
D
D
Receiver
Device
Driver
Device
Z = 50 W
CLK
Figure 5. Typical CML Termination for Output Driver and Device Evaluation
(See Application Note AND8173 − Termination of CML Devices)
temp. 260°C
20 − 40 sec. max.
Temperature (°C)
6°C/sec. max.
peak
260
3°C/sec. max.
217
ramp−up
cooling
175
150
pre−heat
reflow
Time
60ꢀ 180 sec.
60ꢀ 150 sec.
Figure 6. Recommended Reflow Soldering Profile
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5
NBXDDA016, NBXDDB016
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB−01
ISSUE C
A
B
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D1
4X
0.15
C
2. CONTROLLING DIMENSION: MILLIMETERS.
MILLIMETERS
DIM
A
A1
A2
A3
b
MIN
1.70
NOM
1.80
0.70 REF
0.36 REF
0.10
MAX
1.90
E
E2
H E1
TERMINAL 1
INDICATOR
0.08
1.30
0.12
1.50
1.40
D
7.00 BSC
6.20
6.81
5.08 BSC
5.00 BSC
4.40
D1
D2
D3
E
E1
E2
E3
e
6.17
6.66
6.23
6.96
D2
TOP VIEW
A3
A2
4.37
4.65
4.43
4.95
0.10
C
4.80
3.49 BSC
2.54 BSC
1.27
A
L
1.17
1.37
R
0.70 REF
SIDE VIEW
SEATING
PLANE
A1
C
D3
SOLDERING FOOTPRINT*
e
2
3
1
R
6X
1.50
E3
5.06
0.10
0.05
C
C
A
B
6
5
4
6X b
6X L
BOTTOM VIEW
6X
2.54
PITCH
1.50
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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NBXDDA016/D
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