MTD2955ET4 [ONSEMI]
12A, 60V, 0.3ohm, P-CHANNEL, Si, POWER, MOSFET, CASE 369A-13, DPAK-3;
| 型号： | MTD2955ET4 |
| 厂家： | 
ONSEMI |
| 描述： | 12A, 60V, 0.3ohm, P-CHANNEL, Si, POWER, MOSFET, CASE 369A-13, DPAK-3 开关 脉冲 晶体管 |
| 文件： | 总12页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD2955E
Preferred Device
TMOS E−FET. Power Field
Effect Transistor DPAK for
Surface Mount
P−Channel Enhancement−Mode Silicon
Gate
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TMOS POWER FET
12 AMPERES
60 VOLTS
This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
R
DS(on) = 0.3 W
D
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
G
S
• Diode is Characterized for Use in Bridge Circuits
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
MARKING
• Surface Mount Package Available in 16 mm, 13 inch /
2500 Unit Tape & Reel, Add T4 Suffix to Part Number
• Replaces the MTD2955
DIAGRAM
YWW
xxxxxxxx
DPAK
SUFFIX
CASE 369A
Style 2
xxxxxxxxx = Specific Device Code
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTD2955ET4
DPAK
2500/ Tape &
Reel
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
April, 2003 − Rev. 5
MTD2955E/D
MTD2955E
MAXIMUM RATINGS (T = 25°C Unless Otherwise Noted)
C
Rating
Symbol
Value
60
Unit
Vdc
Vdc
Drain−Source Voltage
V
DSS
DGR
Drain−Gate Voltage (R = 1.0 MW)
V
V
60
GS
Gate−Source Voltage
− Continuous
V
GS
$ 15
Vdc
Vpk
− Non−Repetitive (t ≤ 10 ms)
$ 25
p
GSM
Drain Current − Continuous
I
I
12
7.0
36
Adc
Apk
D
D
− Continuous @ 100°C
− Single Pulse (t v 10 ms)
I
p
DM
Total Power Dissipation
P
75
0.6
1.75
Watts
W/°C
Watts
D
Derate above 25°C
Total Power Dissipation @ T = 25°C, When Mounted to Minimum Recommended Pad Size
A
Operating and Storage Temperature Range
T , T
−55 to 150
216
°C
J
stg
Single Pulse Drain−to−Source Avalanche Energy − Starting T = 25°C
E
AS
mJ
J
(V = 25 Vdc, V = 10 Vdc, I = 12 Apk, L = 3.0 mH, R = 25 W)
DD
GS
L
G
Thermal Resistance
°C/W
°C
Junction−to−Case
Junction−to−Ambient
Junction−to−Ambient, When Mounted to Minimum Recommended Pad Size
R
R
R
1.67
100
71.4
q
JC
JA
JA
q
q
Maximum Temperature for Soldering Purposes, 1/8” From Case for 10 Seconds
T
260
L
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MTD2955E
ELECTRICAL CHARACTERISTICS (T = 25°C Unless Otherwise Noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−Source Breakdown Voltage
V
(BR)DSS
(V = 0 Vdc, I = 250 mAdc)
60
−
−
85
−
−
Vdc
mV/°C
GS
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
mAdc
DSS
GSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
10
100
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current (V = ±15 Vdc, V = 0)
I
−
−
100
nAdc
GS
DS
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
V
GS(th)
(V = V , I = 250 mAdc)
2.0
−
−
3.0
4.0
−
Vdc
mV/°C
DS
GS
D
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V = 10 Vdc, I = 6.0 Adc)
R
V
−
0.26
0.30
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V = 10 Vdc)
GS
DS(on)
(I = 12 Adc)
(I = 6.0 Adc, T = 125°C)
D
−
−
−
−
4.3
3.8
D
J
Forward Transconductance (V = 13 Vdc, I = 6.0 Adc)
g
FS
3.0
4.8
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
565
225
45
700
315
100
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
9.0
39
20
80
35
20
32
−
ns
d(on)
(V = 30 Vdc, I = 12 Adc,
Rise Time
t
r
DD
D
V
R
= 10 Vdc,
= 9.1 W)
GS
Turn−Off Delay Time
Fall Time
t
17
d(off)
G
t
f
8.0
16
Gate Charge
(Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
3.0
6.0
5.0
(V = 48 Vdc, I = 12 Adc,
DS
D
V
GS
= 10 Vdc)
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
V
Vdc
ns
SD
(I = 12 Adc, V = 0 Vdc)
S
GS
−
−
2.2
1.8
3.8
−
(I = 12 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(Figure 14)
t
−
−
−
−
100
75
−
−
−
−
rr
t
a
(I = 12 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/ms)
S
t
25
b
Q
0.475
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
−
−
4.5
7.5
−
−
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25” from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
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MTD2955E
TYPICAL ELECTRICAL CHARACTERISTICS
−ꢀ24
−ꢀ18
−ꢀ12
−ꢀ6
−ꢀ24
V
=ꢀ10ꢀV
T = 25°C
V
DS
≥ 10 V
GS
J
T = −ꢀ55°C
J
9 V
−ꢀ20
−ꢀ16
−12
−ꢀ8
−ꢀ4
0
8 V
7 V
25°C
100°C
6 V
5 V
0
0
−1
−2
−ꢀ3 −ꢀ4
−ꢀ5 −ꢀ6
−ꢀ7 −ꢀ8
−ꢀ9 −10
−2
−ꢀ3
−ꢀ4
−ꢀ5
−ꢀ6
−ꢀ7
−ꢀ8
−ꢀ9
−ꢀ10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.48
0.44
0.40
V
= 10 V
GS
T = 25°C
J
T = 100°C
J
V
GS
=ꢀ10ꢀV
0.36
0.32
0.28
0.24
0.20
25°C
15 V
−ꢀ55°C
0.2
0.1
0
−ꢀ2 −ꢀ4 −ꢀ6 −ꢀ8 −10 −12 −14 −16 −ꢀ18 −ꢀ20 −ꢀ22 −ꢀ24
0
−ꢀ2 −ꢀ4 −ꢀ6 −ꢀ8 −10 −12 −14 −16 −18 −ꢀ20 −ꢀ22 −ꢀ24
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1.6
1.4
1.2
1000
100
10
V
=ꢀ0ꢀV
GS
V
= 10 V
GS
=ꢀ6 A
I
D
T = 125°C
J
100°C
25°C
1.0
0.8
0.6
−ꢀ50
−ꢀ25
0
25
50
75
100
125
150
−15 −ꢀ20 −ꢀ25 −ꢀ30 −ꢀ35 −ꢀ40 −ꢀ45 −ꢀ50 −ꢀ55 −ꢀ60
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTD2955E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in Figure 9 is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1600
1400
V
DS
= 0
V
GS
= 0
T = 25°C
J
C
C
iss
1200
1000
800
600
400
200
0
rss
C
iss
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD2955E
1000
70
14
12
10
8
V
I
= 30 V
DD
= 12 A
60
D
QT
V
GS
= 10 V
50
T = 25°C
J
V
GS
100
Q1
Q2
40
30
tr
6
t
d(off)
10
I
= 12 A
D
t
d(on)
4
20
T = 25°C
J
t
f
2
0
10
Q3
V
DS
1
0
0
2
4
6
8
10
12
14
16
18
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
12
V
GS
= 0 V
T = 25°C
J
10
8
6
4
2
0
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1 2.2
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12).
r f
exceed (T
− T )/(R ).
Maximum energy at currents below rated continuous I can
J(MAX)
C
qJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
safely be assumed to equal the values indicated.
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MTD2955E
SAFE OPERATING AREA
100
10
240
200
160
120
I
D
= 12 A
V
= 20 V
SINGLE PULSE
GS
T
= 25°C
C
100 ms
1 ms
10 ms
1.0
0.1
dc
80
40
0
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
10
100
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
q
(t) = r(t) R
q
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.05
0.02
t
1
1
0.01
t
2
T
− T = P
C
R (t)
q
JC
J(pk)
(pk)
SINGLE PULSE
DUTY CYCLE, D = t /t
1 2
0.01
0.00001
0.0001
0.001
0.01
t, TIME (SECONDS)
0.1
1.0
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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MTD2955E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.165
4.191
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
example, a graph of R
Figure 15.
versus drain pad area is shown in
qJA
surface mount device is determined by T
maximum rated junction temperature of the die, R , the
, the
J(max)
100
qJA
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
thermal resistance from the device Junction−to−Ambient,
and the operating temperature, T . Using the values
1.75 Watts
A
80
60
40
20
provided on the data sheet, P can be calculated as follows:
D
T = 25°C
A
T
J(max) − TA
Rq
°
PD =
JA
3.0 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
A
5.0 Watts
calculate the power dissipation of the device. For a DPAK
device, P is calculated as follows.
D
0
2
4
6
8
10
150°C − 25°C
= 1.75 Watts
PD =
A, Area (square inches)
71.4°C/W
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the area
of the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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8
MTD2955E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
SOLDER PASTE
OPENINGS
2
and D PAK packages. If one uses a 1:1 opening to screen
STENCIL
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
2
typical stencil for the DPAK and D PAK packages. The
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Due to shadowing and the inability to set the wave height
2
to incorporate other surface mount components, the D PAK
is not recommended for wave soldering.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
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MTD2955E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 17 shows a typical heating profile
for use when soldering a surface mount device to a printed
circuit board. This profile will vary among soldering
systems but it is a good starting point. Factors that can affect
the profile include the type of soldering system in use,
density and types of components on the board, type of solder
used, and the type of board or substrate material being used.
This profile shows temperature versus time. The line on the
a
low density board. The Vitronics SMD310
convection/infrared reflow soldering system was used to
generate this profile. The type of solder used was 62/36/2
Tin Lead Silver with a melting point between 177−189°C.
When this type of furnace is used for solder reflow work, the
circuit boards and solder joints tend to heat first. The
components on the board are then heated by conduction. The
circuit board, because it has a large surface area, absorbs the
thermal energy more efficiently, then distributes this energy
to the components. Because of this effect, the main body of
a component may be up to 30 degrees cooler than the
adjacent solder joints.
STEP 5
HEATING
ZONES 4 & 7
SPIKE"
STEP 6
VENT
STEP 7
COOLING
STEP 1
PREHEAT
ZONE 1
RAMP"
STEP 4
HEATING
ZONES 3 & 6
SOAK"
STEP 2
VENT
STEP 3
HEATING
SOAK" ZONES 2 & 5
RAMP"
205° TO 219°C
PEAK AT
SOLDER JOINT
200°C
150°C
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
100°C
50°C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 17. Typical Solder Heating Profile
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10
MTD2955E
PACKAGE DIMENSIONS
DPAK
CASE 369A−13
ISSUE AB
SEATING
PLANE
−T−
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.84
0.94
MAX
6.35
6.73
2.38
0.88
1.01
1.19
A
B
C
D
E
F
0.235
0.250
0.086
0.027
0.033
0.037
0.250
0.265
0.094
0.035
0.040
0.047
4
2
Z
A
K
S
1
3
G
H
J
0.180 BSC
4.58 BSC
U
0.034
0.018
0.102
0.040
0.023
0.114
0.87
0.46
2.60
1.01
0.58
2.89
K
L
0.090 BSC
2.29 BSC
F
J
R
S
U
V
Z
0.175
0.020
0.020
0.030
0.138
0.215
0.050
−−−
0.050
−−−
4.45
0.51
0.51
0.77
3.51
5.46
1.27
−−−
1.27
−−−
L
H
D 2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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11
MTD2955E
E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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MTD2955E/D
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