MTD2955V [ONSEMI]
Power MOSFET 12A, 60V P-Channel DPAK; 功率MOSFET的12A ， 60V P沟道DPAK
| 型号： | MTD2955V |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 12A, 60V P-Channel DPAK |
| 文件： | 总10页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD2955V
Power MOSFET 12 A, 60 V
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
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12 A, 60 V
R
DS(on) = 185 mW (Typ)
Features
• Avalanche Energy Specified
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
P−Channel
• Pb−Free Packages are Available
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
60
Unit
Vdc
Vdc
Drain−to−Source Voltage
V
DSS
G
Drain−to−Gate Voltage (R = 1.0 MW)
V
DGR
60
GS
S
Gate−to−Source Voltage
− Continuous
V
± 20
± 25
Vdc
Vpk
GS
− Non−repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (t ≤ 10 ms)
I
I
12
8.0
42
Adc
D
D
I
DM
Apk
p
4
DPAK−3
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C (Note 2)
P
D
60
0.4
2.1
Watts
W/°C
Watts
CASE 369C
STYLE 2
2
1
3
Operating and Storage Temperature
Range
T , T
−55 to
175
°C
J
stg
Single Pulse Drain−to−Source Avalanche
E
AS
216
mJ
Energy − Starting T = 25°C
J
4
(V = 25 Vdc, V = 10 Vdc, Peak
DD
GS
I = 12 Apk, L = 3.0 mH, R = 25 W)
L
G
DPAK−3
CASE 369D
STYLE 2
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1)
− Junction to Ambient (Note 2)
°C/W
°C
R
R
R
2.5
100
71.4
q
JC
JA
JA
1
q
2
3
q
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
T
260
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using the 0.5 sq.in. pad size.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
April, 2004 − Rev. 7
MTD2955V/D
MTD2955V
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V = 0 Vdc, I = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 5)
V
Vdc
mV/°C
mAdc
(BR)DSS
60
−
−
58
−
−
GS
D
Zero Gate Voltage Drain Current
I
DSS
−
−
−
−
10
100
(V = 60 Vdc, V = 0 Vdc)
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V = ± 20 Vdc, V = 0 Vdc)
I
−
−
100
nAdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(V = V , I = 250 mAdc)
(Cpk ≥ 2.0) (Note 5)
(Cpk ≥ 1.5) (Note 5)
V
Vdc
mV/°C
W
GS(th)
2.0
−
2.8
5.0
4.0
−
DS
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
R
V
DS(on)
−
0.185
0.230
(V = 10 Vdc, I = 6.0 Adc)
GS
D
Drain−to−Source On−Voltage
(V = 10 Vdc, I = 12 Adc)
Vdc
DS(on)
−
−
−
−
2.9
2.5
GS
D
(V = 10 Vdc, I = 6.0 Adc, T = 150°C)
GS
D
J
Forward Transconductance (V = 10 Vdc, I = 6.0 Adc)
g
FS
3.0
5.0
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
C
−
−
−
550
200
50
770
280
100
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
C
rss
t
−
−
−
−
−
−
−
−
15
50
30
100
50
80
30
−
ns
d(on)
(V = 30 Vdc, I = 12 Adc,
Rise Time
t
r
DD
D
V
GS
= 10 Vdc,
= 9.1 W)
Turn−Off Delay Time
Fall Time
t
24
R
d(off)
G
t
f
39
Gate Charge
Q
T
Q
1
Q
2
Q
3
19
nC
4.0
9.0
7.0
(V = 48 Vdc, I = 12 Adc,
DS
D
V
GS
= 10 Vdc)
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
V
Vdc
ns
SD
(I = 12 Adc, V = 0 Vdc)
S
GS
−
−
1.8
1.5
3.0
−
(I = 12 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
115
90
−
−
−
−
rr
t
a
(I = 12 Adc, V = 0 Vdc,
S
GS
t
25
b
dI /dt = 100 A/ms)
S
Reverse Recovery Stored
Charge
Q
0.53
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
nH
nH
D
−
−
3.5
4.5
−
−
Internal Source Inductance
L
S
−
7.5
−
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
5. Reflects typical values.
Max limit − Typ
C
=
pk
3 x SIGMA
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2
MTD2955V
TYPICAL ELECTRICAL CHARACTERISTICS
24
25
20
15
10
5
V
DS
≥ 10 V
T = 25°C
J
T = −ꢀ55°C
J
V
GS
= 10 V
9 V
8 V
7 V
21
18
15
12
9
100°C
25°C
6 V
5 V
6
3
0
0
0
1
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.250
0.225
0.200
0.175
0.150
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
T = 25°C
V
GS
= 10 V
J
V
GS
= 10 V
T = 100°C
J
25°C
15 V
0.125
0.100
0.075
0.050
−ꢀ55°C
0
3
6
9
12
15
18
21
24
0
3
6
9
12
15
18
21
24
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1000
100
10
V
GS
= 0 V
V
= 10 V
GS
I
D
= 6 A
T = 125°C
J
100°C
−ꢀ50 −ꢀ25
0
25
50
75
100 125
150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD2955V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1800
1600
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
C
iss
1400
1200
1000
800
600
400
200
0
C
rss
C
iss
C
C
oss
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD2955V
1000
30
10
9
8
7
6
5
4
3
2
1
0
V
= 30 V
DD
QT
27
24
I
D
= 12 A
V
= 10 V
GS
T = 25°C
Q1
Q2
J
21
V
GS
100
18
15
12
t
r
t
f
t
d(off)
d(on)
t
10
9
I
= 12 A
D
T = 25°C
6
3
J
Q3
V
DS
1
0
20
1
10
R , GATE RESISTANCE (OHMS)
100
0
2
4
6
8
10
12
14
16
18
Q , TOTAL CHARGE (nC)
T
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
12
V
= 0 V
11
GS
T = 25°C
J
10
9
8
7
6
5
4
3
2
1
0
0.5
0.7
V
0.9
1.1
1.3
1.5
1.7
1.9
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T )/(R ).
energy at currents below rated continuous I can safely be
J(MAX)
C
qJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
assumed to equal the values indicated.
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5
MTD2955V
SAFE OPERATING AREA
225
200
175
150
125
100
10
V
= 15 V
GS
SINGLE PULSE
= 25°C
I
D
= 12 A
T
C
100 ms
1 ms
100
75
50
25
0
10 ms
1.0
0.1
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.05
0.1
R
q
(t) = r(t) R
q
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
0.01
SINGLE PULSE
t
READ TIME AT t
1
1
t
2
T
− T = P
C
R (t)
q
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MTD2955V
ORDERING INFORMATION
Device
†
Package
Shipping
MTD2955V
DPAK−3
75 Units/Rail
75 Units/Rail
MTD2955VG
DPAK−3
(Pb−Free)
MTD2955V−1
DPAK−3
75 Units/Rail
MTD2955V−1G
DPAK−3
(Pb−Free)
75 Units/Rail
MTD2955VT4
DPAK−3
2500 Tape & Reel
2500 Tape & Reel
MTD2955VT4G
DPAK−3
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
DPAK−3
DPAK−3
CASE 369D
CASE 369C
STYLE 2
STYLE 2
4
Drain
4
Drain
2
1
Gate
3
Drain
1
2
3
Source
Gate Drain Source
2955V
Y
Device Code
= Year
WW
= Work Week
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7
MTD2955V
PACKAGE DIMENSIONS
DPAK−3
CASE 369C−01
ISSUE O
NOTES:
SEATING
PLANE
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MTD2955V
DPAK−3
CASE 369D−01
ISSUE B
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
G
M
T
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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9
MTD2955V
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local Sales Representative.
MTD2955V/D
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