MMFT1N10ET3 [ONSEMI]
1000mA, 100V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-261AA;
| 型号： | MMFT1N10ET3 |
| 厂家： | 
ONSEMI |
| 描述： | 1000mA, 100V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-261AA 局域网 开关 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MMFT1N10E/D
SEMICONDUCTOR TECHNICAL DATA
N–Channel Enhancement Mode
Silicon Gate TMOS E–FET
SOT–223 for Surface Mount
Motorola Preferred Device
MEDIUM POWER
TMOS FET
1 AMP
This advanced E–FET is a TMOS Medium Power MOSFET
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient device also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
dc–dc converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients. The device is
housed in the SOT–223 package which is designed for medium
power surface mount applications.
100 VOLTS
R
= 0.25 OHM
DS(on)
2,4
4
D
1
2
•
•
•
Silicon Gate for Fast Switching Speeds
Low R — 0.25 Ω max
The SOT–223 Package can be Soldered Using Wave or Re-
flow. The Formed Leads Absorb Thermal Stress During Sol-
dering, Eliminating the Possibility of Damage to the Die
Available in 12 mm Tape and Reel
3
1
DS(on)
G
CASE 318E–04, STYLE 3
TO–261AA
S
3
•
Use MMFT1N10ET1 to order the 7 inch/1000 unit reel.
Use MMFT1N10ET3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Drain–to–Source Voltage
Symbol
Value
100
Unit
Vdc
Adc
V
DS
GS
Gate–to–Source Voltage — Continuous
V
±20
Drain Current — Continuous
Drain Current — Pulsed
I
D
1
4
I
DM
Total Power Dissipation @ T = 25°C
Derate above 25°C
0.8
6.4
Watts
mW/°C
A
(1)
P
D
Operating and Storage Temperature Range
T , T
stg
–65 to 150
168
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 60 V, V = 10 V, Peak I = 1 A, L = 0.2 mH, R = 25 Ω)
GS L G
DEVICE MARKING
1N10
THERMAL CHARACTERISTICS
Thermal Resistance — Junction–to–Ambient (surface mounted)
R
156
°C/W
θJA
Maximum Temperature for Soldering Purposes,
Time in Solder Bath
260
10
°C
Sec
T
L
(1) Power rating when mounted on FR–4 glass epoxy printed circuit board using recommended footprint.
TMOS is a registered trademark of Motorola, Inc.
E–FET is a trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (V
GS
= 0, I = 250 µA)
V
100
—
—
—
—
—
10
Vdc
µAdc
nAdc
D
(BR)DSS
Zero Gate Voltage Drain Current, (V
DS
= 100 V, V
= 0)
I
GS
DSS
Gate–Body Leakage Current, (V
= 20 V, V
DS
= 0)
I
—
100
GS
GSS
ON CHARACTERISTICS
Gate Threshold Voltage, (V
DS
= V , I = 1 mA)
GS
V
2
—
—
4.5
0.25
0.33
—
Vdc
Ohms
Vdc
D
GS(th)
DS(on)
DS(on)
Static Drain–to–Source On–Resistance, (V
GS
= 10 V, I = 0.5 A)
R
V
—
—
—
D
Drain–to–Source On–Voltage, (V
GS
= 10 V, I = 1 A)
—
D
Forward Transconductance, (V
= 10 V, I = 0.5 A)
D
g
FS
2.2
mhos
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
C
—
—
—
410
145
55
—
—
—
iss
(V
V
f = 1 MHz)
= 20 V,
= 0,
DS
GS
Output Capacitance
pF
oss
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS
Turn–On Delay Time
t
—
—
—
—
—
—
—
15
15
30
32
7
—
—
—
—
—
—
—
d(on)
(V
= 25 V, I = 0.5 A
D
Rise Time
DD
t
r
ns
V
= 10 V, R = 50 ohms,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 25 ohms)
GS
t
f
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Q
g
(V
= 80 V, I = 1 A,
D
DS
V
Q
1.3
3.2
nC
= 10 Vdc)
gs
gd
GS
See Figures 15 and 16
Q
(1)
SOURCE DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
I
= 1 A, V
= 1 A, V
= 0
V
t
—
—
0.8
—
Vdc
ns
S
GS
SD
Forward Turn–On Time
Reverse Recovery Time
Limited by stray inductance
90
I
S
= 0,
on
GS
dl /dt = 400 A/µs,
S
t
—
rr
V
= 50 V
R
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%
2
Motorola TMOS Power MOSFET Transistor Device Data
10
8
1.2
1.1
1.0
10 V
9 V
7 V
= 25
8 V
V
I
= V
GS
DS
= 1.0 mA
T
°
C
D
J
6 V
6
4
0.9
0.8
0.7
5 V
2
0
V
= 4 V
GS
0
2
4
6
8
10
–50
0
50
T , JUNCTION TEMP (°C)
100
150
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
J
Figure 1. On Region Characteristics
Figure 2. Gate–Threshold Voltage Variation
With Temperature
4
3
2
0.5
0.4
0.3
V
= 10 V
V
= 10 V
T
= –55°C
GS
DS
J
100°C
25
°
C
T
= 100°C
J
25
°
C
0.2
0.1
0
–55
°
C
1
0
0
2
4
6
8
10
0
2
4
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
I , DRAIN CURRENT (AMPS)
D
GS
Figure 3. Transfer Characteristics
Figure 4. On–Resistance versus Drain Current
0.5
0.4
0.3
0.5
0.4
T
= 25
= 1 A
°
C
V
= 10 V
J
GS
I = 1 A
D
I
D
0.3
0.2
0.1
0
0.2
0.1
0
4
6
8
10
12
14
16
–50
0
50
100
C)
150
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (
°
GS
J
Figure 5. On–Resistance versus
Gate–to–Source Voltage
Figure 6. On–Resistance versus Junction
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
3
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on an ambient temperature of 25°C and a
maximum junction temperature of 150°C. Limitations for re-
petitive pulses at various ambient temperatures can be de-
termined by using the thermal response curves. Motorola
Application Note, AN569, “Transient Thermal Resistance–
General Data and Its Use” provides detailed instructions.
10
1
V
= 20 V
GS
SINGLE PULSE
= 25
T
°C
A
20 ms
100 ms
0.1
1 s
DC
500 ms
0.01
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
0.001
0.1
1
10
100
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
I
and the breakdown voltage, BV . The switching SOA
DM
DSS
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
is applicable for both turn–on and turn–off of the devices for
switching times less than one microsecond.
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
R
R
(t) = r(t) R
θ
(pk)
θ
θ
JA
JA
JA
°C/W MAX
= 156
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01
READ TIME AT t
1
0.01
t
1
T
– T = P
A
R
(t)
JA
J(pk)
(pk)
θ
t
SINGLE PULSE
2
DUTY CYCLE, D = t /t
1 2
0.001
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
1.0E+00
1.0E+01
Figure 8. Thermal Response
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source–drain
current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows the limita-
tions of I
and peak V
for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
FM
9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dI /dt is specified with a maximum value. Higher
DS
S
values of dI /dt require an appropriate derating of I , peak V
or both. Ultimately dI /dt is limited primarily by device, package,
S
FM
DS
S
and circuit impedances. Maximum device stress occurs during t as the diode goes from conduction to reverse blocking.
rr
V
is the peak drain–to–source voltage that the device must sustain during commutation; I
is the maximum forward
FM
DS(pk)
source–drain diode current just prior to the onset of commutation.
is specified at 80% rated BV to ensure that the CSOA stress is maximized as I decays from I
V
R
to zero.
R
GS
DSS
S
RM
/dt in excess of 10 V/ns was at-
should be minimized during commutation. T has only a second order effect on CSOA.
J
Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dV
tained with dI /dt of 400 A/µs.
DS
S
4
Motorola TMOS Power MOSFET Transistor Device Data
15 V
0
V
GS
I
FM
dl /dt
S
90%
I
S
t
rr
10%
t
I
on
RM
0.25 I
RM
t
frr
V
DS(pk)
V
V
R
V
DS
dsL
V
f
MAX. CSOA
STRESS AREA
Figure 9. Commutating Waveforms
5
R
GS
4.5
dI /dt
S
≤ 400 A/µs
DUT
4
3.5
3
–
V
R
2.5
2
I
I
S
L
i
+
FM
V
DS
+
1.5
1
20 V
–
V
GS
0.5
0
0
20
40
60
80
100
120
140
V
= 80% OF RATED V
DSS
R
V
= V + L dl /dt
dsL
f i S
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
Figure 10. Commutating Safe Operating Area
(CSOA)
Figure 11. Commutating Safe Operating Area
Test Circuit
BV
DSS
L
V
DS
I
I
L
L(t)
V
DD
R
G
t
V
DD
t
P
t, (TIME)
Figure 12. Unclamped Inductive Switching
Test Circuit
Figure 13. Unclamped Inductive Switching
Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
V
V
GS
DS
1400
1200
C
iss
T
= 25°C
J
f = 1 MHz
C
C
oss
rss
1000
800
600
400
C
iss
C
oss
200
0
C
rss
20
15
10
5
0
5
10
15
20
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 14. Capacitance Variation With Voltage
10
8
V
= 50 V
V
= 80 V
DS
DS
6
4
T
= 25°C
= 1 A
J
I
D
2
0
V
= 10 V
GS
0
2
4
6
8
Q , TOTAL GATE CHARGE (nC)
g
Figure 15. Gate Charge versus Gate–To–Source Voltage
+18 V
47 k
V
DD
SAME
DEVICE TYPE
AS DUT
1 mA
10 V
100 k
V
15 V
0.1 µF
in
2N3904
2N3904
FERRITE
BEAD
100 k
DUT
100
47 k
V
= 15 V ; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
pk
in
Figure 16. Gate Charge Test Circuit
6
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to insure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.15
3.8
0.079
2.0
0.248
6.3
0.091
2.3
0.091
2.3
0.079
2.0
inches
mm
0.059
1.5
0.059
1.5
0.059
1.5
SOT–223
SOT–223 POWER DISSIPATION
The power dissipation of the SOT–223 is a function of the
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
drain pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined by
of using surface mount technology. A graph of R
drain pad area is shown in Figure 17.
versus
θJA
T
R
, the maximum rated junction temperature of the die,
, the thermal resistance from the device junction to
J(max)
θJA
ambient, and the operating temperature, T . Using the values
A
160
Board Material = 0.0625
″
provided on the data sheet for the SOT–223 package, P can
D
G–10/FR–4, 2 oz Copper
T
= 25°C
A
be calculated as follows:
140
120
0.8 Watts
T
– T
A
J(max)
P
=
D
R
θJA
°
1.25 Watts*
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
1.5 Watts
100
80
the equation for an ambient temperature T of 25°C, one can
calculatethe power dissipation of the device which in this case
is 800 milliwatts.
A
*Mounted on the DPAK footprint
0.0
0.2
0.4
0.6
0.8
1.0
A, Area (square inches)
150°C – 25°C
= 800 milliwatts
P
=
D
Figure 17. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
156°C/W
The 156°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 800 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–223 package. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
stainless steel with a typical thickness of 0.008 inches. The
stencil opening size for the SOT–223 package should be the
same as the pad size on the printed circuit board, i.e., a 1:1
registration.
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass or
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6 STEP 7
VENT COOLING
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
205°
TO
219°C
200
°
C
C
170°C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
150°
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
140°C
100°C
MASS OF ASSEMBLY)
100
°
C
C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 18. Typical Solder Heating Profile
8
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
A
F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
2
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MIN
MAX
0.263
0.145
0.068
0.035
0.126
0.094
MIN
6.30
3.30
1.50
0.60
2.90
2.20
0.020
0.24
1.50
0.85
0
MAX
6.70
3.70
1.75
0.89
3.20
2.40
0.100
0.35
2.00
1.05
10
S
B
0.249
0.130
0.060
0.024
0.115
0.087
1
3
D
0.0008 0.0040
L
0.009
0.060
0.033
0
0.014
0.078
0.041
10
G
J
C
0.264
0.287
6.70
7.30
0.08 (0003)
M
H
K
STYLE 3:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
CASE 318E–04
TO–261AA
SOT–223
ISSUE H
Motorola TMOS Power MOSFET Transistor Device Data
9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MMFT1N10E/D
◊
相关型号：
MMFT2955ET1
Small Signal Field-Effect Transistor, 1.2A I(D), 60V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-261AA
MOTOROLA
MMFT2955ET1G
1200mA, 60V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-261AA, LEAD FREE, CASE 318E-04, 4 PIN
ONSEMI
MMFT2955ET3
Small Signal Field-Effect Transistor, 1.2A I(D), 60V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-261AA
MOTOROLA
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