MJD42CRLG [ONSEMI]
Complementary Power Transistors; 互补功率晶体管
| 型号： | MJD42CRLG |
| 厂家： | 
ONSEMI |
| 描述： | Complementary Power Transistors |
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MJD41C (NPN)
MJD42C (PNP)
Preferred Device
Complementary Power
Transistors
DPAK For Surface Mount Applications
http://onsemi.com
Designed for general purpose amplifier and low speed switching
applications.
SILICON
Features
POWER TRANSISTORS
6 AMPERES
100 VOLTS, 20 WATTS
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
• Straight Lead Version in Plastic Sleeves (“1” Suffix)
• Electrically Similar to Popular TIP41 and TIP42 Series
MARKING
DIAGRAMS
• Monolithic Construction With Built−in Base − Emitter Resistors
• Epoxy Meets UL 94 V−0 @ 0.125 in
• ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
4
YWW
J4xCG
2
1
• Pb−Free Packages are Available
3
DPAK
CASE 369C
STYLE 1
MAXIMUM RATINGS
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Symbol
Max
100
100
5
Unit
Vdc
Vdc
Vdc
Adc
4
V
CEO
YWW
J4xCG
V
CB
EB
V
1
2
DPAK−3
CASE 369D
STYLE 1
I
6
10
Collector Current − Continuous
− Peak
C
3
Base Current
I
2
Adc
B
P
P
20
0.16
W
W/°C
Total Power Dissipation @ T = 25°C
D
D
C
Y
= Year
Derate above 25°C
WW = Work Week
J4xC = Device Code
x = 1 or 2
Total Power Dissipation (Note 1)
W
W/°C
°C
1.75
0.014
@ T = 25°C
A
G
= Pb−Free Package
Derate above 25°C
Operating and Storage Junction
Temperature Range
T , T
J
−65 to +150
stg
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
6.25
71.4
Unit
°C/W
°C/W
Preferred devices are recommended choices for future use
and best overall value.
Thermal Resistance, Junction−to−Case
R
q
JC
Thermal Resistance, Junction−to−Ambient
(Note 1)
R
q
JA
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
January, 2006 − Rev. 6
MJD41C/D
MJD41C (NPN) MJD42C (PNP)
ELECTRICAL CHARACTERISTICS (T = 25_C unless otherwise noted)
C
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 2)
V
100
−
−
Vdc
mAdc
mAdc
mAdc
CEO(sus)
(I = 30 mAdc, I = 0)
C
B
I
50
10
0.5
Collector Cutoff Current
(V = 60 Vdc, I = 0)
CEO
CE
B
I
−
Collector Cutoff Current
CES
(V = 100 Vdc, V = 0)
CE
EB
I
−
Emitter Cutoff Current
EBO
(V = 5 Vdc, I = 0)
BE
C
ON CHARACTERISTICS (Note 2)
h
FE
−
DC Current Gain
(I = 0.3 Adc, V = 4 Vdc)
30
15
−
75
C
CE
(I = 3 Adc, V = 4 Vdc)
C
CE
V
−
1.5
2
Vdc
Vdc
Collector−Emitter Saturation Voltage
(I = 6 Adc, I = 600 mAdc)
CE(sat)
C
B
V
−
Base−Emitter On Voltage
(I = 6 Adc, V = 4 Vdc)
BE(on)
C
CE
DYNAMIC CHARACTERISTICS
f
3
−
−
MHz
−
Current Gain − Bandwidth Product (Note 3)
T
(I = 500 mAdc, V = 10 Vdc, f = 1 MHz)
test
C
CE
h
20
Small−Signal Current Gain
(I = 0.5 Adc, V = 10 Vdc, f = 1 kHz)
fe
C
CE
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
3. f = ⎪h ⎪• f
.
test
T
fe
ORDERING INFORMATION
Device
†
Package Type
Package
Shipping
MJD41CRL
DPAK
1800 / Tape & Reel
2500 / Tape & Reel
MJD41CRLG
DPAK
(Pb−Free)
MJD41CT4
DPAK
369C
MJD41CT4G
DPAK
(Pb−Free)
MJD42C
DPAK
MJD42CG
DPAK
(Pb−Free)
75 Units / Rail
MJD42C1
DPAK−3
369D
369C
MJD42C1G
DPAK−3
(Pb−Free)
MJD42CRL
DPAK
1800 / Tape & Reel
2500 / Tape & Reel
MJD42CRLG
DPAK
(Pb−Free)
MJD42CT4
DPAK
MJD42CT4G
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
MJD41C (NPN) MJD42C (PNP)
TYPICAL CHARACTERISTICS
T
T
C
V
CC
+ꢀ30 V
A
2.5 25
R
C
2
20
25 ms
SCOPE
+11 V
R
B
0
1.5 15
T
C
D
1
51
−ꢀ9 V
T
A
SURFACE MOUNT
1
10
t , t ≤ 10 ns
r
f
DUTY CYCLE = 1%
−ꢀ4 V
0.5
0
5
0
R and R VARIED TO OBTAIN DESIRED CURRENT LEVELS
ꢃD MUST BE FAST RECOVERY TYPE, e.g.:
B
C
1
ꢃꢃMSB5300 USED ABOVE I ≈ 100 mA
B
ꢃꢃMSD6100 USED BELOW I ≈ 100 mA
B
REVERSE ALL POLARITIES FOR PNP.
25
50
75
100
125
150
T, TEMPERATURE (°C)
Figure 1. Power Derating
Figure 2. Switching Time Test Circuit
2
1
500
T = 25°C
J
300
200
V
= 2 V
CE
V = 30 V
CC
I /I = 10
T = 150°C
J
C B
0.7
0.5
100
70
25°C
0.3
0.2
t
r
50
30
20
0.1
−ꢀ55°C
0.07
t @ V
d
≈ 5 V
BE(off)
0.05
10
7
0.03
0.02
5
0.06
0.2 0.3 0.4 0.6
1
2
4
6
0.06
0.2
0.4 0.6
1
2
4
6
0.1
0.1
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (AMP)
C
Figure 3. DC Current Gain
Figure 4. Turn−On Time
5
2
1.6
1.2
0.8
0.4
0
T = 25°C
J
T = 25°C
3
2
J
V
I /I = 10
= 30 V
CC
C B
t
s
I = I
B1 B2
1
0.7
0.5
V
@ I /I = 10
C B
CE(sat)
0.3
0.2
V
@ V = 4 V
CE
BE
t
f
0.1
0.07
0.05
V
@ I /I = 10
C B
BE(sat)
0.06
0.2 0.3 0.4 0.6
1
2
3
4
6
0.06
0.2
0.4 0.6
1
2
4
6
0.1
0.1
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (AMP)
C
Figure 5. “On” Voltages
Figure 6. Turn−Off Time
http://onsemi.com
3
MJD41C (NPN) MJD42C (PNP)
2
300
T = 25°C
J
T = 25°C
J
200
1.6
I
C
= 1 A
2.5 A
5 A
C
C
ib
1.2
0.8
0.4
0
100
70
ob
50
30
0.5
1
2
3
5
10
20 30
50
10
20 30
50
100
200 300 500
1000
V , REVERSE VOLTAGE (VOLTS)
R
I , BASE CURRENT (mA)
B
Figure 8. Capacitance
Figure 7. Collector Saturation Region
1
0.7
D = 0.5
0.2
0.5
0.3
0.2
P
(pk)
R
R
= r(t) R
q
JC
q
q
JC(t)
0.1
= 6.25°C/W MAX
JC
0.1
0.07
0.05
0.05
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
0.02
t
2
1
T
− T = P q
C (pk) JC(t)
J(pk)
0.03
0.02
DUTY CYCLE, D = t /t
0.01
1 2
SINGLE PULSE
0.01
0.01
0.02 0.03 0.05
0.1
0.2 0.3 0.5
1
2
3
5
10
20 30
50
100
200 300 500
1000
t, TIME (ms)
Figure 9. Thermal Response
10
5
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
100ꢂms
500ꢂms
3
2
breakdown. Safe operating area curves indicate I − V
C
CE
1ꢂms
dc
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
5ꢂms
1
0.5
0.3
WIRE BOND LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
The data of Figure 10 is based on T
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided
= 150_C; T is
J(pk)
C
CURVES APPLY BELOW RATED V
CEO
0.1
0.05
0.03
T
v 150_C. T
may be calculated from the data in
J(pk)
J(pk)
T
= 25°C SINGLE PULSE
C
Figure 9. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
T = 150°C
J
MJD41C, 42C
0.01
1
2
3
5
7
10
20 30
50 70 100
V
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
CE
Figure 10. Maximum Forward Bias
Safe Operating Area
http://onsemi.com
4
MJD41C (NPN) MJD42C (PNP)
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
NOTES:
SEATING
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
PLANE
C
2. CONTROLLING DIMENSION: INCH.
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
MJD41C (NPN) MJD42C (PNP)
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
NOTES:
C
B
R
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
4
2
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 1:
PIN 1. BASE
G
M
T
0.13 (0.005)
2. COLLECTOR
3. EMITTER
4. COLLECTOR
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MJD41C/D
相关型号：
MJD44
General Purpose Power and Switching Such as Output or Driver Stages in Applications D-PAK for Surface Mount Applications
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明