MC74VHCT138ADR2G [ONSEMI]
3−to−8 Line Decoder; 3至8行译码器
| 型号： | MC74VHCT138ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3−to−8 Line Decoder |
| 文件： | 总7页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT138A
3−to−8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3−to−8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 − A2)
determine which one of the outputs (Y0 − Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because they
have full 5.0 V CMOS level output swings.
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MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
VHCT138AG
AWLYWW
1
The VHCT138A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
16
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
VHCT
138A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
Features
• High Speed: t = 7.6 ns (Typ) at V = 5.0 V
PD
CC
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
WW, W = Work Week
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
• Designed for 4.5 V to 5.5 V Operating Range
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
PIN ASSIGNMENT
• ESD Performance:
A0
A1
1
2
16
15
V
CC
Human Body Model > 2000 V;
Machine Model > 200 V
Y0
Y1
Y2
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• Pb−Free Packages are Available*
3
4
5
6
14
13
A2
E1
E2
E3
12
11
Y3
Y4
7
8
10
9
Y7
Y5
Y6
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
January, 2006 − Rev. 3
MC74VHCT138A/D
MC74VHCT138A
FUNCTION TABLE
LOGIC DIAGRAM
Inputs
Outputs
15
14
13
12
Y0
1
2
3
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A0
A1
A2
Y1
Y2
Y3
SELECT
INPUTS
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ACTIVE−LOW
OUTPUTS
11
10
Y4
Y5
Y6
Y7
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
9
7
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
L
H
H
H
L
6
5
E3
E2
E1
H
H
H
ENABLE
INPUTS
4
H
H
H = high level (steady state); L = low level (steady state);
X = don’t care
EXPANDED LOGIC DIAGRAM
15
Y0
14
13
Y1
Y2
1
2
3
A0
A1
A2
12
11
Y3
Y4
10
Y5
5
4
E2
E1
9
7
Y6
Y7
6
E3
IEC LOGIC DIAGRAM
BIN/OCT
DMUX
1
2
3
1
15
14
13
12
11
10
9
15
14
13
12
11
10
9
A0
Y0
Y1
Y2
Y3
A0
A1
A2
Y0
1
2
4
0
1
2
3
0
0
1
2
3
0
7
2
3
A1
A2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G
2
Y4
Y5
Y6
Y7
&
&
4
5
4
5
6
5
4
6
5
4
E3
E2
E1
E3
E2
E1
EN
6
7
6
7
7
7
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2
MC74VHCT138A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
– 0.5 to + 7.0
V
CC
V
in
– 0.5 to + 7.0
V
V
V
out
V
= 0
CC
– 0.5 to + 7.0
High or Low State – 0.5 to V + 0.5
CC
cuit. For proper operation, V and
I
Input Diode Current
− 20
mA
mA
mA
mA
mW
in
IK
V
out
should be constrained to the
I
Output Diode Current (V
< GND; V
> V )
CC
20
25
75
OK
OUT
OUT
range GND v (V or V ) v V
.
CC
in
out
Unused inputs must always be
tied to an appropriate logic voltage
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
out
I
CC
CC
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
P
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
D
T
Storage Temperature
– 65 to + 150
_C
stg
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
3.0
0
Max
5.5
5.5
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
in
V
V
out
V
= 0
CC
0
0
V
High or Low State
V
CC
T
Operating Temperature
Input Rise and Fall Time
− 55
0
+ 125
20
_C
ns/V
A
t , t
r
V =5.0V 0.5V
CC
f
The q of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table
JA
and figure below.
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 1. Failure Rate vs. Time
Junction Temperature
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3
MC74VHCT138A
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
Minimum High−Level Input
Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
IH
V
Maximum Low−Level Input
Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IL
V
Minimum High−Level Output
Voltage
V
= V or V
= −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
OH
IN
IH
IL
IL
I
OH
V
= V or V
IH IL
IN
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
Maximum Low−Level Output
Voltage
V
= V or V
= 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
OL
IN
IH
IL
IL
I
OL
V
= V or V
IH IL
IN
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input Leakage Current
V
V
= 5.5 V or GND
0 to 5.5
5.5
0.1
4.0
1.0
1.0
mA
mA
IN
IN
I
Maximum Quiescent Supply
Current
= V or GND
40.0
40.0
CC
IN
CC
I
Quiescent Supply Current
Output Leakage Current
V
V
= 3.4 V
5.5
0.0
1.35
0.5
1.50
5.0
1.50
5.0
mA
CCT
IN
I
= 5.5 V
mA
OPD
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
Typ
T
= ≤ 85°C
T ≤ 125°C
A
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
C = 15pF
Unit
t
t
t
,
Maximum Propagation Delay,
Input A to Y
V
V
V
V
V
V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
9.5
10.8 15.5
14.5
1.0
1.0
16.0
17.0
1.0
1.0
16.0
17.0
ns
PLH
t
CC
CC
CC
CC
CC
CC
L
C = 50pF
L
PHL
C = 15pF
7.6
8.1
10.4
11.4
1.0
1.0
12.0
13.0
1.0
1.0
12.0
13.0
L
C = 50pF
L
,
Maximum Propagation Delay,
Input E3 to Y
C = 15pF
9.7
9.5
13.0
14.0
1.0
1.0
14.5
15.5
1.0
1.0
14.5
15.5
ns
ns
PLH
L
t
C = 50pF
L
PHL
C = 15pF
6.6
7.1
9.1
10.1
1.0
1.0
10.5
11.5
1.0
1.0
10.5
11.5
L
C = 50pF
L
,
Maximum Propagation Delay,
Input E1 or E2 to Y
C = 15pF
10.1 14.0
9.9
1.0
1.0
15.5
16.5
1.0
1.0
15.5
16.5
PLH
L
t
C = 50pF
L
15.0
PHL
C = 15pF
7.0
7.5
9.6
10.6
1.0
1.0
11.0
12.0
1.0
1.0
11.0
12.0
L
C = 50pF
L
C
Maximum Input Capacitance
4
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0V
CC
49
C
PD
Power Dissipation Capacitance (Note 1)
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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4
MC74VHCT138A
SWITCHING WAVEFORMS
VALID
VALID
3V
3V
E3
1.5V
A
Y
1.5V
GND
GND
t
t
PLH
PHL
t
t
PHL
PLH
V
V
OH
OL
V
V
OH
OL
Y
1.5V
1.5V
Figure 2.
Figure 3.
3V
E2 or E1
1.5V
GND
t
t
PLH
PHL
V
V
OH
OL
Y
1.5V
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT138ADR2
MC74VHCT138ADR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74VHCT138ADTR2
MC74VHCT138ADTRG
TSSOP−16*
TSSOP−16*
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74VHCT138A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
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6
MC74VHCT138A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
F
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
ON Semiconductor and
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHCT138A/D
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ONSEMI
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