MC74VHCT138AMR2 [ONSEMI]
AHCT/VHCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, EIAJ, SOIC-16;
| 型号： | MC74VHCT138AMR2 |
| 厂家： | 
ONSEMI |
| 描述： | AHCT/VHCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, EIAJ, SOIC-16 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC74VHCT138A is an advanced high speed CMOS 3–to–8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
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MARKING DIAGRAMS
16
9
VHCT138A
AWLYYWW
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V, because they
have full 5V CMOS level output swings.
1
SOIC–16
D SUFFIX
CASE 751B
8
9
16
The VHCT138A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage.
VHCT
138A
The output structures also provide protection when V
= 0V. These
CC
AWLYWW
TSSOP–16
DT SUFFIX
CASE 948F
input and output structures help prevent device destruction caused by
supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc.
1
8
• High Speed: t
= 7.6ns (Typ) at V
= 5V
16
9
PD
• Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
VHCT138A
ALYW
• TTL–Compatible Inputs: V = 0.8V; V = 2.0V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
SOIC EIAJ–16
M SUFFIX
CASE 966
IL IH
1
8
• Designed for 4.5V to 5.5V Operating Range
A
= Assembly Location
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
WL = Wafer Lot
YY = Year
WW = Work Week
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
A
L
Y
= Assembly Location
= Wafer Lot
= Year
Y
W = Work Week
PIN ASSIGNMENT
A0
A1
1
2
16
15
V
ORDERING INFORMATION
CC
Y0
Y1
Y2
Device
Package
Shipping
MC74VHCT138AD
MC74VHCT138ADR2
MC74VHCT138ADT
SOIC–16 48 Units/Rail
SOIC–16 2500 Units/Reel
TSSOP–16 96 Units/Rail
3
4
5
6
14
13
A2
E1
E2
E3
12
11
Y3
Y4
MC74VHCT138ADTR2 TSSOP–16 2500 Units/Reel
SOIC
MC74VHCT138AM
48 Units/Rail
EIAJ–16
7
8
10
9
SOIC
EIAJ–16
Y7
Y5
Y6
MC74VHCT138AMEL
2000 Units/Reel
GND
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
May, 2000 – Rev. 1
MC74VHCT138A/D
MC74VHCT138A
FUNCTION TABLE
LOGIC DIAGRAM
Inputs
Outputs
15
14
13
12
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
3
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A0
A1
A2
SELECT
INPUTS
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ACTIVE–LOW
OUTPUTS
11
10
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
9
7
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
6
5
4
E3
E2
E1
ENABLE
INPUTS
H
H
H = high level (steady state); L = low level (steady state);
X = don’t care
EXPANDED LOGIC DIAGRAM
15
Y0
14
13
Y1
Y2
1
2
3
A0
A1
A2
12
11
Y3
Y4
10
Y5
5
4
E2
E1
9
7
Y6
Y7
6
E3
IEC LOGIC DIAGRAM
BIN/OCT
DMUX
0
1
2
3
1
15
14
13
12
11
10
9
15
14
13
12
11
10
9
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
4
0
1
2
3
0
0
1
2
3
2
3
G
7
2
&
&
4
5
4
5
6
5
4
6
5
4
E3
E2
E1
E3
E2
E1
EN
6
7
6
7
7
7
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2
MC74VHCT138A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
out
V
= 0
– 0.5 to + 7.0
V
CC
High or Low State – 0.5 to V + 0.5
CC
– 20
cuit. For proper operation, V and
in
I
IK
Input Diode Current
mA
mA
mA
mA
mW
V
should be constrained to the
out
I
Output Diode Current (V
< GND; V
OUT
> V )
CC
± 20
± 25
± 75
OK
OUT
DC Output Current, per Pin
DC Supply Current, V and GND Pins
range GND (V or V
)
V
CC
.
in out
Unused inputs must always be
tied to an appropriate logic voltage
I
out
I
CC
CC
level (e.g., either GND or V
).
CC
Unused outputs must be left open.
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
T
stg
Storage Temperature
– 65 to + 150
C
* Absolutemaximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute–maximum–rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
3.0
0
Max
5.5
5.5
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
V
V
out
V
= 0
0
0
V
CC
High or Low State
V
CC
T
Operating Temperature
Input Rise and Fall Time
– 55 + 125
20
C
A
t , t
r f
V
CC
=5.0V ±0.5V
0
ns/V
The
figure below.
of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
JA
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 1. Failure Rate vs. Time
Junction Temperature
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3
MC74VHCT138A
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
≤ 85°C
T ≤ 125°C
A
A
V
(V)
CC
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
Max
Min
Max
V
IH
Minimum High–Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low–Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High–Level
Output Voltage
V
= V or V
IH
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
IL
IL
I
= –50 µ
OH
V
IN
= V or V
IH
IL
V
= V or V
IH
= –4 mA
= –8 mA
IN
OH
OH
I
I
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low–Level
Output Voltage
V
= V or V
IH
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
IL
IL
I
= 50 µA
OL
V
IN
= V or V
IH
IL
V
= V or V
IH
= 4 mA
= 8 mA
IN
OL
OL
I
I
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
± 0.1
± 1.0
40.0
1.50
5.0
± 1.0
40.0
1.50
5.0
µA
µA
mA
µA
IN
IN
I
Maximum Quiescent
Supply Current
V
V
V
= V
or GND
5.5
5.5
0.0
4.0
CC
IN
CC
I
Quiescent Supply
Current
= 3.4 V
1.35
0.5
CCT
IN
I
Output Leakage
Current
= 5.5 V
OUT
OPD
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= ≤ 85°C
T ≤ 125°C
A
Symbol
Parameter
Maximum
Propagation Delay,
Input A to Y
Test Conditions
Unit
Min
Typ
Max
Min
Max
Min
Max
t
t
t
,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
C
C
= 15pF
= 50pF
9.5
10.8
14.5
15.5
1.0
1.0
16.0
17.0
1.0
1.0
16.0
17.0
ns
PLH
L
L
t
PHL
C
C
= 15pF
= 50pF
7.6
8.1
10.4
11.4
1.0
1.0
12.0
13.0
1.0
1.0
12.0
13.0
L
L
,
Maximum
Propagation Delay,
Input E3 to Y
C
C
= 15pF
= 50pF
9.7
9.5
13.0
14.0
1.0
1.0
14.5
15.5
1.0
1.0
14.5
15.5
ns
ns
PLH
t
L
L
PHL
C
C
= 15pF
= 50pF
6.6
7.1
9.1
10.1
1.0
1.0
10.5
11.5
1.0
1.0
10.5
11.5
L
L
,
Maximum
Propagation Delay,
Input E1 or E2 to Y
C
C
= 15pF
= 50pF
10.1
9.9
14.0
15.0
1.0
1.0
15.5
16.5
1.0
1.0
15.5
16.5
PLH
L
L
t
PHL
C
C
= 15pF
= 50pF
7.0
7.5
9.6
10.6
1.0
1.0
11.0
12.0
1.0
1.0
11.0
12.0
L
L
C
Maximum Input
Capacitance
4
10
10
10
pF
IN
Typical @ 25°C, V
= 5.0V
CC
C
Power Dissipation Capacitance (Note 1.)
pF
49
PD
1. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Averageoperatingcurrentcanbeobtainedbytheequation:I
power consumption; P = C
=C isusedtodeterminetheno–loaddynamic
V
f
+I .C
CC(OPR)
CC
PD CC in CC PD
2
V
CC
f + I
in CC
V
.
D
PD
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4
MC74VHCT138A
SWITCHING WAVEFORMS
VALID
1.5V
VALID
3V
3V
E3
1.5V
A
GND
GND
t
t
PLH
PHL
t
t
PHL
PLH
V
OH
V
OH
Y
1.5V
Y
1.5V
V
OL
V
OL
Figure 2.
Figure 3.
3V
GND
E2 or E1
1.5V
t
t
PLH
PHL
V
OH
Y
1.5V
V
OL
Figure 4.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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5
MC74VHCT138A
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
S
0.15 (0.006) T U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
–V–
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
F
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
H
DETAIL E
SEATING
PLANE
–T–
D
G
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6
MC74VHCT138A
PACKAGE DIMENSIONS
SOIC EIAJ–16
M SUFFIX
CASE 966–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
A
–––
0.05
0.35
0.18
9.90
5.10
2.05
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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7
MC74VHCT138A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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