MC74VHC32_14 [ONSEMI]
Quad 2-Input OR Gate;
ONSEMI 
MC74VHC32
Quad 2-Input OR Gate
The MC74VHC32 is an advanced high speed CMOS 2−input OR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
http://onsemi.com
MARKING
DIAGRAMS
Features
14
14
• High Speed: t = 3.8 ns (Typ) at V = 5.0 V
PD
CC
1
VHC32G
AWLYWW
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
CC
A
SOIC−14
D SUFFIX
CASE 751A
• High Noise Immunity: V
= V
= 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
1
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
14
14
OLP
VHC
32
ALYW ꢀ
ꢀ
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
1
TSSOP
• ESD Performance:
1
DT SUFFIX
CASE 948G
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 48 FETs or 12 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
A
= Assembly Location
= Year
WL, L = Wafer Lot
Y
WW, W = Work Week
G or ꢀ = Pb−Free Package
1
A1
3
Y1
2
B1
4
(Note: Microdot may be in either location)
A2
6
Y2
5
B2
FUNCTION TABLE
Y = A+B
9
Inputs
Output
A3
8
Y3
10
A
B
Y
B3
12
L
L
L
H
L
L
H
H
H
A4
11
Y4
13
H
H
B4
H
Figure 1. Logic Diagram
V
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
CC
14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2 GND
(Top View)
Figure 2. Pinout: 14−Lead Packages
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 7
MC74VHC32/D
MC74VHC32
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
–0.5 to V +0.5
V
out
IK
CC
I
−20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
50
CC
†
†
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Package
TSSOP Package
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
–65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating − SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
V
in
5.5
V
V
DC Output Voltage
Operating Temperature
Input Rise and Fall Time
0
V
V
out
CC
T
−40
+125
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −40°C to 125°C
A
V
CC
V
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
OH
V
in
= V or V
IH
IL
3.0
4.5
2.58
3.94
2.48
3.80
I
I
= −4.0 mA
= −8.0 mA
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
OL
V
in
= V or V
IH
IL
3.0
4.5
0.36
0.36
0.44
0.44
I
OL
I
OL
= 4.0 mA
= 8.0 mA
I
Maximum Input
Leakage Current
V
V
= 5.5 V or GND
0 to 5.5
5.5
0.1
2.0
1.0
mA
mA
in
in
I
Maximum Quiescent
Supply Current
= V or GND
20.0
CC
in
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
http://onsemi.com
2
MC74VHC32
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T = −40°C to 125°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Unit
t
,
Maximum Propagation
Delay,
A or B to Y
V
V
5.5
8.0
7.9
11.4
1.0
1.0
9.5
13.0
ns
PLH
CC
L
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
CC
L
C = 50 pF
L
C
Maximum Input Capacitance
4
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
14
C
Power Dissipation Capacitance (Note 1)
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Symbol
Characteristic
Unit
V
V
OLP
Quiet Output Maximum Dynamic V
0.8
−0.8
3.5
OL
V
OLV
Quiet Output Minimum Dynamic V
−0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
TEST
POINT
V
CC
A or B
50%
OUTPUT
DEVICE
UNDER
TEST
GND
C *
L
t
t
PLH
PHL
Y
50% V
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
http://onsemi.com
3
MC74VHC32
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC32DR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
96 Units / Rail
MC74VHC32DTG
TSSOP−14
(Pb−Free)
MC74VHC32DTR2G
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
4
MC74VHC32
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C
A
DETAIL A
h
X 45ꢁ
A
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
M
A1
e
M
0 ꢁ
7ꢁ
0 ꢁ
7ꢁ
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
MC74VHC32
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0 ꢁ
8 ꢁ
0 ꢁ
8 ꢁ
SEATING
−T−
H
G
DETAIL E
D
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74VHC32/D
相关型号：
©2020 ICPDF网 联系我们和版权申明