MC74VHC3540DW [ONSEMI]
Octal Bus Buffer Inverting; 八路总线缓冲器反相
| 型号： | MC74VHC3540DW |
| 厂家： | 
ONSEMI |
| 描述： | Octal Bus Buffer Inverting |
| 文件： | 总8页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
MC74VHC540
Octal Bus Buffer
Inverting
The MC74VHC540 is an advanced high speed CMOS inverting
octal bus buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The MC74VHC540 features inputs and outputs on opposite sides of
the package and two AND--ed active-low output enables. When either
OE1 or OE2 are high, the terminal outputs are in the high impedance
state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
DW SUFFIX
20--LEAD SOIC WIDE PACKAGE
CASE 751D--05
DT SUFFIX
20--LEAD TSSOP PACKAGE
CASE 948E--02
• High Speed: tPD = 3.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
M SUFFIX
20--LEAD SOIC EIAJ PACKAGE
CASE 967--01
ORDERING INFORMATION
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC WIDE
TSSOP
SOIC EIAJ
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 124 FETs or 31 Equivalent Gates
PIN ASSIGNMENT
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
OE1
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
V
CC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
GND 10
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 -- Rev. 3
MC74VHC540/D
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DATA
INPUTS
INVERTING
OUTPUTS
A8
1
OE1
OUTPUT
ENABLES
19
OE2
http://onsemi.com
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high--impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
-- 2 0
± 20
± 25
± 75
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND ≤ (V or V ) ≤ V .
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V ).
P
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
D
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
_C
*
Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute--maximum--rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
in
5.5
V
V
out
0
V
V
CC
T
Operating Temperature, All Package Types
-- 4 0
+ 85
_C
ns/V
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
V
= 3.3V ±0.3V
=5.0V ±0.5V
0
0
100
20
f
CC
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = -- 40 to 85°C
A
V
CC
Min
1.50
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
Minimum High--Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
IH
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low--Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
Minimum High--Level
Output Voltage
V
= V or V
= -- 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
OH
in
IH
IL
IL
I
OH
V
in
= V or V
IH
I
I
= -- 4mA
= -- 8mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
Maximum Low--Level
Output Voltage
V
= V or V
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = -- 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 5.5
± 0.1
± 1.0
μA
in
in
I
Maximum
Three--State Leakage
Current
= V or V
IH
5.5
5.5
± 0.25
± 2.5
μA
μA
OZ
in
IL
V
= V or GND
out CC
I
Maximum Quiescent
Supply Current
V
in
= V or GND
4.0
40.0
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= -- 40 to 85°C
Min
Typ
Max
Min
1.0
Max
Symbol
Parameter
Test Conditions
Unit
t
,
Maximum Propagation Delay,
A to Y
(Figures 1 and 3)
V
V
V
= 3.3 ± 0.3V
C
L
C
L
= 15pF
= 50pF
4.8
7.3
7.0
10.5
8.5
12.0
ns
PLH
CC
CC
CC
t
1.0
PHL
= 5.0 ± 0.5V
C
L
C
L
= 15pF
= 50pF
3.7
5.2
5.0
7.0
1.0
1.0
6.0
8.0
t
,
Output Enable TIme,
OEn to Y
(Figures 2 and 4)
= 3.3 ± 0.3V
= 1kΩ
C
L
C
L
= 15pF
= 50pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
ns
PZL
t
R
PZH
L
V
R
= 5.0 ± 0.5V
= 1kΩ
C
L
C
L
= 15pF
= 50pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
CC
L
t
,
Output Disable Time,
OEn to Y
(Figures 2 and 4)
V
R
= 3.3 ± 0.3V
= 1kΩ
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
11.2
15.4
8.8
1.5
1.0
10
1.0
17.5
10.0
PLZ
CC
L
L
L
L
t
PHZ
L
V
R
= 5.0 ± 0.5V
= 1kΩ
6.0
1.0
CC
L
t
,
Output to Output Skew
V
= 3.3 ± 0.3V
(Note 1)
ns
ns
OSLH
CC
t
OSHL
V
= 5.0 ± 0.5V
CC
(Note 1)
C
in
Maximum Input Capacitance
4
6
10
pF
pF
C
out
Maximum Three--State Output
Capacitance (Output in High
Impedance State)
Typical @ 25°C, V = 5.0V
CC
17
C
PD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. t = |t -- t
|, t
= |t
-- t
|.
PHLn
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ¯ V ¯ f + I /8 (per bit). C is used to determine the no--load
CC(OPR
CC
PD CC in CC PD
2
dynamic power consumption; P = C ¯ V
¯ f + I ¯ V
.
D
PD
CC
in
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.9
1.2
-- 1 . 2
3.5
OLP
OL
Quiet Output Minimum Dynamic V
-- 0 . 9
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
1.5
V
ILD
http://onsemi.com
4
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
50%
50%
V
CC
GND
A
50%
t
t
PLZ
PZL
HIGH
IMPEDANCE
GND
t
t
PLH
PHL
50% V
t
Y
Y
CC
V
V
+0.3V
--0.3V
OL
t
50% V
PZH
PHZ
CC
Y
OH
50% V
CC
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
CC
1kΩ
OUTPUT
OUTPUT
TESTING t AND t
.
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
INPUT EQUIVALENT CIRCUIT
INPUT
http://onsemi.com
5
OUTLINE DIMENSIONS
DW SUFFIX
SOIC
CASE 751D--05
ISSUE F
D
A
θ
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
20
11
10
E
B
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
T
0.25
A
B
e
H
h
L
θ
1.27 BSC
A
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
_
_
18X
e
A1
C
T
http://onsemi.com
6
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP
CASE 948E--02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
K
K1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE --W--.
J
J1
B
L
-- U --
PIN 1
IDENT
SECTION N--N
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
M
A
-- V --
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
-- -- --
6.60 0.252
4.50 0.169
1.20
N
-- -- --
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
-- W --
C
6.40 BSC
G
D
M
0
8
0
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
-- T -- SEATING
PLANE
http://onsemi.com
7
OUTLINE DIMENSIONS
M SUFFIX
SOIC EIAJ
CASE 967--01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
20
11
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
e
A
DIM MIN
MAX
2.05
0.20 0.002
0.50 0.014
0.27 0.007
12.80 0.486
5.45 0.201
MIN
-- -- --
MAX
0 . 0 8 1
0.008
0.020
0.011
0.504
0.215
c
A
1
b
c
-- -- --
0.05
0.35
0.18
12.35
5.10
A
D
E
e
A
1
b
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
E
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
L
L
E
M
Q
Z
0
0.70
-- -- --
10
0
10
0.035
0 . 0 3 2
_
_
_
_
0.90 0.028
0 . 8 1 -- -- --
1
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800--282--9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082--1312 USA
Phone: 480--829--7710 or 800--344--3860 Toll Free USA/Canada
Fax: 480--829--7709 or 800--344--3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2--9--1 Kamimeguro, Meguro--ku, Tokyo, Japan 153--0051
Phone: 81--3--5773--3850
For additional information, please contact your
local Sales Representative.
MC74VHC540/D
相关型号：
MC74VHC373DWR2
Bus Driver, AHC/VHC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SOIC-20
MOTOROLA
©2020 ICPDF网 联系我们和版权申明