MC74LVX74DR2G [ONSEMI]
Dual D−Type Flip−Flop with Set and Clear; 双D型触发器带设置和清除
| 型号： | MC74LVX74DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual D−Type Flip−Flop with Set and Clear |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX74
Dual D−Type Flip−Flop
with Set and Clear
With 5.0 V−Tolerant Inputs
The MC74LVX74 is an advanced high speed CMOS D−type
flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the
interface of 5.0 V systems to 3.0 V systems.
The signal level applied to the D input is transferred to O output
during the positive going transition of the Clock pulse.
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MARKING
DIAGRAMS
Clear (CD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
14
1
SOIC−14
D SUFFIX
CASE 751A
LVX74G
AWLYWW
Features
1
• High Speed: f
= 145 MHz (Typ) at V = 3.3 V
CC
max
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
14
• Power Down Protection Provided on Inputs
LVX
74
TSSOP−14
DT SUFFIX
CASE 948G
• Balanced Propagation Delays
ALYW G
1
• Low Noise: V
= 0.5 V (Max)
OLP
G
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
1
14
• ESD Performance:
SOEIAJ−14
M SUFFIX
CASE 965
Human Body Model > 2000 V;
Machine Model > 200 V
LVX74
ALYWG
1
• Pb−Free Packages are Available*
1
A
= Assembly Location
WL, L = Wafer Lot
= Year
V
CD2 D2 CP2 SD2 O2
13 12 11 10 9
O2
8
CC
Y
14
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN NAMES
Pins
Function
1
2
3
4
5
6
7
CP1, CP2
D1, D2
Clock Pulse Inputs
Data Inputs
CD1 D1 CP1 SD1 O1
O1 GND
Figure 1. 14−Lead Pinout
CD1, CD2
SD1, SD2
On, On
Direct Clear Inputs
Direct Set Inputs
Outputs
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 3
MC74LVX74/D
MC74LVX74
4
10
SD1
SD2
SD
CD
SD
CD
2
3
12
11
5
6
9
8
D1
D
D2
D
O1
O1
O2
O2
Q
Q
Q
Q
CP1
CP
CP2
CD2
CP
1
13
CD1
Figure 2. Logic Diagram
INPUTS
OUTPUTS
SDn
CDn
CPn
Dn
On
On
OPERATING MODE
L
H
H
L
X
X
X
X
H
L
L
H
Asynchronous Set
Asynchronous Clear
L
L
X
X
H
H
Undetermined
Load and Read Register
Hold
H
H
H
H
↑
↑
h
l
H
L
L
H
H
H
↑
X
NC
NC
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; L = Low Voltage Level; l =
Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; NC = No Change; X = High or Low Voltage Level or
Transitions are Acceptable; ↑ = Low−to−High Transition; ↑ = Not a Low−to−High Transition; For I Reasons DO NOT FLOAT Inputs
CC
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
V
in
V
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
–0.5 to V +0.5
V
out
IK
CC
I
−20
mA
mA
mA
mA
mW
_C
I
20
25
OK
I
out
CC
I
DC Supply Current, V and GND Pins
50
CC
P
Power Dissipation
180
D
T
stg
Storage Temperature
–65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time
−40
0
+85
100
_C
ns/V
A
Dt/DV
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2
MC74LVX74
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
V
OH
High−Level Output Voltage
(V = V or V )
I
I
I
= −50mA
= −50mA
= −4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
in
IH
IL
V
I
Low−Level Output Voltage
(V = V or V )
I
OL
I
OL
I
OL
= 50mA
= 50mA
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
OL
in
IH
IL
Input Leakage Current
V
V
= 5.5V or GND
3.6
3.6
0.1
2.0
1.0
mA
mA
in
in
I
Quiescent Supply Current
= V or GND
20.0
CC
in
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Propagation Delay
Test Conditions
Unit
t
,
V
V
V
V
V
V
= 2.7V
C = 15pF
C = 50pF
L
7.3
9.8
15.0
18.5
1.0
1.0
18.5
22.0
ns
PLH
CC
CC
CC
CC
CC
CC
L
t
CP to O or O
PHL
= 3.3 0.3V
= 2.7V
C = 15pF
C = 50pF
L
5.7
8.2
9.7
13.2
1.0
1.0
11.5
15.0
L
t
,
Propagation Delay
SD or CD to O or O
C = 15pF
8.4
10.9
15.6
19.1
1.0
1.0
18.5
22.0
ns
MHz
ns
PLH
L
t
C = 50pF
L
PHL
= 3.3 0.3V
= 2.7V
C = 15pF
C = 50pF
L
6.6
9.1
10.1
13.6
1.0
1.0
12.0
15.5
L
f
Maximum Clock Frequency
(50% Duty Cycle)
C = 15pF
55
45
135
60
50
40
max
L
C = 50pF
L
= 3.3 0.3V
C = 15pF
C = 50pF
L
95
60
145
85
80
50
L
t
t
Output−to−Output Skew
(Note 1)
V
CC
V
CC
= 2.7V
= 3.3 0.3V
C = 50pF
C = 50pF
L
1.5
1.5
1.5
1.5
OSHL
OSLH
L
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
Guaranteed Limit
V
CC
T
A
= 25_C
8.5
6.0
T
A
= − 40 to 85_C
V
Symbol
Parameter
Minimum Pulse Width, CP
Unit
t
w
2.7V
3.3V 0.3
10.0
7.0
ns
t
Minimum Pulse Width, CD or SD
Minimum Setup Time, D to CP
2.7V
3.3V 0.3
8.5
6.0
10.0
7.0
ns
ns
ns
ns
w
t
su
2.7V
3.3V 0.3
8.0
5.5
9.5
6.5
t
Minimum Hold Time, D to CP
2.7V
3.3V 0.3
0.5
0.5
0.5
0.5
h
t
Minimum Recovery Time, SD or CD to CP
2.7V
3.3V 0.3
6.5
5.0
7.5
5.0
rec
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3
MC74LVX74
CAPACITIVE CHARACTERISTICS
Symbol
T
A
= 25°C
Typ
4
T = − 40 to 85°C
A
Min
Max
Min
Max
Parameter
Unit
Cin
Input Capacitance
Power Dissipation Capacitance (Note 2)
10
10
pF
C
25
pF
PD
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /2 (per flip−flop). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 3.3V, Measured in SOIC Package)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Symbol
Characteristic
Unit
V
Quiet Output Maximum Dynamic V
0.5
−0.5
2.0
V
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
V
V
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
ILD
0.8
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX74DR2
SOIC−14
2500 Tape & Reel
MC74LVX74DR2G
SOIC−14
(Pb−Free)
MC74LVX74DT
MC74LVX74DTG
MC74LVX74DTR2
MC74LVX74DTR2G
MC74LVX74M
TSSOP−14*
TSSOP−14*
TSSOP−14*
TSSOP−14*
SOEIAJ−14
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
MC74LVX74MG
SOEIAJ−14
(Pb−Free)
MC74LVX74MEL
SOEIAJ−14
2000 Tape & Reel
MC74LVX74MELG
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74LVX74
SWITCHING WAVEFORMS
t
w
V
CC
50%
SD or CD
GND
t
PHL
V
CC
CP
50%
50% V
O or O
CC
GND
t
w
t
PLH
1/f
max
50% V
CC
t
t
PHL
O or O
CP
PLH
t
rec
50% V
CC
V
CC
O or O
50%
GND
Figure 3.
Figure 4.
VALID
V
CC
50%
D
GND
t
su
t
h
V
CC
50%
CP
GND
Figure 5.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 6.
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5
MC74LVX74
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
CASE 948G−01
ISSUE A
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
0
8
0
8
D
_
_
_
_
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6
MC74LVX74
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
7
1
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
A
e
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
b
A
1
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
M
0.13 (0.005)
0.10 (0.004)
D
E
e
10.50 0.390
5.45 0.201
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
0.50
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
1
0.70
−−−
Z
1.42
−−−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74LVX74/D
相关型号：
MC74LVX74MR2
LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SO-14
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