MC74LVX574MG [ONSEMI]
Octal D-Type Flip-Flop with 3-State Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | MC74LVX574MG |
| 厂家： | 
ONSEMI |
| 描述： | Octal D-Type Flip-Flop with 3-State Outputs |
| 文件： | 总8页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX574
Octal D−Type Flip−Flop
with 3−State Outputs
The MC74LVX574 is an advanced high speed CMOS octal
flip−flop with 3−state outputs. The inputs tolerate voltages up to 7.0 V,
allowing the interface of 5.0 V systems to 3.0 V systems.
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MARKING
This 8−bit D−type flip−flop is controlled by a clock pulse input and
an output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
DIAGRAMS
Features
20
SOIC−20
DW SUFFIX
CASE 751D
• High Speed: t = 8.5 ns (Typ) at V = 3.3 V
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
PD
CC
LVX574
AWLYYWW
CC
A
20
1
1
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
20
LVX
574
ALYW
• ESD Performance:
TSSOP−20
DT SUFFIX
CASE 948E
20
Human Body Model > 2000 V;
Machine Model > 200 V
1
1
• Pb−Free Packages are Available*
20
V
O0
19
O1
18
O2
17
O3
16
O4
15
O5
14
O6
13
O7
12
CP
11
SOEIAJ−20
M SUFFIX
CASE 967
1
CC
74LVX574
AWLYWW
20
20
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
1
2
3
4
5
6
7
9
8
10
W, WW = Work Week
OE
D0
D1
D2
D3
D4
D5
D6
D7 GND
Figure 1. 20−Lead Pinout (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 2
MC74LVX574/D
MC74LVX574
C
19
18
Q
Q
Q
Q
Q0
2
3
4
5
D0
D1
D2
D3
D4
D5
D
C
Q1
D
PIN NAMES
Pins
C
17
16
Q2
Q3
D
Function
OE
CP
D0−D7
O0−O7
Output Enable Input
Clock Pulse Input
Data Inputs
C
D
3−State Latch Outputs
C
15
14
Q
Q
Q
Q
Q4
Q5
6
7
D
C
D
FUNCTION TABLE
INPUTS
C
13
12
Q6
Q7
8
9
D6
D7
D
OUTPUT
Q
OE
CP
D
C
D
L
L
H
L
X
X
H
L
No Change
Z
L
H
L, H,
X
11
1
CP
OE
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX574DWR2
MC74LVX574DWR2G
SOIC−20
1000 Tape & Reel
1000 Tape & Reel
SOIC−20
(Pb−Free)
MC74LVX574DT
MC74LVX574DTR2
MC74LVX574M
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
2500 Tape & Reel
40 Units / Rail
MC74LVX574MG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74LVX574MEL
MC74LVX574MELG
SOEIAJ−20
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX574
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
V
in
V
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
–0.5 to V +0.5
V
out
IK
CC
I
−20
±20
mA
mA
mA
mA
mW
_C
I
OK
I
±25
out
CC
I
DC Supply Current, V and GND Pins
±75
CC
P
Power Dissipation
180
D
T
stg
Storage Temperature
–65 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time
−40
0
+85
100
_C
ns/V
A
Dt/DV
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
1.5
2.0
2.4
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
V
V
V
V
V
IL
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
OH
High−Level Output Voltage
I
I
I
= −50mA
= −50mA
= −4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
(V = V or V )
in
IH
IL
V
OL
Low−Level Output Voltage
(V = V or V )
I
I
I
= 50mA
= 50mA
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
OL
OL
OL
in
IH
IL
I
Input Leakage Current
V
V
= 5.5V or GND
3.6
3.6
±0.1
±1.0
±2.5
mA
mA
in
in
I
Maximum 3−State Leakage Current
= V or V
IH
±0.2
OZ
in
IL
V
out
= V or GND
5
CC
I
Quiescent Supply Current
V
in
= V or GND
3.6
4.0
40.0
mA
CC
CC
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3
MC74LVX574
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
50
Max
Symbol
Parameter
Test Conditions
Unit
f
Maximum Clock Frequency
(50% Duty Cycle)
V
V
V
V
V
= 2.7V
C = 15pF
L
60
45
115
60
ns
max
CC
CC
CC
CC
CC
C = 50pF
L
40
= 3.3 ± 0.3V
= 2.7V
C = 15pF
C = 50pF
L
80
50
125
75
65
45
L
Propagation Delay
CP to O
t
t
t
,
C = 15pF
L
9.2
14.5
1.0
1.0
17.5
21.0
ns
ns
ns
ns
PLH
t
C = 50pF
L
11.5 18.0
8.5 13.2
11.0 16.7
9.8 15.0
11.4 18.5
8.2 12.8
PHL
= 3.3 ± 0.3V
= 2.7V
C = 15pF
C = 50pF
L
1.0
1.0
15.5
19.0
L
Output Enable Time
OE to O
,
C = 15pF
L
1.0
1.0
18.5
22.0
PZL
t
R = 1kW
C = 50pF
L
PZH
L
V
CC
= 3.3 ± 0.3V
C = 15pF
L
1.0
1.0
15.0
18.5
R = 1kW
C = 50pF
L
10.7 16.3
L
Output Disable Time
OE to O
,
V
CC
= 2.7V
C = 50pF
L
12.1 19.1
1.0
22.0
PLZ
t
R = 1kW
PHZ
L
V
CC
= 3.3 ± 0.3V
C = 50pF
L
11.0 15.0
1.0
17.0
R = 1kW
L
t
t
Output−to−Output Skew
(Note 1)
V
CC
V
CC
= 2.7V
C = 50pF
L
1.5
1.5
1.5
1.5
OSHL
OSLH
= 3.3 ±0.3V
C = 50pF
L
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
CAPACITIVE CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
4
Max
Min
Max
Symbol
Parameter
Unit
pF
Cin
Input Capacitance
10
10
C
C
Maximum Three−State Output Capacitance
Power Dissipation Capacitance (Note 2)
6
pF
out
PD
28
pF
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /8 (per latch). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 3.3V, Measured in SOIC Package)
r
f
L
CC
T
A
= 25°C
Typ
0.5
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.8
−0.8
2.0
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.5
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= − 40 to 85°C
Typ
Limit
Limit
Symbol
Parameter
Test Conditions
Unit
t
Minimum Pulse Width, CP
V
CC
V
CC
= 2.7V
= 3.3 ±0.3V
6.5
5.0
7.5
5.0
ns
w(h)
t
Minimum Setup Time, D to CP
Minimum Hold Time, D to CP
V
V
= 2.7V
= 3.3 ±0.3V
5.0
3.5
5.0
3.5
ns
ns
su
CC
CC
t
V
CC
V
CC
= 2.7V
= 3.3 ±0.3V
1.5
1.5
1.5
1.5
h
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4
MC74LVX574
SWITCHING WAVEFORMS
V
CC
CP
50%
GND
t
w
1/f
max
t
t
PHL
PLH
Q
50% V
CC
Figure 3.
OE
V
CC
50%
VOL +0.3V
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
VOL −0.3V
D
50%
IMPEDANCE
50% VCC
GND
O
O
t
su
t
h
t
t
PHZ
V
CC
PZH
CP
50%
GND
50% VCC
HIGH
IMPEDANCE
Figure 4.
Figure 5.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
CONNECT TO GND WHEN
TESTING t AND t
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
Figure 7. Three−State Test Circuit
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5
MC74LVX574
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
DETAIL E
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
−W−
F
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
G
D
J1
K
H
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0 8 0 8
0.252 BSC
M
_
_
_
_
PLANE
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6
MC74LVX574
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
20
11
Q
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1
H
E
_
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MAX
0.081
0.008
0.020
0.011
0.504
0.215
A
A
1
−−−
0.05
0.35
0.18
12.35
5.10
−−−
0.002
0.014
0.007
0.486
0.201
A
b
1
b
c
M
0.10 (0.004)
0.13 (0.005)
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0
10
_
0.035
0.032
_
_
_
0.70
−−−
0.90
0.81
0.028
−−−
1
Z
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7
MC74LVX574
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74LVX574/D
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