MC74LCX16543ADTR2 [ONSEMI]
LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56;
| 型号： | MC74LCX16543ADTR2 |
| 厂家： | 
ONSEMI |
| 描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low-Voltage CMOS 16-Bit
MC74LCX16543A
Latching Transceiver
With 5V–Tolerant Inputs and Outputs
(3–State, Non–Inverting)
The MC74LCX16543A is a high performance, non–inverting
16–bit latching transceiver operating from a 2.7 to 3.6V supply. The
device is byte controlled. Each byte has separate control inputs which
can be tied together for full 16–bit operation. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
LOW–VOLTAGE CMOS
16–BIT LATCHING
TRANSCEIVER
performance. A V specification of 5.5V allows MC74LCX16543A
I
inputs to be safely driven from 5V devices. The MC74LCX16543A is
suitable for memory address driving and all TTL level bus oriented
transceiver applications.
For data flow from A to B with the EAB LOW, the A–to–B Output
Enable (OEAB) must be LOW in order to enable data to the B bus, as
indicated in the Function Table. With EAB LOW, a LOW signal on the
A–to–B Latch Enable (LEAB) input makes the A–to–B latches
transparent; a subsequent LOW–to–HIGH transition of the LEAB
signal will latch the A latches, and the outputs no longer change with
the A inputs. With EAB and OEAB both LOW, the 3–State B output
buffers are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is symmetric to that above,
but uses the EBA, LEBA, and OEBA inputs.
DT SUFFIX
56–LEAD PLASTIC TSSOP PACKAGE
CASE 1202–01
• Designed for 2.7 to 3.6V V Operation
CC
• 5.2ns Maximum t
pd
• 5V Tolerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When V = 0V
OFF
CC
PIN NAMES
• LVTTL Compatible
• LVCMOS Compatible
Pins
Function
• 24mA Balanced Output Sink and Source Capability
OExxn
Exxn
LExxn
A0–A15
B0–B15
Output Enable Inputs
Enable Inputs
Latch Enable Inputs
3–State Inputs/Outputs
3–State Inputs/Outputs
• Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
January, 2001 – Rev. 1
MC74LCX16543/D
MC74LCX16543A
DETAIL A
52
D
B0
Q
OEAB1 1
LEAB1 2
EAB1 3
GND 4
A0 5
56 OEBA1
55 LEBA1
54 EBA1
53 GND
52 B0
LE
D
5
A0
Q
LE
A1 6
51 B1
DETAIL A x 7
V
CC
7
50
V
CC
A2 8
A3 9
49 B2
48 B3
47 B4
46 GND
45 B5
44 B6
43 B7
42 B8
41 B9
40 B10
39 GND
38 B11
37 B12
36 B13
A4 10
56
1
OEBA1
EBA1
OEAB1
EAB1
GND 11
A5 12
54
55
3
2
LEAB1
LEBA1
A6 13
A7 14
A8 15
DETAIL B
A9 16
D
42
B8
A10 17
GND 18
A11 19
A12 20
A13 21
Q
LE
D
LE
15
A8
Q
V
CC
22
35
V
CC
A14 23
A15 24
34 B14
DETAIL Bx 7
33 B15
GND 25
32 GND
31 EBA2
30 LEBA2
29 OEBA2
EAB2 26
LEAB2 27
OEAB2 28
29
28
OEBA2
EBA2
OEAB2
EAB2
31
30
26
27
LEAB2
LEBA2
Figure 2. Pinout: 56-Lead TSSOP
Figure 1. LOGIC DIAGRAM
(Top View)
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2
MC74LCX16543A
FUNCTION TABLE
Inputs
EABn
Data Ports
Operating Mode
OEABn
OEBAn
EBAn
LEABn
LEBAn
An
Bn
Input
X
H
H
Input
X
L
X
L
X
L
X
L
X
X
Disable Outputs
X
Transparent Data; Outputs Disabled
Latch and Outputs Disabled
H
H
l
l
h
h
L
H
Input
Output
H
L
X*
X*
L
X
l
h
Z
Z
Load and B Outputs Disabled
H
L
X
X
X
Z
Hold; B Outputs Disabled
Transparent A to B
L
L
H
H
H
X
X
L
l
h
L
H
Latch and Display B Outputs
Load and A Outputs Disabled
H
L
Output
Input
X*
X*
H
L
Z
Z
l
h
X
X
H
L
Z
X
Hold; A Outputs DIsabled
Transparent B to A
L
L
H
H
X
H
L
l
Latch and Display A Outputs
H
h
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; L = Low Voltage
Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; X = Don’t Care; * = The latches are
not internally gated with the Output Enables. Therefore, data at the A or B ports may enter the latches at any time, provided that the LExx and
Exx pins are set accordingly. For I reasons, Do Not Float Inputs.
CC
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage
Value
Condition
Unit
V
V
V
V
–0.5 to +7.0
CC
DC Input Voltage
–0.5 ≤ V ≤ +7.0
V
I
I
DC Output Voltage
–0.5 ≤ V ≤ +7.0
Output in 3–State
Note 1.
V
O
O
–0.5 ≤ V ≤ V + 0.5
V
O
CC
I
I
DC Input Diode Current
DC Output Diode Current
–50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
–50
+50
V < GND
O
OK
V
O
> V
CC
I
I
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
±50
O
±100
±100
CC
GND
T
–65 to +150
STG
*
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
1. Output in HIGH or LOW State. I absolute maximum rating must be observed.
O
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3
MC74LCX16543A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
2.0
1.5
3.3
3.3
3.6
3.6
V
V
V
Input Voltage
0
5.5
V
V
I
Output Voltage
(HIGH or LOW State)
(3–State)
0
0
V
CC
O
5.5
–24
24
I
I
I
I
HIGH Level Output Current, V = 3.0V – 3.6V
mA
mA
mA
mA
°C
OH
OL
OH
OL
CC
LOW Level Output Current, V = 3.0V – 3.6V
CC
HIGH Level Output Current, V = 2.7V – 3.0V
–12
12
CC
LOW Level Output Current, V = 2.7V – 3.0V
CC
T
A
Operating Free–Air Temperature
–40
0
+85
10
∆t/∆V
Input Transition Rise or Fall Rate, V from 0.8V to 2.0V,
ns/V
IN
V
CC
= 3.0V
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C
Symbol
Characteristic
HIGH Level Input Voltage (Note 2.)
LOW Level Input Voltage (Note 2.)
HIGH Level Output Voltage
Condition
2.7V ≤ V ≤ 3.6V
Min
2.0
Max
Unit
V
V
V
V
IH
CC
2.7V ≤ V ≤ 3.6V
0.8
V
IL
CC
2.7V ≤ V ≤ 3.6V; I = –100µA
V – 0.2
CC
V
OH
CC
OH
V
CC
V
CC
V
CC
= 2.7V; I = –12mA
2.2
OH
= 3.0V; I = –18mA
2.4
2.2
OH
= 3.0V; I = –24mA
OH
V
LOW Level Output Voltage
2.7V ≤ V ≤ 3.6V; I = 100µA
0.2
0.4
V
OL
CC
OL
V
= 2.7V; I = 12mA
OL
CC
CC
CC
V
V
= 3.0V; I = 16mA
0.4
OL
= 3.0V; I = 24mA
0.55
±5.0
±5.0
OL
I
I
Input Leakage Current
3–State Output Current
2.7V ≤ V ≤ 3.6V; 0V ≤ V ≤ 5.5V
µA
µA
I
CC
I
2.7 ≤ V ≤ 3.6V; 0V ≤ V ≤ 5.5V;
OZ
CC
O
V = V or V
IL
I
IH
I
I
Power–Off Leakage Current
Quiescent Supply Current
V
= 0V; V or V = 5.5V
10
20
µA
µA
µA
µA
OFF
CC
I
O
2.7 ≤ V ≤ 3.6V; V = GND or V
CC
CC
I
CC
2.7 ≤ V ≤ 3.6V; 3.6 ≤ V or V ≤ 5.5V
±20
500
CC
I
O
∆I
Increase in I per Input
2.7 ≤ V ≤ 3.6V; V = V – 0.6V
CC IH CC
CC
CC
2. These values of V are used to test DC electrical characteristics only.
I
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4
MC74LCX16543A
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)
Limits
T
A
= –40°C to +85°C
V
= 3.0V to 3.6V
Max
V
= 2.7V
CC
CC
Symbol
Parameter
Propagation Delay
Waveform
Min
Min
Max
Unit
t
t
1
1.5
1.5
5.4
5.4
1.5
1.5
6.0
6.0
ns
PLH
An to Bn or Bn to An
PHL
t
t
Propagation Delay
LEBAn to An or LEABn to Bn
4
2
2
2
2
1.5
1.5
7.0
7.0
1.5
1.5
8.2
8.2
ns
ns
ns
ns
ns
PLH
PHL
t
t
Output Enable Time
OEBAn to An or OEABn to Bn
1.5
1.5
6.5
6.5
1.5
1.5
7.0
7.0
PZH
PZL
t
t
Output Disable Time
OEBAn to An or OEABn to Bn
1.5
1.5
6.5
6.5
1.5
1.5
7.0
7.0
PHZ
PLZ
t
t
Output Enable Time
EBAn to An or EABn to Bn
1.5
1.5
6.5
6.5
1.5
1.5
7.0
7.0
PZH
PZL
t
t
Output Disable Time
EBAn to An or EABn to Bn
1.5
1.5
6.5
6.5
1.5
1.5
7.0
7.0
PHZ
PLZ
t
t
t
t
t
Setup Time, HIGH to LOW Data to LExxn
Hold Time, HIGH to LOW Data to LExxn
Setup Time, HIGH to LOW Data to Exxn
Hold Time, HIGH to LOW Data to Exxn
Latch Enable or Enable Pulse Width, LOW
4
4
4
4
4
2.5
1.5
2.5
1.5
3.0
2.5
1.5
2.5
1.5
3.0
ns
ns
ns
ns
ns
ns
s
h
s
h
w
t
t
Output–to–Output Skew
(Note 3.)
1.0
1.0
OSHL
OSLH
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
) or LOW–to–HIGH (t
); parameter
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Typ
Symbol
Characteristic
Condition
= 3.3V, C = 50pF, V = 3.3V, V = 0V
Min
Max
Unit
V
OLP
Dynamic LOW Peak Voltage (Note
4.)
V
V
0.8
V
CC
L
IH
IL
V
OLV
Dynamic LOW Valley Voltage (Note
4.)
= 3.3V, C = 50pF, V = 3.3V, V = 0V
0.8
V
CC
L
IH
IL
4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
= 3.3V, V = 0V or V
Typical
Unit
pF
C
C
C
V
V
7
8
IN
CC
I
CC
CC
Input/Output Capacitance
= 3.3V, V = 0V or V
pF
I/O
PD
CC
I
Power Dissipation Capacitance
10MHz, V = 3.3V, V = 0V or V
CC
20
pF
CC
I
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5
MC74LCX16543A
2.7V
0V
An
or Bn
1.5V
t , t
PLH PHL
V
OH
OL
Bn
or An
1.5V
V
WAVEFORM 1 - A/B to B/A PROPAGATION DELAYS
= t = 2.5ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
2.7V
OExxn
or Exxn
1.5V
1.5V
0V
t
t
PHZ
PZH
V
- 0.3V
OH
An
or Bn
1.5V
1.5V
≈ 0V
t
t
PLZ
PZL
≈ 3.0V
An
or Bn
V
+ 0.3V
OL
WAVEFORM 2 - OExx/Exx to A or B OUTPUT ENABLE AND DISABLE TIMES
= t = 2.5ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
Figure 3. AC Waveforms
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6
MC74LCX16543A
2.7V
1.5V
An
or Bn
0V
t
w
t
s
t
h
NEGATIVE
PULSE
1.5V
1.5V
1.5V
2.7V
t
Exxn
or LExxn
1.5V
1.5V
w
0V
t
, t
PLH PHL
V
OH
POSITIVE
PULSE
1.5V
An
or Bn
1.5V
t
w
V
OL
WAVEFORM 3 - INPUT PULSE DEFINITION
= t = 2.5ns, 10% to 90% of 0V to 2.7V
WAVEFORM 4 - Enable to A or B PROPAGATION DELAYS, Enable MINIMUM
PULSE WIDTH, A or B to Enable SETUP AND HOLD TIMES
t
R
F
t
R
= t = 2.5ns, 10% to 90%; f = 1MHz; t = 500ns except when noted
F W
Figure 3. AC Waveforms (continued)
V
CC
6V
OPEN
GND
R
1
PULSE
GENERATOR
DUT
R
T
C
L
R
L
TEST
SWITCH
Open
6V
t
t
, t
PLH PHL
, t
PZL PLZ
Open Collector/Drain t
and t
6V
PLH
PHL
t
, t
GND
PZH PHZ
C = 50pF or equivalent (Includes jig and probe capacitance)
L
R = R = 500Ω or equivalent
L
1
R = Z
of pulse generator (typically 50Ω)
T
OUT
Figure 4. Test Circuit
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7
MC74LCX16543A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 1202–01
ISSUE A
56X K REF
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.12 (0.005)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
J
J1
56
29
SECTION N–N
B
–U–
L
N
1
28
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
MILLIMETERS
INCHES
DIM MIN
MAX
14.10
6.20
1.10
0.15
0.75
MIN
MAX
0.555
0.244
0.043
0.006
0.030
A
–V–
PIN 1
A
B
13.90
6.00
---
0.547
0.236
---
IDENT.
N
C
D
0.05
0.50
0.002
0.020
M
F
F
G
H
0.50 BSC
0.0197 BSC
0.12
0.09
0.09
0.17
0.17
7.95
0
---
0.20
0.16
0.27
0.23
8.25
8
0.005
0.004
0.004
0.007
0.007
0.313
0
---
0.008
0.006
0.011
0.009
0.325
8
0.25 (0.010)
DETAIL E
J
J1
K
D
K1
L
C
–W–
M
0.076 (0.003)
–T–
_
_
_
_
DETAIL E
SEATING
PLANE
H
G
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MC74LCX16543/D
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