MC74LCX16374DTR2 [ONSEMI]
Low−Voltage CMOS 16−Bit D−Type Flip−Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting); 低电压CMOS 16位D型触发器，具有5 V容限输入和输出（三态，非反相）
| 型号： | MC74LCX16374DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | Low−Voltage CMOS 16−Bit D−Type Flip−Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) |
| 文件： | 总8页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LCX16374
Low−Voltage CMOS 16−Bit
D−Type Flip−Flop
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The MC74LCX16374 is a high performance, non−inverting 16−bit
D−type flip−flop operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Clock Pulse
inputs. These control pins can be tied together for full 16−bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
TSSOP−48
DT SUFFIX
CASE 1201
48
switching noise performance. A V specification of 5.5 V allows
I
1
MC74LCX16374 inputs to be safely driven from 5.0 V devices.
The MC74LCX16374 consists of 16 edge−triggered flip−flops with
individual D−type inputs and 5.0 V−tolerant 3−state true outputs. The
buffered clocks (CPn) and buffered Output Enables (OEn) are common
to all flip−flops within the respective byte. The flip−flops will store the
state of individual D inputs that meet the setup and hold time
requirements on the LOW−to−HIGH Clock (CP) transition. With the
OE LOW, the contents of the flip−flops are available at the outputs.
When the OE is HIGH, the outputs go to the high impedance state. The
OE input level does not affect the operation of the flip−flops.
MARKING DIAGRAM
48
Features
• Designed for 2.3 to 3.6 V V Operation
LCX16374G
AWLYYWW
CC
• 6.2 ns Maximum t
pd
• 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
• Supports Live Insertion and Withdrawal
1
• I
Specification Guarantees High Impedance When V = 0 V
CC
OFF
• LVTTL Compatible
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 6
MC74LCX16374/D
MC74LCX16374
1
24
25
OE1
CP1
OE2
CP2
OE1
O0
CP1
D0
1
2
48
47
46
45
48
O1
D1
3
2
13
14
16
17
19
20
22
23
nCP
D
nCP
D
O0
O1
O2
O3
O4
O5
O6
O7
O8
47
Q
Q
Q
Q
Q
36
Q
Q
Q
Q
Q
GND
O2
GND
4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
5
44 D2
3
O3
D3
V
6
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
nCP
D
nCP
D
O9
46
44
43
41
40
38
37
35
33
32
30
29
27
26
V
CC
7
CC
O4
O5
D4
8
5
nCP
D
nCP
D
D5
9
O10
O11
O12
O13
O14
O15
D10
D11
D12
D13
D14
D15
GND
O6
GND
D6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6
nCP
D
nCP
D
O7
D7
O8
D8
O9
D9
8
nCP
D
nCP
D
GND
O10
O11
GND
D10
D11
9
nCP
D
nCP
D
V
CC
V
CC
Q
Q
Q
Q
Q
Q
O12
O13
GND
O14
O15
OE2
D12
D13
GND
D14
D15
CP2
11
12
nCP
D
nCP
D
nCP
D
nCP
D
Figure 2. Logic Diagram
Figure 1. Pinout: 48−Lead
(Top View)
Table 1. PIN NAMES
Pins
Function
OEn
CPn
D0−D15
O0−O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
TRUTH TABLE
Inputs
Outputs
Inputs
Outputs
CP1
↑
OE1
L
D0:7
H
O0:7
H
CP2
↑
OE2
L
D8:15
O8:15
H
L
H
L
↑
L
L
L
↑
L
L
L
X
O0
Z
L
L
X
X
O0
Z
X
H
X
X
H
H
L
Z
↑
X
=
=
=
=
=
High Voltage Level
Low Voltage Level
High Impedance State
Low−to−High Transition
High or Low Voltage Level and Transitions Are Acceptable; for I reasons, DO NOT FLOAT Inputs
CC
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2
MC74LCX16374
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LCX16374DT
MC74LCX16374DTG
MC74LCX16374DTR2
M74LCX16374DTR2G
TSSOP−48*
TSSOP−48*
TSSOP−48*
TSSOP−48*
39 Units / Rail
39 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage
Value
Condition
Unit
V
V
CC
−0.5 to +7.0
V
I
DC Input Voltage
−0.5 ≤ V ≤ +7.0
V
I
V
O
DC Output Voltage
−0.5 ≤ V ≤ +7.0
Output in 3−State
V
O
−0.5 ≤ V ≤ V + 0.5
Output in HIGH or LOW State. (Note 1)
V
O
CC
I
DC Input Diode Current
DC Output Diode Current
−50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
I
−50
+50
50
V < GND
O
OK
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
O
I
100
100
CC
I
GND
T
−65 to +150
STG
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
(HIGH or LOW State)
(3−State)
0
0
V
CC
5.5
I
HIGH Level Output Current
LOW Level Output Current
V
V
V
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
= 2.3 V − 2.7 V
− 24
− 12
− 8
mA
mA
OH
CC
CC
CC
I
V
CC
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
= 2.3 V − 2.7 V
+ 24
+ 12
+ 8
OL
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate, V from 0.8 V to 2.0 V,
−40
0
+85
10
°C
A
Dt/DV
ns/V
IN
V
CC
= 3.0 V
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3
MC74LCX16374
DC ELECTRICAL CHARACTERISTICS
T
A
= −40°C to +85°C
Min
1.7
2.0
Max
Symbol
Characteristic
Condition
Unit
V
IH
HIGH Level Input Voltage (Note 2)
2.3 V ≤ V ≤ 2.7 V
V
CC
2.7 V ≤ V ≤ 3.6 V
CC
V
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
2.3 V ≤ V ≤ 2.7 V
0.7
0.8
V
V
IL
CC
2.7 V ≤ V ≤ 3.6 V
CC
V
OH
V
CC
− 0.2
2.3 V ≤ V ≤ 3.6 V; I = 100 mA
CC
OL
V
= 2.3 V; I = −8 mA
1.8
2.2
2.4
2.2
CC
OH
V
CC
V
CC
V
CC
= 2.7 V; I = −12 mA
OH
= 3.0 V; I = −18 mA
OH
= 3.0 V; I = −24 mA
OH
V
LOW Level Output Voltage
0.2
0.6
0.4
0.4
0.55
5.0
5.0
V
2.3 V ≤ V ≤ 3.6 V; I = 100 mA
OL
CC
OL
V
CC
= 2.3 V; I = 8 mA
OL
V
= 2.7 V; I = 12 mA
OL
CC
CC
CC
V
V
= 3.0 V; I = 16 mA
OL
= 3.0 V; I = 24 mA
OL
I
Input Leakage Current
3−State Output Current
2.3 V ≤ V ≤ 3.6 V; 0 V ≤ V ≤ 5.5 V
mA
mA
I
CC
I
I
2.3 ≤ V ≤ 3.6 V; 0V ≤ V ≤ 5.5 V;
CC O
OZ
V = V or V
IL
I
IH
I
Power−Off Leakage Current
Quiescent Supply Current
V
= 0 V; V or V = 5.5 V
10
20
mA
mA
mA
mA
OFF
CC
I
O
I
2.3 ≤ V ≤ 3.6 V; V = GND or V
CC I CC
CC
2.3 ≤ V ≤ 3.6 V; 3.6 ≤ V or V ≤ 5.5 V
20
CC
I
O
DI
Increase in I per Input
2.3 ≤ V ≤ 3.6 V; V = V − 0.6 V
500
CC
CC
CC
IH
CC
2. These values of V are used to test DC electrical characteristics only.
I
AC CHARACTERISTICS t = t = 2.5 ns; C = 50 pF; R = 500 W
R
F
L
L
T
A
= −40°C to +85°C
V
CC
= 3.3 V 0.3 V
V
CC
= 2.7 V
V = 2.5 V 0.2 V
CC
C = 50 pF
L
C = 50 pF
L
C = 30 pF
L
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Clock Pulse Frequency
Propagation Delay
Waveform
Unit
MHz
ns
f
1
1
170
max
t
t
1.5
1.5
6.2
6.2
1.5
1.5
6.5
6.5
1.5
1.5
7.4
7.4
PLH
PHL
CP to O
n
t
t
Output Enable Time to
High and Low Level
2
2
1
1.5
1.5
6.1
6.1
1.5
1.5
6.3
6.3
1.5
1.5
7.9
7.9
ns
ns
ns
PZH
PZL
t
Output Disable Time From
High and Low Level
1.5
1.5
6.0
6.0
1.5
1.5
6.2
6.2
1.5
1.5
7.2
7.2
PHZ
t
PLZ
n
t
s
Setup Time, HIGH or LOW D to
CP
2.5
2.5
3.0
n
t
Hold Time, HIGH or LOW D to CP
1
3
1.5
3.0
1.5
3.0
2.0
3.5
ns
ns
ns
h
t
w
CP Pulse Width, HIGH
t
t
Output−to−Output Skew
(Note 3)
1.0
1.0
OSHL
OSLH
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
guaranteed by design.
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4
MC74LCX16374
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Min
Typ
Max
Symbol
Characteristic
Condition
Unit
V
OLP
Dynamic LOW Peak Voltage
(Note 4)
V
CC
V
CC
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
0.8
0.6
V
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
V
OLV
Dynamic LOW Valley Voltage
(Note 4)
V
CC
V
CC
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
−0.8
−0.6
V
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
= 3.3 V, V = 0 V or V
Typical
Unit
pF
C
V
V
7
8
IN
CC
I
CC
CC
C
Output Capacitance
= 3.3 V, V = 0 V or V
pF
OUT
CC
I
C
Power Dissipation Capacitance
10 MHz, V = 3.3 V, V = 0 V or V
CC
20
pF
PD
CC
I
V
CC
V
CC
Vmi
Vmi
OEn
Dn
Vmi
0 V
0 V
V
t
t
PHZ
PZH
t
h
t
s
V
OH
V
HZ
CC
Vmo
On
Vmo
CPn
0 V
f
max
t
t
PLZ
PZL
t
, t
PLH PHL
V
OH
Vmo
On
On
Vmo
V
HZ
V
OL
V
OL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
t
R
F
W
F
W
V
CC
CPn
Vmi
Vmi
t
t
0 V
w
V
CC
w
Vmo
Vmo
CPn
0 V
WAVEFORM 3 − PULSE WIDTH
t
R
= t = 2.5 ns (or fast as required) from 10% to 90%;
F
Output requirements: V ≤ 0.8 V, V ≥ 2.0 V
OL
OH
Figure 3. AC Waveforms
Table 2. AC WAVEFORMS
V
CC
3.3 V 0.3 V
1.5 V
2.7 V
1.5 V
1.5 V
2.5 V + 0.2 V
Symbol
Vmi
V
/ 2
/ 2
CC
CC
Vmo
1.5 V
V
V
V
+ 0.3 V
− 0.3 V
V
+ 0.3 V
V
OL
+ 0.15 V
− 0.15 V
HZ
OL
OL
V
V
OH
V
OH
− 0.3 V
V
OH
LZ
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5
MC74LCX16374
V
CC
6 V or V × 2
CC
OPEN
R
1
PULSE
GENERATOR
GND
DUT
R
T
C
L
R
L
Figure 4. Test Circuit
Table 3. TEST CIRCUIT
TEST
SWITCH
t
, t
Open
PLH PHL
t
, t
6 V at V = 3.3 ꢀ 0.3 V
CC
PZL PLZ
6 V at V = 2.5 ꢀ 0.2 V
CC
Open Collector/Drain t
and t
6 V
PLH
PHL
t
, t
GND
PZH PHZ
C = 50 pF at V = 3.3 ꢀ 0.3 V or equivalent (includes jig and probe capacitance)
L
CC
C = 30 pF at V = 2.5 ꢀ 0.2 V or equivalent (includes jig and probe capacitance)
L
CC
R = R = 500 W or equivalent
L
1
R = Z
of pulse generator (typically 50 W)
T
OUT
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6
MC74LCX16374
PACKAGE DIMENSIONS
TSSOP−48
DT SUFFIX
CASE 1201−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
48X K REF
K
K1
M
S
S
V
0.12 (0.005)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
J1
48
25
SECTION N−N
B
−U−
L
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
1
24
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
12.60
6.20
1.10
0.15
0.75
MAX
0.496
0.244
0.043
0.006
0.030
A
B
12.40
6.00
−−−
0.488
0.236
−−−
A
−V−
PIN 1
IDENT.
N
C
D
0.05
0.50
0.002
0.020
M
F
F
G
H
0.50 BSC
0.0197 BSC
0.37
0.09
0.09
0.17
0.17
7.95
0
−−−
0.20
0.16
0.27
0.23
8.25
8
0.015
0.004
0.004
0.007
0.007
0.313
0
−−−
0.008
0.006
0.011
0.009
0.325
8
0.25 (0.010)
DETAIL E
J
J1
K
K1
L
D
C
M
_
_
_
_
−W−
0.076 (0.003)
DETAIL E
−T−
SEATING
PLANE
H
G
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7
MC74LCX16374
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74LCX16374/D
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