MC74HCU04AD [ONSEMI]
Hex Unbuffered Inverter; 六角无缓冲变频器型号: | MC74HCU04AD |
厂家: | ONSEMI |
描述: | Hex Unbuffered Inverter |
文件: | 总8页 (文件大小:162K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
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This device consists of six single–stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high–input impedance amplifier. For digital
applications, the HC04A is recommended.
MARKING
DIAGRAMS
14
PDIP–14
N SUFFIX
CASE 646
MC74HCU04AN
AWLYYWW
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
1
• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator
Configurations
14
SOIC–14
D SUFFIX
CASE 751A
HCU04A
AWLYWW
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
1
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
14
HCU
04A
ALYW
TSSOP–14
DT SUFFIX
CASE 948G
• Chip Complexity: 12 FETs or 3 Equivalent Gates
LOGIC DIAGRAM
1
A
= Assembly Location
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
Y3
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
PIN ASSIGNMENT
A1
Y1
1
2
14
13 A6
12
V
CC
Y = A
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
A2
Y2
3
4
Y6
11 A5
10 Y5
11
13
A3
Y3
5
6
7
PIN 14 = V
PIN 7 = GND
CC
9
8
A4
Y4
GND
FUNCTION TABLE
Inputs
A
Outputs
Y
ORDERING INFORMATION
L
H
H
L
Device
Package
PDIP–14
Shipping
MC74HCU04AN
2000 / Box
55 / Rail
MC74HCU04AD
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
MC74HCU04ADR2
MC74HCU04ADT
MC74HCU04ADTR2
2500 / Reel
96 / Rail
2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 2
MC74HCU04A/D
MC74HCU04A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/ C from 65 to 125 C
SOIC Package: –7mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
—
No
Limit
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= 0.5 V*
out
85 C
125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
|I
2.0
3.0
4.5
6.0
1.7
2.5
3.6
4.8
1.7
2.5
3.6
4.8
l.7
V
|
20 µA
2.5
3.6
4.8
out
V
Maximum Low–Level Input
Voltage
V
= V
– 0.5 V*
2.0
3.0
4.5
6.0
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= GND
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
in
|I
|
20 µA
out
V
in
= GND
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.36
3.86
5.36
2.26
3.76
5.26
2.20
3.70
5.20
out
out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V
|
2.0
4.5
6.0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
V
in
CC
20 µA
|I
out
V
in
= V
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
CC
out
out
out
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2
MC74HCU04A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
I
Maximum Input Leakage
Current
V
V
= V
= V
or GND
6.0
± 0.1
± 1.0
± 1.0
µA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
6.0
1
10
40
µA
CC
in
CC
I
= 0 µA
out
NOTE: InformationontypicalparametricvaluescanbefoundinChapter2oftheONSemiconductorHigh–SpeedCMOSDataBook(DL129/D).
*For V = 2.0 V, V = 0.2 V or V – 0.2 V.
CC out CC
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
85 C
125 C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
70
40
14
12
90
45
18
15
105
50
21
ns
PLH
PHL
18
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
pF
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Informationon typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Inverter)*
pF
15
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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3
MC74HCU04A
TEST POINT
OUTPUT
t
t
f
r
V
CC
90%
50%
10%
DEVICE
UNDER
TEST
INPUT A
GND
C *
L
t
t
PHL
PLH
90%
50%
10%
OUTPUT Y
t
t
TLH
THL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
LOGIC DETAIL
(1/6 of Device Shown)
V
CC
A
Y
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4
MC74HCU04A
TYPICAL APPLICATIONS
Crystal Oscillator
Stable RC Oscillator
R
2
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
V
out
R > > R
2
1
1
C < C
2
C
1/6 HCU04A
R
1
R
2
R
1
C
1
C
2
V
out
Schmitt Trigger
High Input Impedance Single–Stage Amplifier
with a 2 to 6 V Supply Range
R
2
V
CC
1 M
1/6 HCU04A
R > 6R
2
1
1/6 HCU04A 1/6 HCU04A
R
1
INPUT
OUTPUT
V
in
V
out
1 M
Multi–Stage Amplifier
LED Driver
+V
V
CC
1/6 HCU04A
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
INPUT
OUTPUT
For reduced power supply current, use high–efficiency LEDs
such as the Hewlett–Packard HLMP series or equivalent.
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5
MC74HCU04A
PACKAGE DIMENSIONS
PDIP–14
N SUFFIX
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
19.56
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
M
N
0
10
0.039
0
0.39
10
1.01
0.015
H
G
D
M
SOIC–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
7
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
K
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T B
A
7
0
7
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
R
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6
MC74HCU04A
PACKAGE DIMENSIONS
TSSOP–14
DT SUFFIX
CASE 948G–01
ISSUE O
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
–V–
A
B
C
4.90
4.30
–––
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
––– 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
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7
MC74HCU04A
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withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC74HCU04A/D
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