MC74HCU04ADG [ONSEMI]
Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS; 六角无缓冲变频器高性能硅栅CMOS型号: | MC74HCU04ADG |
厂家: | ONSEMI |
描述: | Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS |
文件: | 总9页 (文件大小:167K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74HCU04A
Hex Unbuffered Inverter
High−Performance Silicon−Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of six single−stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high−input impedance amplifier. For digital
applications, the HC04A is recommended.
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MARKING
DIAGRAMS
14
1
PDIP−14
N SUFFIX
CASE 646
Features
MC74HCU04AN
AWLYYWWG
14
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
1
• Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator
Configurations
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 12 FETs or 3 Equivalent Gates
• Pb−Free Packages are Available
14
SOIC−14
D SUFFIX
CASE 751A
HCU04AG
AWLYWW
14
1
1
14
HCU
TSSOP−14
DT SUFFIX
CASE 948G
14
04A
ALYWG
1
G
1
14
SOEIAJ−14
F SUFFIX
CASE 965
74HCU04A
ALYWG
14
1
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 4
MC74HCU04A/D
MC74HCU04A
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
Y1
1
2
14
13 A6
12
V
1
2
4
6
CC
A1
A2
A3
Y1
Y2
Y3
3
5
A2
Y2
3
4
Y6
11 A5
10 Y5
A3
Y3
5
6
7
9
8
A4
Y4
GND
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
11
13
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
H
L
Y = A
PIN 14 = V
CC
PIN 7 = GND
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCU04AN
PDIP−14
25 Units / Rail
55 Units / Rail
MC74HCU04ANG
PDIP−14
(Pb−Free)
MC74HCU04AD
SOIC−14
MC74HCU04ADG
SOIC−14
(Pb−Free)
MC74HCU04ADR2
MC74HCU04ADR2G
SOIC−14
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2000 / Tape & Reel
MC74HCU04ADTR2
MC74HCU04ADTR2G
MC74HCU04AFEL
MC74HCU04AFELG
TSSOP−14*
TSSOP−14*
SOEIAJ−14
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCU04A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
± 20
± 25
± 50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
6.0
V , V
in out
V
CC
V
T
A
– 55
−
+ 125
_C
ns
t , t
No
r
f
Limit
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25_C
1.7
2.5
3.6
4.8
Symbol
Parameter
Test Conditions
= 0.5 V*
out
|I | v 20 mA
out
v 85_C
1.7
2.5
3.6
4.8
v 125_C
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
l.7
V
Voltage
2.5
3.6
4.8
V
Maximum Low−Level Input
Voltage
V
= V – 0.5 V*
2.0
3.0
4.5
6.0
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= GND
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
|I | v 20 mA
out
V
in
= GND
|I | v 2.4 mA
3.0
4.5
6.0
2.36
3.86
5.36
2.26
3.76
5.26
2.20
3.70
5.20
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
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3
MC74HCU04A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25_C
0.2
0.5
0.5
Symbol
Parameter
Test Conditions
v 85_C
0.2
0.5
0.5
v 125_C
Unit
V
OL
Maximum Low−Level Output
V
= V
CC
|I | v 20 mA
2.0
4.5
6.0
0.2
0.5
0.5
V
in
Voltage
out
V
= V
|I | v 2.4 mA
3.0
4.5
6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
in
in
CC
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
1
10
40
CC
in
CC
I
= 0 mA
out
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. For V = 2.0 V, V = 0.2 V or V − 0.2 V.
CC
out
CC
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25_C
70
40
14
12
Symbol
Parameter
v 85_C
90
45
18
15
v 125_C
Unit
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
105
50
ns
PLH
t
PHL
21
18
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
pF
in
3. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
4. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
15
C
Power Dissipation Capacitance (Per Inverter)*
pF
PD
2
5. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
V
CC
TEST POINT
OUTPUT
t
r
t
f
V
CC
A
Y
90%
50%
10%
DEVICE
INPUT A
GND
UNDER
TEST
C *
L
t
t
PLH
PHL
90%
50%
10%
OUTPUT Y
t
t
TLH
THL
*Includes all probe and jig capacitance
Figure 3. Logic Detail
Figure 1. Switching Waveforms
Figure 2. Test Circuit
(1/6 of Device Shown)
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4
MC74HCU04A
TYPICAL APPLICATIONS
R
2
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
R > > R
2
1
V
out
C < C
1
2
1/6 HCU04A
R
1
C
C
1
C
2
R
2
R
1
V
out
Figure 4. Crystal Oscillator
Figure 5. Stable RC Oscillator
V
CC
R
2
1 M
1/6 HCU04A
INPUT
OUTPUT
R > 6R
2
1
1/6 HCU04A 1/6 HCU04A
R
1
1 M
V
in
V
out
Figure 6. Schmitt Trigger
Figure 7. High Input Impedance Single−Stage
Amplifier with a 2 to 6 V Supply Range
+ꢀV
V
CC
1/6 HCU04A
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
INPUT
OUTPUT
For reduced power supply current, use high−efficiency LEDs
such as the Hewlett−Packard HLMP series or equivalent.
Figure 8. Multi−Stage Amplifier
Figure 9. LED Driver
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5
MC74HCU04A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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6
MC74HCU04A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MC74HCU04A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74HCU04A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢁꢂ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢁꢂ2. CONTROLLING DIMENSION: MILLIMETER.
ꢁꢂ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢁꢂ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢁꢂ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
−−−
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
1
0.70
−−−
Z
1.42
−−−
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74HCU04A/D
相关型号:
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