MC14562BCP [ONSEMI]
128-Bit Static Shift Register; 128位静态移位寄存器
| 型号： | MC14562BCP |
| 厂家： | 
ONSEMI |
| 描述： | 128-Bit Static Shift Register |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14562B is a 128–bit static shift register constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.
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MARKING
DIAGRAMS
14
• Diode Protection on All Inputs
• Fully Static Operation
• Cascadable to Provide Longer Shift Register Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
PDIP–14
P SUFFIX
CASE 646
MC14562BCP
AWLYYWW
1
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
per Package (Note 2.)
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
T
stg
Device
MC14562BCP
Package
Shipping
25/Rail
T
Lead Temperature
(8–Second Soldering)
L
PDIP–14
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14562B/D
MC14562B
PIN ASSIGNMENT
Q64
Q96
1
2
3
4
5
6
7
14
V
DD
13 Q32
12 DATA
11 NC
Q128
NC
CLOCK
Q112
10 Q16
9
8
Q48
Q80
V
SS
NC = NO CONNECTION
BLOCK DIAGRAM
Q16
10
13
9
12
5
DATA
Q32
Q48
Q64
1
Q80
Q96
Q112
Q128
8
2
6
3
CLOCK
Pins 4 and 11
not used.
V
V
= PIN 14
= PIN 7
DD
SS
LOGIC DIAGRAM
CLOCK 5
DATA IN 12
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
1
2
3
16
17
32
33
48
49
64
10 Q16
13 Q32
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
65
80
81
96
97
112
113
128
9
1
Q48
Q64
8
2
Q80
Q96
6
3
Q112
Q128
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2
MC14562B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(3.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 05 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
±0.1
—
—
±0.00001
±0.1
—
—
±1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(4.) (5.)
Total Supply Current
I
T
5.0
10
15
I = (1.94 µA/kHz) f + I
T
I = (3.81 µA/kHz) f + I
T
I = (5.52 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25 C.
5. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.004.
T
L
DD
SS
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3
MC14562B
SWITCHING CHARACTERISTICS (6.) (C = 50 pF, T = 25 C)
L
A
(7.)
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Output Rise and Fall Time
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time
Clock to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 515 ns
= (0.66 ns/pF) C + 217 ns
L
5.0
10
15
—
—
—
600
250
170
1200
500
340
PLH PHL
L
, t
PLH PHL
, t
= (0.5 ns/pF) C + 145 ns
PLH PHL
L
Clock Pulse Width
(50% Duty Cycle)
t
5.0
10
15
600
220
150
300
110
75
—
—
—
ns
MHz
ns
WH
Clock Pulse Frequency
f
cl
5.0
10
15
—
—
—
1.9
5.6
8.0
1.1
3.0
4.0
Data to Clock Setup Time
t
t
5.0
10
15
– 20
– 10
0
– 170
– 64
– 60
—
—
—
su(1)
su(0)
5.0
10
15
– 20
– 10
0
– 91
– 58
– 48
—
—
—
ns
Data to Clock Hold Time
t
5.0
10
15
350
165
155
263
109
100
—
—
—
ns
h(1)
t
5.0
10
15
350
200
140
267
140
93
—
—
—
ns
h(0)
Clock Input Rise and Fall Times
t , t
r
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
f
6. The formulas given are for the typical characteristics only at 25 C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14562B
V
DD
Q16
DATA
Q32
Q48
Q64
Q80
Q96
Q112
Q128
CLOCK
7
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
V
SS
I
D
500 µF
V
DD
f
o
CLOCK
V
SS
V
DD
DATA
(f = 1/2 f )
o
V
SS
Figure 1. Power Dissipation Test Circuit and Waveforms
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5
MC14562B
TIMING DIAGRAM
PIN
PULSE 1
PULSE 16
PULSE 32
PULSE 128
NO.’S
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28
3
AC TEST WAVEFORMS
PULSE 1
50%
PULSE 2
PULSE 16
PULSE 17
50%
V
DD
90%
10%
CLOCK
50%
50%
V
SS
t
WH
t
r
t
t
f
WL
V
DD
50%
50%
DATA IN
Q16
V
SS
t
su(0)
t
h(0)
V
DD
90%
50%
10%
V
SS
t
PHL
t
THL
PULSE 1
50%
PULSE 2
PULSE 16
PULSE 17
V
DD
50%
50%
50%
CLOCK
V
SS
t
WH
t
WL
V
DD
50%
50%
DATA IN
Q16
V
SS
t
su(1)
t
h(1)
V
DD
90%
10%
50%
V
SS
t
PLH
t
THL
NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
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6
MC14562B
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
N
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
–––
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
–––
2.41
0.38
3.43
7.87
10
–T–
SEATING
PLANE
J
K
M
N
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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7
MC14562B
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MC14562B/D
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