MC14562BCPD [MOTOROLA]
4000/14000/40000 SERIES, 128-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14, 646-06;型号: | MC14562BCPD |
厂家: | MOTOROLA |
描述: | 4000/14000/40000 SERIES, 128-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14, 646-06 移位寄存器 |
文件: | 总6页 (文件大小:187K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 632
The MC14562B is a 128–bit static shift register constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Data is clocked in and out of the shift register on the
positive edge of the clock input. Data outputs are available every 16 bits,
from 16 through bit 128. This complementary MOS shift register is primarily
used where low power dissipation and/or high noise immunity is desired.
P SUFFIX
PLASTIC
CASE 646
•
•
•
•
•
Diode Protection on All Inputs
Fully Static Operation
Cascadable to Provide Longer Shift Register Lengths
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
T
A
= – 55° to 125°C for all packages.
V
DD
– 0.5 to + 18.0
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
BLOCK DIAGRAM
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
Q16
Q32
Q48
Q64
10
13
9
T
stg
– 65 to + 150
260
12
DATA
T
Lead Temperature (8–Second Soldering)
C
L
1
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Q80
Q96
Q112
Q128
8
2
6
3
5
CLOCK
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
Pins 4 and 11
not used.
V
V
= PIN 14
= PIN 7
DD
SS
CLOCK
5
DATA IN 12
D Q
C
D
C
Q
D Q
C
D Q
C
D
C
Q
D Q
C
D
C
Q
D Q
C
D
C
Q
D Q
C
1
2
3
16
17
32
33
48
49
64
10 Q16
13 Q32
D Q
C
D
C
Q
D Q
C
D
C
Q
D Q
C
D Q
C
D
C
Q
D Q
C
65
80
81
96
97
112
113
128
9
1
Q48
Q64
8
2
Q80
Q96
6
3
Q112
Q128
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 05 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
±0.1
—
—
±0.00001
±0.1
—
—
±1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (1.94 µA/kHz) f + I
= (3.81 µA/kHz) f + I
= (5.52 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.004.
SS
T
L
PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
Q64
Q96
Q128
NC
1
2
3
4
14
13
12
11
V
DD
Q32
DATA
NC
voltages to this high-impedance circuit. For proper operation, V and
in
V
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
out
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V
or V ). Unused outputs must be left open.
DD
SS
CLOCK
Q112
5
6
10
9
Q16
Q48
V
7
8
Q80
SS
NC = NO CONNECTION
MC14562B
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
V
DD
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
TLH THL
, t
TLH THL
L
Propagation Delay Time
Clock to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 515 ns
= (0.66 ns/pF) C + 217 ns
L
= (0.5 ns/pF) C + 145 ns
5.0
10
15
—
—
—
600
250
170
1200
500
340
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
Clock Pulse Width
t
5.0
10
15
600
220
150
300
110
75
—
—
—
ns
MHz
ns
WH
(50% Duty Cycle)
Clock Pulse Frequency
f
cl
5.0
10
15
—
—
—
1.9
5.6
8.0
1.1
3.0
4.0
Data to Clock Setup Time
t
t
5.0
10
15
– 20
– 10
0
– 170
– 64
– 60
—
—
—
su(1)
su(0)
5.0
10
15
– 20
– 10
0
– 91
– 58
– 48
—
—
—
ns
Data to Clock Hold Time
t
5.0
10
15
350
165
155
263
109
100
—
—
—
ns
h(1)
h(0)
t
5.0
10
15
350
200
140
267
140
93
—
—
—
ns
Clock Input Rise and Fall Times
t , t
r f
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
Q16
DATA
Q32
Q48
Q64
Q80
Q96
Q112
Q128
CLOCK
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
7
V
SS
I
500 µF
D
V
V
V
V
DD
SS
DD
SS
f
o
CLOCK
DATA
(f = 1/2 f )
o
Figure 1. Power Dissipation Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14562B
3
TIMING DIAGRAM
PIN
PULSE 1
PULSE 16
PULSE 32
PULSE 128
NO.’S
CLOCK
5
DATA IN 12
Q16 10
Q32 13
Q28
3
AC TEST WAVEFORMS
PULSE 1
50%
PULSE 2
PULSE 16
PULSE 17
V
V
90%
10%
DD
CLOCK
50%
50%
50%
SS
t
WH
t
r
t
t
f
WL
V
V
DD
50%
50%
DATA IN
Q16
SS
t
su(0)
t
h(0)
V
V
DD
90%
50%
10%
SS
t
PHL
t
THL
PULSE 17
PULSE 1
50%
PULSE 2
PULSE 16
V
V
DD
50%
50%
50%
CLOCK
SS
t
WH
t
WL
V
V
DD
50%
50%
DATA IN
Q16
SS
t
su(1)
t
h(1)
V
V
DD
90%
10%
50%
SS
t
PLH
t
THL
NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
MC14562B
4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
7
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
–T–
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
G
N
M
D 14 PL
0.25 (0.010)
J 14 PL
0.25 (0.010)
L
M
N
0.300 BSC
7.62 BSC
0
15
0
15
M
S
T
A
M
S
T
B
0.020
0.040
0.51
1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
1
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
MOTOROLA CMOS LOGIC DATA
MC14562B
5
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE F
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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are registered
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MC14562B/D
◊
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