MC14521BFEL [ONSEMI]
24-Stage Frequency Divider; 24级分频器
| 型号： | MC14521BFEL |
| 厂家： | 
ONSEMI |
| 描述： | 24-Stage Frequency Divider |
| 文件： | 总12页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14521B consists of a chain of 24 flip–flops with an input
circuit that allows three modes of operation. The input will function as
a crystal oscillator, an RC oscillator, or as an input buffer for an
external oscillator. Each flip–flop divides the frequency of the
24
previous flip–flop by two, consequently this part will count up to 2
=
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16,777,216. The count advances on the negative going edge of the
clock. The outputs of the last seven–stages are available for added
flexibility.
MARKING
DIAGRAMS
16
• All Stages are Resettable
• Reset Disables the RC Oscillator for Low Standby Power Drain
PDIP–16
P SUFFIX
CASE 648
MC14521BCP
AWLYYWW
• RC and Crystal Oscillator Outputs Are Capable of Driving External
Loads
1
• Test Mode to Reduce Test Time
16
• V ′ and V ′ Pins Brought Out on Crystal Oscillator Inverter to
DD
SS
SOIC–16
D SUFFIX
CASE 751B
Allow the Connection of External Resistors for Low–Power
Operation
14521B
AWLYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
• Capable of Driving Two Low–power TTL Loads or One Low–power
16
Schottky TTL Load over the Rated Temperature Range.
SOEIAJ–16
F SUFFIX
CASE 966
MC14521B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
A
= Assembly Location
Symbol
Parameter
Value
Unit
V
WL or L = Wafer Lot
YY or Y = Year
V
DD
DC Supply Voltage Range
–0.5 to +18.0
WW or W = Work Week
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
ORDERING INFORMATION
Device
Package
PDIP–16
SOIC–16
Shipping
P
Power Dissipation,
per Package (Note 3.)
500
mW
D
MC14521BCP
MC14521BD
2000/Box
48/Rail
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
T
stg
MC14521BDR2
SOIC–16 2500/Tape & Reel
T
Lead Temperature
L
MC14521BF
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
See Note 1.
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14521BFEL
MC14521BFR2
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14521B/D
MC14521B
PIN ASSIGNMENT
Q24
1
2
3
4
5
6
7
8
16
V
DD
RESET
15 Q23
14 Q22
13 Q21
12 Q20
11 Q19
10 Q18
V
SS
′
OUT 2
V
′
DD
IN 2
V
SS
9
IN 1
BLOCK DIAGRAM
RESET
2
Output
Count Capacity
18
Q18
Q19
Q20
Q21
Q22
Q23
Q24
2
= 262,144
= 524,288
19
20
21
22
23
24
2
2
2
2
2
2
STAGES
1 THRU 17
STAGES
18 THRU 24
= 1,048,576
= 2,097,152
= 4,194,304
= 8,388,608
= 16,777,216
9
6
IN 1
IN 2
Q18 Q19 Q20 Q21 Q22 Q23 Q24
V
V
= PIN 16
= PIN 8
DD
SS
5
DD
4
3
V
SS
7
10 11 12 13 14 15
1
V
′
OUT2
OUT 1
′
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2
MC14521B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Pins 4 & 7
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 2.5 Vdc)
Source
Pins 1, 10,
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
mAdc
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc) 11, 12, 13, 14
OH
(V = 13.5 Vdc)
OH
and 15
15
(V = 0.4 Vdc)
Sink
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.42 µA/kHz) f + I
T
I = (0.85 µA/kHz) f + I
T
I = (1.40 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.003.
T
L
DD
SS
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3
MC14521B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
(8.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise and Fall Time (Counter Outputs)
t
, t
ns
TLH THL
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 12.5 ns
L
TLH THL
Propagation Delay Time
Clock to Q18
t
, t
µs
PHL PLH
t
t
t
, t
= (1.7 ns/pF) C + 4415 ns
= (0.66 ns/pF) C + 1667 ns
L
= (0.5 ns/pF) C + 1275 ns
L
5.0
10
15
—
—
—
4.5
1.7
1.3
9.0
3.5
2.7
PHL PLH
L
, t
PHL PLH
, t
PHL PLH
Clock to Q24
t
t
t
, t
= (1.7 ns/pF) C + 5915 ns
= (0.66 ns/pF) C + 2167 ns
L
= (0.5 ns/pF) C + 1675 ns
L
5.0
10
15
—
—
—
6.0
2.2
1.7
12
4.5
3.5
PHL PLH
L
, t
PHL PLH
, t
PHL PLH
Propagation Delay Time
Reset to Q
t
ns
PHL
n
t
t
t
= (1.7 ns/pF) C + 1215 ns
5.0
10
15
—
—
—
1300
500
375
2600
1000
750
PHL
PHL
PHL
L
= (0.66 ns/pF) C + 467 ns
L
= (0.5 ns/pF) C + 350 ns
L
Clock Pulse Width
t
5.0
10
15
385
150
120
140
55
40
—
—
—
ns
MHz
µs
WH(cl)
Clock Pulse Frequency
Clock Rise and Fall Time
Reset Pulse Width
f
cl
5.0
10
15
—
—
—
3.5
9.0
12
2.0
5.0
6.5
t
, t
5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
TLH THL
t
5.0
10
15
1400
600
450
700
300
225
—
—
—
ns
WH(R)
Reset Removal Time
t
5.0
10
15
30
0
– 40
– 200
– 160
– 110
—
—
—
ns
rem
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
0.01 µF
CERAMIC
500 µF
I
D
V
DD
V
DD
20 ns
90%
10%
20 ns
DD
Q18
Q19
PULSE
GENERATOR
V
C
L
IN 2
V
in
50%
C
L
Q20
Q21
Q22
Q23
Q24
0 V
C
L
50% DUTY CYCLE
C
L
C
L
R
C
L
C
L
V
V
SS
SS
Figure 1. Power Dissipation Test Circuit and Waveform
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4
MC14521B
V
DD
V
V ′
DD
DD
20 ns
20 ns
90%
20 ns
IN 2
Q18
Q19
PULSE
GENERATOR
C
L
IN 2
50%
10%
C
L
Q20
Q21
Q22
Q23
Q24
C
L
t
t
WH
WL
C
L
90%
C
L
50%
Q
n
R
10%
t
C
L
t
C
L
PLH
PHL
V
SS
V ′
SS
t
t
THL
TLH
Figure 2. Switching Time Test Circuit and Waveforms
500 kHz
Circuit
50 kHz
Circuit
Characteristic
Unit
Crystal Characteristics
Resonant Frequency
500
1.0
50
6.2
kHz
kΩ
Equivalent Resistance, R
S
External Resistor/Capacitor Values
V
DD
R
C
C
47
82
20
750
82
20
kΩ
pF
pF
o
T
S
R
o
R*
V
V ′
DD
DD
Frequency Stability
18 M
Frequency Change as a Function
of V (T = 25 C)
IN 1 OUT 1
OUT 2
Q18
DD
A
V
DD
V
DD
Change from 5.0 V to 10 V
Change from 10 V to 15 V
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
Q19
IN 2
Q20
Q21
Q22
Q23
Q24
Frequency Change as a Function
of Temperature (V = 10 V)
DD
– 4.0
+ 100
– 2.0
+ 120
ppm
ppm
T Change from – 55 C to + 25 C
A
C
S
C
T
MC14521 only
R
Complete Oscillator*
V
SS
V ′
SS
T Change from +25 C to+125 C
A
R*
MC14521 only
– 2.0
– 160
– 2.0
– 560
ppm
ppm
Complete Oscillator*
* Optional for low power operation,
10 kΩ ≤ R ≤ 70 kΩ.
*Complete oscillator includes crystal, capacitors, and resistors.
Figure 4. Typical Data for Crystal Oscillator Circuit
Figure 3. Crystal Oscillator Circuit
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5
MC14521B
100
50
TEST CIRCUIT
FIGURE 7
V
DD
= 10 V
8.0
4.0
TEST CIRCUIT
FIGURE 7
V
DD
= 15 V
20
10
f AS A FUNCTION
OF R
TC
(C = 1000 pF)
(R ≈ 2R
)
TC
S
5.0
0
–4.0
–8.0
–12
–16
f AS A FUNCTION
OF C
2.0
1.0
0.5
10 V
(R = 56 kΩ)
TC
(R = 120 k)
S
5.0 V
0.2
0.1
R
= 56 kΩ,
R = 0, f = 10.15 kHz @ V = 10 V, T = 25°C
S DD A
R = 120 kΩ, f = 7.8 kHz @ V = 10 V, T = 25°C
S DD A
TC
1.0 k
10 k
100 k
1.0 m
0.1
{
C = 1000 pF
R
, RESISTANCE (OHMS)
TC
–55
–25
0
25
50
75
100
125
0.0001
0.001
0.01
T , AMBIENT TEMPERATURE (°C), DEVICE ONLY
C, CAPACITANCE (µF)
A
Figure 5. RC Oscillator Stability
Figure 6. RC Oscillator Frequency as a
Function of RTC and C
R
S
R
TC
V
DD
V
DD
C
V
′
DD
V
DD
V ′
DD
IN 1
Q18
IN 1 OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q19
IN 2
R
PULSE
GENERATOR
IN 2
Q20
Q21
Q22
Q23
Q24
OUT 1
OUT 2
R
V
SS
V
SS
V
SS
V ′
SS
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
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6
MC14521B
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
Reset
In 2
Out 2
V
′
V
′
Q18 thru
Q24
Counter is in three 8–stage
sections in parallel mode
Counter is reset. In 2 and
Out 2 are connected
together
SS
DD
V
Gnd
0
1
0
0
1
0
1
DD
First “0” to “1” transition
on In 2, Out 2 node.
A test function (see Figure 8) has been
includedfor the reduction of test time required to
exercise all 24 counter stages. This test function
divides the counter into three 8–stage sections,
and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are
now at a logic “1”. The counter is now returned
to the normal 24–stages in series configuration.
One more pulse is entered into Input 2 (In 2)
which will cause the counter to ripple from an all
“1” state to an all “0” state.
0
1
—
—
—
0
1
—
—
—
255 “0” to “1” transitions
are clocked into this In 2,
Out 2 node.
The 255th “0” to “1”
transition.
1
1
1
0
0
0
0
1
1
Gnd
Counter converted back to
24–stages in series mode.
1
1
0
0
1
1
V
DD
Out 2 converts back to an
output.
Counter ripples from an all
“1” state to an all “0” stage.
0
1
0
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7
MC14521B
LOGIC DIAGRAM
V
5
RESET
2
DD
9
STAGES
3 THRU 7
1
2
8
IN 1
6
IN 2
4
OUT 2
7
3
V
SS
OUT 1
STAGES
11 THRU 15
9
10
16
17
18
19
20
21
22
23
24
V
V
= PIN 16
= PIN 8
10
Q18
11
Q19
12
Q20
13
Q21
14
Q22
15
Q23
1
Q24
DD
SS
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8
MC14521B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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9
MC14521B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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10
MC14521B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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11
MC14521B
ON Semiconductor and
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