MC145220 [MOTOROLA]
Dual 1.1 GHz PLL Frequency Synthesizer; 双1.1 GHz的PLL频率合成器
| 型号： | MC145220 |
| 厂家： | 
MOTOROLA |
| 描述： | Dual 1.1 GHz PLL Frequency Synthesizer |
| 文件： | 总27页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC145220/D
SEMICONDUCTOR TECHNICAL DATA
F SUFFIX
SOG PACKAGE
CASE 803C
BiCMOS
20
1
The MC145220 is a low–voltage, single–chip frequency synthesizer with
serial interface capable of direct usage up to 1.1 GHz. The device simulta-
neously supports two loops. The two on–chip dual–modulus prescalers may be
independently programmed to divide by either 32/33 or 64/65.
DT SUFFIX
TSSOP
CASE 948D
20
1
The device consists of two dual–modulus prescalers, two 6–stage A
counters, two 12–stage N counters, two fully programmable 13–stage R
(reference) counters, and two lock detectors. Four phase/frequency detectors
are included: two with current source/sink outputs and two with double–ended
outputs.
ORDERING INFORMATION
MC145220F
SOG Package
MC145220DT TSSOP
The counters are programmed via a synchronous serial port which is SPI
compatible. The serial port is byte–oriented to facilitate control via an MCU. Due
to the innovative BitGrabber Plus registers, the MC145220 may be cascaded
with other peripherals featuring BitGrabber Plus without requiring leading
dummy bits or multiple address bits in the serial data stream. In addition,
BitGrabber Plus peripherals may be cascaded with existing BitGrabber
peripherals. Because this device is a dual synthesizer, a single steering bit is
used in the serial data stream to direct the data to either side of the chip.
The phase/frequency detectors have linear transfer functions (no dead
zones). The current delivered by the current source/sink outputs is controllable
via the serial port.
PIN ASSIGNMENT
REF
in
1
2
3
4
5
20
19
18
17
16
D
in
CLK
LD
PD
REF
out
LD
′
PD
out
/
φ
′/φ ′
out R
R
Rx/
φ
Rx
′
/
φ ′
V
V
GND
6
15
GND
′
Also featured are low–power standby for either one or both loops and
on–board support of an external crystal. In addition, the part may be configured
f
f
′
′
f
7
8
14
13
in
in
f
in
in
such that the REF pin accepts an external reference signal. In this
in
configuration, the REF
pin may be programmed to output the REF
in
out
frequency divided by 1, 2, 4, 8, or 16.
V+
′
V+
9
12
11
OUTPUT A
10
ENB
•
•
•
Operating Frequency: 40 to 1100 MHz
Operating Supply Voltage Range: 2.7 to 5.5 V
Supply Current: Both PLLs Operating — 12 mA Nominal
One PLL Operating, One on Standby — 6.5 mA Nominal
Both PLLs on Standby — 30 µA Maximum
Phase Detector Output Current: Up to 2 mA @ 5 V
Up to 1 mA @ 3 V
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Independent R Counters Allow Use of Different Step Sizes for Each Loop
Double–Buffered R Register — Reference and Loop Divide Ratios
Updated Simultaneously
•
•
R Counter Division Range: 1 and 10 to 8,191
Dual–Modulus Capability Provides Total Division of the VCO Frequency up
to 262,143
•
•
•
Direct Interface to Motorola SPI Data Port
Evaluation Kit Available (Part Number MC145220EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
NOTE: This product has been evaluated for operation over a wider range than 40 MHz to 1.1 GHz. If your design requires a wider
frequency range, contact your local Motorola representative for further information.
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
REV 4
1/98
TN98012300
Motorola, Inc. 1998
BLOCK DIAGRAM
32/33 OR
64/65
PRESCALER
8
7
f
f
f
f
in
V
A AND N COUNTERS
3
4
5
LD
PD
in
PHASE/
FREQUENCY
DETECTOR
PAIR
TO MUX FOR
OUTPUT A
/
φ
out
R
RATIO
18
Rx/φ
V
R
2
2
(INTERNAL)
BitGrabber Plus
A REGISTER
23 BITS
23
STBY
(INTERNAL)
2
1
2
13–STAGE
R COUNTER
UNUSED
2
REF
out
BUFFER
AND
CONTROL
BitGrabber Plus
C REGISTER
7 BITS
13
BitGrabber Plus
7
REF
in
C′
REGISTER
7 BITS
DOUBLE BUFFER
UNUSED
3
BitGrabber Plus
R REGISTER
16 BITS
Rs
Rs
13
STBY
(INTERNAL)
′
16
′
2
13–STAGE
COUNTER
R′
18
17
16
f
′
′
R
LD
′
PHASE/
FREQUENCY
DETECTOR
PAIR
PD ′/φ ′
out R
32/33 OR
64/65
PRESCALER
13
14
f
f
f
′
V
in
Rx′/φ ′
V
A′
& N
′
COUNTERS
18
′
in
RATIO
f
′
V
23
PORT
BitGrabber Plus
A′
REGISTER
23 BITS
2
f
′
R
(INTERNAL)
2
f
23
R
10
MUX
OUTPUT A
UNUSED
f
V
DATA OUT
11
20
19
ENB
24 1/2 STAGE
SHIFT REGISTER
D
in
5
ADDRESS
LOGIC AND
STORAGE
2
2
CLK
SELECT FROM
A REGISTER
(INTERNAL)
PLL / PLL
′
PIN 9 = V+ (Positive Power to the main PLL, Reference Circuit, and a portion of the Serial Port)
PIN 6 = GND (Ground to the main PLL, Reference Circuit, and a portion of the Serial Port)
PIN 12 = V+′ (Positive Power to PLL′ and a portion of the Serial Port)
PIN 15 = GND′ (Ground to PLL′ and a portion of the Serial Port)
MC145220
2
MOTOROLA
MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit.
Symbol
Parameter
DC Supply Voltage
Value
– 0.5 to + 6.0
– 0.5 to V+ + 0.5
– 0.5 to V+ + 0.5
± 10
Unit
V
V+, V+
V
in
DC Input Voltage
V
V
out
DC Output Voltage
V
I
in
DC Input Current, per Pin
DC Output Current, per Pin
mA
mA
mA
I
± 20
out
I
DC Supply Current, V+, V+ , GND, and
GND Pins
30
P
Power Dissipation, per Package
Storage Temperature
300
– 65 to + 150
260
mW
°C
D
T
stg
T
Lead Temperature, 1 mm from Case for
10 Seconds
°C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
ELECTRICAL CHARACTERISTICS
(V+ = V+ = 2.7 to 5.5 V, GND = GND , Voltages Referenced to GND, T = – 40 to 85°C, unless otherwise stated)
A
Guaranteed
Limit
Symbol
Parameter
Test Condition
Unit
V
IL
Maximum Low–Level Input Voltage
Device in Reference Mode, dc Coupled
0.3 x V+
V
(D , CLK, ENB, REF )
in
in
V
IH
Minimum High–Level Input Voltage
Device in Reference Mode, dc Coupled
0.7 x V+
V
(D , CLK, ENB, REF )
in
in
V
Minimum Hysteresis Voltage
Maximum Low–Level Output Voltage
(LD, LD , REF , Output A) Output A Not Selected as Port
(CLK, ENB)
100
0.1
mV
V
Hys
V
I
= 20 µA, Device in Reference Mode;
OL
out
out
V
OH
Minimum High–Level Output Voltage
I
= – 20 µA, Device in Reference Mode;
V+ – 0.1
V
out
(REF , Output A) Output A Not Selected as Port
out
I
I
Minimum Low–Level Output Current
Minimum Low–Level Output Current
(REF
)
)
V
= 0.3 V
0.5
0.5
mA
mA
OL
out
out
V
out
= 0.3 V; Phase/Frequency Detectors
OL
(PD /φ , PD
/φ , Rx/φ , Rx /φ
R
Configured with φ , φ Outputs
out out
R
V
V
R V
I
I
Minimum Low–Level Output Current
Minimum Low–Level Output Current
Minimum High–Level Output Current
Minimum High–Level Output Current
(Output A)
(LD, LD )
V
= 0.3 V
= 0.3 V
0.5
0.5
mA
mA
mA
mA
OL
out
V
out
OL
I
(REF
)
V
out
= V+ – 0.3 V
– 0.4
– 0.4
OH
OH
out
I
V
= V+ – 0.3 V; Phase/Frequency Detectors
out
Configured with φ , φ Outputs
(PD /φ , PD
/φ , Rx/φ , Rx /φ
R V V
)
out out
R
R
V
I
Minimum High–Level Output Current
(Output A)
V
out
= V+ – 0.3 V; Output A Not Selected as Port
– 0.4
mA
OH
I
in
Maximum Input Leakage Current
V
in
= V+ or GND; Device in XTAL Mode
± 1.0
µA
(D , CLK, ENB, REF )
in in
I
Maximum Input Current
Maximum Output Leakage Current
(PD /φ , PD
(REF )
in
V
= V+ or GND; Device in Reference Mode
± 150
± 150
µA
in
in
I
I
V
out
= V+ or GND; Phase/Frequency Detectors
nA
OZ
/φ
)
Configured with PD
Output, Output in High–
out
out out
R
R
Impedance State
Maximum Output Leakage Current
V
= V+ or GND; Output A Selected as Port;
± 5
µA
µA
OZ
out
(Output A, LD, LD ) Output in High–Impedance State
I
Maximum Standby Supply Current
V
= V+ or GND; Outputs Open; Both PLLs in
30
STBY
in
Standby Mode, Shut–Down Crystal Mode or
REF –Static–Low Reference Mode
out
= f = 1.1 GHz; both loops active;
in in
I
T
Total Operating Supply Current
f
*
mA
REF = 13 MHz @ 1 V p–p;
in
Output A = Inactive; All Outputs = No Connect;
D , ENB, CLK = V+ or GND; Phase/Frequency
in
Detectors Configured with φ , φ Outputs
R
V
* The nominal value is 12 mA. This is not a guaranteed limit.
MOTOROLA
MC145220
3
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUTS — PD
/φ AND PD ′/φ ′
out R out R
(Phase/Frequency Detectors Configured with PD
Outputs, I
≤ 2 mA @V+ = V+ = 4.5 to 5.5 V, I
≤ 1 mA @V+ = V+ = 2.7 to 4.4 V,
out
out
out
GND = GND , Voltages Referenced to GND)
Guaranteed
Limit
Parameter
Test Condition
Unit
%
Maximum Source Current Variation Part–to–Part
Maximum Sink–versus–Source Mismatch
Output Voltage Range
(Notes 3 and 4)
(Note 3)
V
= 0.5 x V+
± 20
12
out
V
out
= 0.5 x V+
%
(Note 3)
I
variation ≤ 20%
0.5 to V+ – 0.5 V
V
out
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40 to 85°C and given supply voltage within 2.7 to 5.5 V.
4. Applicable for the Rx/φ or Rx′/φ ′ reference pin tied to the GND or GND′ pin through a resistor. See Pin Descriptions for suggested resistor
V
V
values.
AC INTERFACE CHARACTERISTICS
(V+ = V+ = 2.7 to 5.5 V, GND = GND , T = – 40 to 85°C, C = 25 pF, Input t = t = 10 ns)
A
L
r
f
Guaranteed
Limit
Symbol
Parameter
Unit
f
Serial Data CLK Frequency
(Figure 1)
dc to 2.0
MHz
clk
NOTE: Refer to Clock t below
w
t
, t
Maximum Propagation Delay, CLK to Output A (Selected as Data Out)
Maximum Propagation Delay, ENB to Output A (Selected as Port)
(Figures 1 and 5)
(Figures 2 and 6)
200
200
200
ns
ns
ns
PLH PHL
t
, t
PZL PLZ
t
, t
Maximum Output Transition Time, Output A; t
only, on Output A when Selected as Port
THL
(Figures 1, 5, and 6)
TLH THL
C
Maximum Input Capacitance — D , CLK, ENB
in
10
pF
in
TIMING REQUIREMENTS (V+ = V+ = 2.7 to 5.5 V, GND = GND , T = – 40 to 85°C, Input t = t = 10 ns unless otherwise indicated)
A
r
f
Guaranteed
Limit
Symbol
Parameter
Minimum Setup and Hold Times, D versus CLK
Unit
ns
t , t
su
(Figure 3)
(Figure 4)
(Figure 4)
(Figure 1)
(Figure 1)
50
100
*
h
in
t
, t , t
Minimum Setup, Hold, and Recovery Times, ENB versus CLK
Minimum Pulse Width, ENB
ns
su
h
rec
t
cycles
ns
w
w
t
Minimum Pulse Width, CLK
250
100
t , t
r f
Maximum Input Rise and Fall Times — CLK
µs
* The minimum limit is 3 REF cycles or 195 f or f ′ cycles with selection of a 64/65 prescale ratio or 99 f or f ′ cycles with selection of a 32/33
in
in
in
in
in
prescale ratio, whichever is greater.
MC145220
4
MOTOROLA
t
t
r
f
V+
90%
50%
10%
CLK
V+
GND
50%
ENB
t
t
GND
w
w
1/f
clk
t
t
PHL
t
t
PZL
PLH
PLZ
90%
50%
10%
OUTPUT A
(DATA OUT)
50%
OUTPUT A
10%
t
t
THL
TLH
Figure 1.
Figure 2.
t
t
w
w
VALID
V+
V+
ENB
CLK
50%
50%
D
in
GND
GND
t
t
h
su
t
t
t
rec
su
h
V+
V+
50%
CLK
50%
GND
FIRST
LAST
CLOCK
GND
CLOCK
Figure 3.
Figure 4.
V+
TEST POINT
TEST POINT
7.5 k
Ω
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C *
C *
L
L
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 5.
Figure 6.
MOTOROLA
MC145220
5
LOOP SPECIFICATIONS (V+ = V+ = 2.7 to 5.5 V unless otherwise indicated, GND = GND , T = – 40 to 85°C)
A
Guaranteed
Operating Range
Symbol
Parameter
Input Sensitivity Range, f
Test Condition
Min
Max
Unit
P
in
f (Figure 7)
in or in
40 MHz ≤ frequency < 300 MHz
300 MHz ≤ frequency < 700 MHz
700 MHz ≤ frequency < 1100 MHz
– 2
– 5
– 16
8
6
4
dBm*
∆P
in
Difference Allowed Between f and f
in in
10
27
dB
dB
—
Isolation Between f and f
in in
15
4
f
Input Frequency, REF Externally Driven in
in
Reference Mode (Figure 8)
V
≥ 400 mV p–p, R Counter set to divide
ref
in
ratio such that f ≤ 1 MHz, REF Counter set
R
to divide ratio such that REF
out
≤ 5 MHz
MHz
MHz
f
Crystal Frequency, Crystal Mode (Figure 9)
C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
Capacitance; R Counter and REF Counter
XTAL
same as above
V+ = 2.7 V
2
2
2
2
10
13
15
15
V+ = 3.5 V
V+ = 4.5 V
V+ = 5.5 V
f
Output Frequency, REF
(Figures 10 and 12)
C = 25 pF
L
dc
dc
16
5
1
MHz
MHz
ns
out
out
Operating Frequency of the Phase Detectors
Output Pulse Width, φ , φ , φ
f
t
w
φ
f
R
in Phase with f , C = 25 pF
125
R
V,
R
V
V
L
(Figures 11 and 12)
C
Input Capacitance, REF
—
5
pF
in
in
* Power level at the input to the dc block.
MC145220
6
MOTOROLA
SINE WAVE
GENERATOR
DC
BLOCK
TEST
POINT
50
Ω PAD
OUTPUT A
f
f
(f )
in
v
DEVICE
UNDER
TEST
50
Ω
in
GND
V+
GND V+
NOTE: Alternately, the 50 Ω pad may be a T network.
Figure 7. Test Circuit
SINE WAVE
GENERATOR
TEST
POINT
0.01 µF
OUTPUT A
REF
in
(f
)
R
DEVICE
UNDER
TEST
50
Ω
TEST
POINT
50
Ω*
V
REF
out
in
GND
V+
GND V+
* Characteristic Impedance
Figure 8. Test Circuit — Reference Mode
TEST
POINT
REF
REF
OUTPUT A
in
(f
)
R
C1
DEVICE
UNDER
TEST
out
1 / f
out
C2
GND
V+
GND V+
REF
out
50%
Figure 10. Switching Waveform
Figure 9. Test Circuit — Crystal Mode
TEST POINT
DEVICE
UNDER
TEST
t
w
C *
L
50%
OUTPUT
* Includes all probe and fixture capacitance.
Figure 11. Switching Waveform
Figure 12. Test Circuit
MOTOROLA
MC145220
7
A
B
f
(PIN 8)
in
SOG PACKAGE
C
D
–j2
PIN 8) – SOG PACKAGE
Impedance (Ω)
Point
3 V Supply
1900 – j 157
1440 – j 228
552 – j 380
5 V Supply
1970 – j 102
1510 + j 19
671 – j 334
A
B
C
–j1
D
196 – j 141
223 – j 147
G
F
E
f
′ (PIN 13)
in
SOG PACKAGE
H
–j2
(PIN 13) – SOG PACKAGE
Impedance (Ω)
Point
3 V Supply
1900 + j 149
878 + j 703
705 + j 208
5 V Supply
1930 + j 214
746 + j 741
626 + j 327
E
F
–j1
G
H
215 – j 69.3
243 – j 61.3
Figure 13. Nominal Input Impedance of f and f ′ — Series Format (R + jX)
in
in
(50 – 1100 MHz)
MC145220
8
MOTOROLA
CLK
PIN DESCRIPTIONS
Serial Data Clock Input (Pin 19)
DIGITAL INTERFACE PINS
Low–to–high transitions on CLK shift bits available at the
D
in
D
pin, while high–to–low transitions shift bits from Output A
in
Serial Data Input (Pin 20)
(when configured as Data Out, see Pin 10). The 24–1/2
stage shift register is static, allowing clock rates down to dc in
a continuous or intermittent mode.
The bit stream begins with the MSB and is shifted in on the
low–to–high transition of CLK. The bit pattern is 1 byte (8
bits) long to access the C or configuration registers, 2 bytes
(16 bits) to access the first buffer of the R registers, or
3 bytes (24 bits) to access the A registers (see Table 1). The
values in the registers do not change during shifting because
the transfer of data to the registers is controlled by ENB.
Eight clock cycles are required to access the C registers.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A regis-
ters. See Table 1 and Figures 14, 15, and 16. The number of
clocks required for cascaded devices is shown in Figures 25
through 27.
CLK typically switches near 50% of V+ and has a Schmitt–
triggered input buffer. Slow CLK rise and fall times are al-
lowed. See the last paragraph of D for more information.
NOTE
The value programmed for the N counter must be
greater than or equal to the value of the A counter.
in
The 13 LSBs of the R registers are double–buffered. As in-
dicated above, data is latched into the first buffer on a 16–bit
transfer. (The 3 MSBs are not double–buffered and have an
immediate effect after a 16–bit transfer.) The two second
buffers of the R register contain the two 13–bit divide ratios
for the R counters. These second buffers are loaded with the
contents of the first buffer as follows. Whenever the A regis-
ter is loaded, the Rs (second) buffer is loaded from the R
(first) buffer. Similarly, whenever the A register is loaded, the
Rs (second) buffer is updated from the R (first) buffer. This
allows presenting new values to the R, A, and N counters
simultaneously. Note that two different R counter divide
ratios may be established: one for the main PLL and another
for PLL .
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
GND (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK be-
ing a don’t care) during power–up. Floating, tog-
gling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
Afterthesetwoaccesses, thetwocascadedchips
perform normally.
The bit stream does not need address bits due to the inno-
vative BitGrabber Plus registers. A steering bit is used to
direct data to either the main PLL or PLL section of the chip.
Data is retained in the registers over a supply range of 2.7 to
5.5 V. The formats are shown in Figures 14, 15, and 16.
ENB
Active–Low Enable Input (Pin 11)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inac-
tive high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is
D
typically switches near 50% of V+ to maximize noise
in
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
made via D and CLK, and ENB is taken back high. The
in
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 1.
the resistor are worst–case I
mum tolerable power consumption, and maximum data rate.
of the driving device, maxi-
OL
NOTE
Table 1. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Transitions on ENB must not be attempted while
CLK is high. This puts the device out of synchro-
nization with the microcontroller. Resynchro-
nization occurs whenever ENB is high and CLK is
low.
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
C Registers
R Register,
First Buffer
A Registers
Not Allowed
See Figures
24 to 27
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
This input is Schmitt–triggered and switches near 50% of
V+, thereby minimizing the chance of loading erroneous data
24
A23, A22, A21, . . ., A0
Other Values ≤ 32
Values > 32
into the registers. See the last paragraph of D for more
in
information.
For POR information, see the note for the CLK pin.
MOTOROLA
MC145220
9
OUTPUT A
Configurable Digital Output (Pin 10)
values, as recommended by the crystal supplier, are con-
nected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external re-
sistor of 1 MΩ to 15 MΩ is connected directly across the pins
to ensure linear operation of the amplifier. The required con-
nections for the crystal are shown in Figure 9. To turn on the
oscillator, bits R15, R14, and R13 must have an octal value
of one (001 in binary). This is the active–crystal mode shown
in Figure 16. In this mode, the crystal oscillator runs and the
R Counter divides the crystal frequency, unless the part is in
standby. If the part is placed in standby via the C or C′ regis-
ter, the oscillator runs, but the R or R′ counter is stopped, re-
spectively. However, if bits R15 to R13 have a value of 0, the
oscillator is stopped, which saves additional power. This is
the shut–down crystal mode shown in Figure 16, and can be
engaged whether in standby or not.
Output A is selectable as f , f , f , f , Data Out, or Port.
R V R
V
Bits A21 and A22 and the steering bit (A23) control the selec-
tion; see Figure 15. When selected as Port, the pin becomes
an open–drain N–channel MOSFET output. As such, a
pullup device is needed for pin 10. With all other selections,
the pin is a totem–pole (push–pull) output.
If A22 = A21 = high, Output A is configured as f when the
steering bit is low and f when the bit is high. These signals
R
are the buffered outputs of the 13–stage R counters. The sig-
nals appear as normally low and pulse high. The signals can
be used to verify the divide ratios of the R counters. These
ratios extend from 10 to 8191 and are determined by the
binary value loaded into bits R0 – R12 in the R register. Also,
direct access to the phase detectors via the REF pin is
allowed by choosing a divide value of one. See Figure 16.
The maximum frequency at which the phase detectors oper-
ate is 1 MHz. Therefore, the frequency of f and f should
not exceed 1 MHz.
If A22 = high and A21 = low, Output A is configured as f
R
in
In the reference mode, REF (pin 1) accepts a signal from
in
an external reference oscillator, such as a TCXO. A signal
swinging from at least the V to V levels listed in the Elec-
IL IH
R
R
trical Characteristics table may be directly coupled to the
pin. If the signal is less than this level, ac coupling must be
used as shown in Figure 8. The ac–coupled signal must be at
least 400 mV p–p. Due to an on–board resistor which is
engaged in the reference modes, an external biasing resistor
V
when the steering bit is low and f when the bit is high.
V
These signals are the buffered outputs of the 12–stage N
counters. The signals appear as normally low and pulse
high. The signals can be used to verify the operation of the
prescalers, A counters, and N counters. The divide ratio be-
tied between REF and REF
is not required.
in
out
With the reference mode, the REF
pin is configured as
out
the output of a divider. As an example, if bits R15, R14,
and R13 have an octal value of seven, the frequency at
tween the f or f ′ input and the f or f signal is N x P + A.
in in
V
V
N is the divide ratio of the N counter, P is 32 with a 32/33
prescale ratio or 64 with a 64/65 prescale ratio, and A is the
divide ratio of the A counter. These ratios are determined by
bits loaded into the A registers. See Figure 15. The maxi-
mum frequency at which the phase detectors operate is
REF
is the REF frequency divided by 16. In addition,
out
in
Figure 16 shows how to obtain ratios of eight, four, and two.
A ratio of one–to–one can be obtained with an octal value of
three. Upon power up, a ratio of eight is automatically in-
itialized. The maximum frequency capability of the REF
out
to V ) and 25 pF
loads. Therefore, for REF frequencies above 5 MHz, the
in
one–to–one ratio may not be used for these large signal
1 MHz. Therefore, the frequency of f and f should not
exceed 1 MHz.
V
V
pin is 5 MHz for large output swings (V
OH
OL
If A22 = low and A21 = high, Output A is configured as
Data Out. This signal is the serial output of the 24–1/2 stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, Output A is
automatically configured as Data Out to facilitate cascading
devices.
If A22 = A21 = low, Output A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high impedance when
the Port bit is high. See Figure 14.
swing and large C requirements. Likewise, for REF fre-
L
in
quencies above 10 MHz, the ratio must be more than two.
If REF is unused, an octal value of two should be used
out
for R15, R14, and R13 and the REF
pin should be
out
floated. A value of two allows REF to be functional while
in
, which minimizes dynamic power con-
sumption and electromagnetic interference (EMI).
disabling REF
out
LOOP PINS
f
, f and f , f
in in
in in
Frequency Inputs (Pins 8, 7 and 13, 14)
REFERENCE PINS
These pins feed the onboard RF amplifiers which drive the
prescalers. These inputs may be fed differentially. However,
they usually are used in single–ended configurations (shown
REF and REF
in
out
Reference Oscillator Input and Output (Pins 1 and 2)
Configurable Pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In the crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–reso-
nant crystal. Frequency–setting capacitors of appropriate
in Figure 7). Note that f is driven while f must be tied to ac
ground (via capacitor). The signal sources driving these pins
originate from external VCOs.
in in
Motorola does not recommend driving f while terminating
in
f
in
because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
MC145220
10
MOTOROLA
PD
/φ , PD
out
/φ
R
These outputs can be enabled, disabled, or interchanged
via C register bits C6 or C0. This is a patented feature. Note
that when disabled in standby, these outputs are forced to
their rest condition (high state). See Figure 14.
out
R
Single–Ended Phase/Frequency Detector Outputs
(Pins 4 and 17)
When the C2 bits in the C or C registers are low, these
pins are independently configured as single–ended outputs
PD
The φ and φ output signals swing from approximately
R
V
GND to V+.
or PD
, respectively. As such, each pin is a three–
out
out
state current–source/sink output for use as a loop error sig-
nal when combined with an external low–pass filter. The
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
LD and LD
Lock Detector Outputs (Pins 3 and 18)
Each output is essentially at a high–impedance state with
very narrow low–going pulses of a few nanoseconds when
the respective loop is locked (f and f of the same phase
R
V
POL bit (C0) in the C register = low (see Figure 14)
and frequency). The output pulses low when f and f are
V
R
Frequency of f > f or Phase of f Leading f : current–
V
R
V
R
out of phase or different frequencies. LD is the logical AND-
ing of φ and φ , while LD is the logical ANDing of φ and
sinking pulses from a floating state
Frequency of f < f or Phase of f Lagging f : current–
R
V
R
V
R
V
R
φ
V
. See Figure 17.
sourcing pulses from a floating state
Frequency and Phase of f = f : essentially a floating
Upon power up, on–chip initialization circuitry forces LD
V
R
and LD to the high–impedance state. These pins are low
during standby. If unused, LD should be tied to GND and LD
should be tied to GND .
These outputs have open–drain N–channel MOSFET driv-
ers. This facilitates a wired–OR function. See Figure 21.
state; voltage at pin determined by loop filter
POL bit (C0) = high
Frequency of f > f or Phase of f Leading f : current–
V
R
V
R
sourcing pulses from a floating state
Frequency of f < f or Phase of f Lagging f : current–
V
R
V
R
sinking pulses from a floating state
Frequency and Phase of f = f : essentially a floating
Rx/φ and Rx /φ
V
V
External Current Setting Resistors (Pins 5 and 16)
V
R
state; voltage at pin determined by loop filter
When the C2 bits in the C or C registers are low, these two
pins are independently configured as current setting pins Rx
or Rx , respectively. As such, resistors tied between each of
these pins and GND and GND , in conjunction with bits C4
and C5 in the C and C registers, determine the amount of
current that the PD
and C5 are both set high, the maximum current is obtained;
see Table 2 for other values of current.
These outputs can be enabled, disabled, and inverted via
the C and C registers. If desired, these pins can be forced to
the floating state by utilization of the standby feature in the C
or C registers (bit C6). This is a patented feature.
The phase detector gain is controllable by bits C4 and C5:
pins sink and source. When bits C4
out
gain (in amps per radian) = PD
by 2π.
current in amps divided
out
Table 2. PD
C5
or PD
out
′ Current
out
PD
/φ , Rx/ φ and PD
/φ , Rx /φ
out R V
Double–Ended Phase/Frequency Detector Outputs
(Pins 4, 5 and 17, 16)
out
R
V
C4
Current
0
0
1
1
0
1
0
1
5%
50%
80%
100%
When the C2 bits in the C or C registers are high, these
two pairs of pins are independently configured as double–
ended outputs φ , φ or φ , φ , respectively. As such,
R
V
R
V
these outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detectors
are described below and are shown in Figure 17.
The formula for determining the value of Rx or Rx is as
follows.
V1 – V2
I
Rx =
where Rx is the value of external resistor in ohms, V1 is the
supply voltage, V2 is 1.5 V for a reference current through Rx
of 100 µA or 1.745 V for a reference current of 200 µA, and I
is the reference current flowing through Rx or Rx .
The reference current flowing through Rx or Rx′ is multi-
plied by a factor of approximately 10 (in the 100% current
POL bit (C0) in the C register = low (see Figure 14)
Frequency of f > f or Phase of f Leading f : φ
=
=
V
R
R
R
R
V
R
V
negative pulses, φ = essentially high
Frequency of f < f or Phase of f Lagging f : φ
V
V
R
V
essentially high, φ = negative pulses
mode)anddeliveredbythePD
or PD
′ pin, respectively.
out
out
Frequency and Phase of f = f : φ and φ remain
essentially high, except for a small minimum time period
when both pulse low in phase
V
R
V
R
To achieve a maximum phase detector output current of
1 mA, the resistor should be about 15 kΩ when a 3 V supply
is employed. See Table 3.
POL bit (C0) = high
Frequency of f > f or Phase of f Leading f : φ
=
=
Table 3. Rx Values
V
R
V
R
R
negative pulses, φ = essentially high
V
PD
out
or PD
out
′
Frequency of f < f or Phase of f Lagging f : φ
V
R
V
R
R
Supply
Voltage
Current in
essentially high, φ = negative pulses
V
100% Mode
Rx
Frequency and Phase of f = f : φ and φ remain
V
R
V
R
3 V
5 V
15 kΩ
16 kΩ
1 mA
2 mA
essentially high, except for a small minimum time period
when both pulse low in phase
MOTOROLA
MC145220
11
Do not use a decoupling capacitor on the Rx or Rx pin.
Use of a capacitor causes undesirable current spikes to ap-
pear on the phase detector output when invoking the standby
mode.
For optimum performance, V+ should be bypassed to
GND and V+ bypassed to GND using separate low–induc-
tance capacitors mounted very close to the MC145220. Lead
lengths and printed circuit board traces to the capacitors
should be minimized. (The very fast switching speed of the
device can cause excessive current spikes on the power
leads if they are improperly bypassed.)
POWER SUPPLY PINS
V+ and V+
Positive Supply Potentials (Pins 9 and 12)
V+ supplies power to the main PLL, reference circuit, and
a portion of the serial port. V+ supplies power to PLL and a
portion of the serial port. Both V+ and V+ must be at the
same voltage level and may range from 2.7 V to 5.5 V with
respect to the GND and GND pins.
GND and GND
Grounds (Pins 6 and 15)
The GND pin is the ground for the main PLL and GND is
the ground for PLL .
MC145220
12
MOTOROLA
ENB
CLK
*
1
2
3
4
5
6
7
8
MSB
C7
LSB
C0
C6
C5
C4
C3
C2
C1
D
in
* At this point, the new byte is transferred to the C or C register and stored. No other registers are affected.
C7 – Steer: Used to direct the data to either the C or C register. A low level directs data to the C register; a high
level is for the C register.
C6 – Standby: When set high, places both the main PLL and PLL (when C6 is set in the C register) or PLL only
(when C6 is set in the C register) in the standby mode for reduced power consumption. The associated
PD
is forced to the floating state, the associated counters (A, N, and R) are inhibited from counting,
out
the associated Rx current is shut off, and the associated prescaler stops counting and is placed in
a low current mode. The associated double–ended phase/frequency detector outputs are forced to
a high level. In standby, the associated LD output is placed in the low–state, thus indicating “not locked”
(open loop). During standby, data is retained in all registers and any register may be accessed.
In standby, the condition of the REF/OSC circuitry is determined by bits R13, R14, and R15 in the
R register per Figure 16. However, if REF
= static low is selected, the internal feedback resistor
out
is disconnected and the REF is inhibited when both PLL and PLL are placed in standby via the
in
C register. Thus, the REF only presents a capacitive load. Note: PLL/PLL standby does not affect
in
the other modes of the REF/OSC circuitry as determined by bits R13, R14, and R15 in the R register.
The PLL standby mode (controlled from the C register) has no effect on the REF/OSC circuit.
When C6 is reset low, the associated PLL (or PLLs) is (are) taken out of standby in two steps. First,
the REF (only in 1 mode, PLL/PLL in standby) resistor is reconnected, REF (only 1 mode) is gated
in in
on, all counters are enabled, and the Rx current is enabled. Any f and f signals are inhibited from
R
V
toggling the phase/frequency detectors and lock detectors. Second, when the appropriate f pulse
R
occurs, the A and N counters are jam loaded, the prescaler is gated on, and the phase/frequency
and lock detectors are initialized. Immediately after the jam load, the A, N, and R counters begin counting
down together. At this point, the f and f pulses are enabled to the phase and lock detectors. (Patented
R
V
feature.)
C5, C4 – I2, I1: Independently controls the PD
or PD ′ source/sink current per Table 2. With both bits high, the
out
out
maximum current (as set by Rx or Rx′) is available. POR forces C5 and C4 to high levels.
C3 – Spare: Unused
C2 – PDA/B: Independently selects which phase/frequency detector is to be used. When set high, the double–ended
detector is selected with outputs φ and φ or φ and φ . When reset low, the current source/sink
R
V
or PD
R
out
V
detector is selected with outputs PD
. In the second case, the appropriate Rx or Rx pin
out
is tied to an external resistor. POR forces C2 low.
C1 – Port: When the Output A pin is selected as “Port” via bits A22 and A21, C1 of the C register determines
the state of Output A. When C1 is set high, Output A is forced to the high–impedance state; C1 low
forces Output A low. The Port bit is not affected by the standby mode. Note: C1 of the C register
is not used in any mode.
C0 – POL: Selects the output polarity of the associated phase/frequency detectors. When set high, this bit inverts
the associated current source/sink output and interchanges the associated double–ended output relative
to the waveforms in Figure 17. Also, see the phase detector output pin descriptions for more information.
This bit is cleared low at power up.
Figure 14. C and C Register Accesses and Format (8 Clock Cycles are Used)
MOTOROLA
MC145220
13
Figure 15. A and A Register Accesses and Format (24 Clock Cycles are Used)
MC145220
14
MOTOROLA
ENB
CLK
NOTE
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB
R15
LSB
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
D
in
0
1
2
CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
0
0
0
0
0
0
0
0
0
0
0
0
0
·
0
0
0
0
0
0
0
0
0
0
0
0
0
0
·
0
1
2
3
4
5
6
7
8
9
A
B
C
·
NOT ALLOWED
0
0
0
0
0
0
0
0
0
0
0
0
·
R COUNTER =
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
÷
1 (NOTE 6)
REFERENCE MODE, REF ENABLED AND REF
in
out
STATIC LOW
3
4
5
6
7
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
= REF (BUFFERED)
in
out
out
out
out
out
= REF /2
in
in
in
= REF /4
= REF /8 (NOTE 3)
= REF /16
in
OCTAL VALUE
R COUNTER =
R COUNTER =
R COUNTER =
÷
÷
÷
10
11
12
·
·
·
·
·
·
·
·
1
1
F
F
F
F
E
F
R COUNTER =
R COUNTER =
÷
÷
8190
8191
BINARY VALUE
HEXADECIMAL VALUE
NOTES:
1. Bits R15 – R13 control the configurable “Buffer and Control” block (see Block Diagram).
2. Bits R12 – R0 control the “13–stage R counter” blocks (see Block Diagram).
3. A power–on initialize circuit forces a default REF to REF
ratio of eight.
in
out
4. At this point, bits R13, R14, and R15 are stored and sent to the “Buffer and Control” block in the Block Diagram. Bits R0 – R12 are loaded
into the first buffer in the double–buffered section of the R register. Therefore, the R or R′ counter divide ratio is not altered yet and retains
the previous ratio loaded. The C, C , A, and A registers are not affected.
5. Bits R0 – R12 are transferred to the second buffer of the R register (Rs in the Block Diagram) on a subsequent 24–bit write to the A
register. The bits are transferred to Rs on a subsequent 24–bit write to the A register. The respective R counter begins dividing by the
new ratio after completing the rest of its present count cycle.
6. Allows direct access to reference input of phase/frequency detectors.
Figure 16. R Register Access and Format (16 Clock Cycles are Used)
MOTOROLA
MC145220
15
f
R
V
V
H
REFERENCE
REF
÷
R
in
L
f
V
V
V
H
FEEDBACK
÷ (N x P + A)
f
in
L
NOTE 1
SOURCING CURRENT
FLOAT
PD
out
SINKING CURRENT
V
V
H
φ
R
L
V
V
H
φ
V
L
HIGH IMPEDANCE
LD
V
L
NOTES:
1. At this point, when both f and f are in phase, the output source and sink circuits are turned on for a short interval.
R
V
2. The PD
either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output
out
is mostly in a floating condition and the voltage at that pin is determined by the low–pass filter capacitor. PD , φ , and φ
out
R
V
are shown with the polarity bit (POL) = low; see Figure 14 for POL.
3. V = High voltage level, V = Low voltage level.
H
L
4. The waveforms are applicable to both the main PLL and PLL′.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms
MC145220
16
MOTOROLA
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output fre-
The following options may be considered to provide a ref-
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
quency (f ) at Output A as a function of supply voltage.
R
Use of a Hybrid Crystal Oscillator
(REF
is not used because loading impacts the oscillator.)
out
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in fre-
quency or becomes unstable with an increase in supply volt-
age. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
Note that the oscillator start–up time is proportional to the
value of R1.
dc coupled to REF . If the oscillator does not have CMOS
in
logic levels on the outputs, capacitive or ac coupling to REF
must be used. See Figure 8.
in
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful.
See Table 4.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
FREQUENCY
SYNTHESIZER
REF . (See Figure 8.) For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
in
REF
in
REF
out
R
f
Use of the On–Chip Oscillator Circuitry
R1*
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.
C1
C2
* May be needed in certain cases. See text.
The crystal should be specified for a loading capacitance,
Figure 18. Pierce Crystal Oscillator Circuit
C , which does not exceed approximately 20 pF when used
L
near the highest operating frequency of the MC145220.
Ca
Assuming R1 = 0 Ω, the shunt load capacitance, C , pres-
L
REF
in
REF
out
ented across the crystal can be estimated to be:
C C
in out
C1 • C2
C1 + C2
C
in
C
C =
L
+ C + C
+
stray
out
a
C
+ C
in
out
where
C
stray
C
= 5 pF (see Figure 19)
= 6 pF (see Figure 19)
in
C
out
Figure 19. Parasitic Capacitances of the
Amplifier and C
C = 1 pF (see Figure 19)
a
stray
C1 and C2 = external capacitors (see Figure 18)
C
= the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
stray
C
S
R
L
S
S
1
2
1
2
The oscillator can be “trimmed” on–frequency by making
either a portion or all of C1 variable. The crystal and associ-
ated components must be located as close as possible to the
C
REF and REF
pins to minimize distortion, stray ca-
O
in
out
pacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
R
X
e
e
2
1
appropriate stray value to the values for C and C . For
in out
this approach, the term C
becomes zero in the above
stray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
expression for C .
L
Power is dissipated in the effective series resistance of the
crystal, R , in Figure 20. The maximum drive level specified
e
Figure 20. Equivalent Crystal Networks
by the crystal manufacturer represents the maximum stress
MOTOROLA
MC145220
17
RECOMMENDED READING
Control”, Electro–Technology, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Table 4. Partial List of Crystal Manufacturers
Motorola — Internet Address http://motorola.com (Search for resonators)
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend one supplier over another and in no way suggests
that this is a complete listing of crystal manufacturers.
MC145220
18
MOTOROLA
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
K
K
φ
VCO
PD
out
VCO
(A)
ω
=
=
n
NC
R
ω
RC
2
K
K
C
R
2
n
φ
VCO
ζ
=
C
N
1 + sRC
sC
Z(s) =
NOTE:
For (A), using K in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/
φ
filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ω = 1/RC′ should be
c
chosen such that ω is not significantly affected.
n
R
2
K
K
φ
VCO
(B)
ω
=
=
n
NCR
1
R
R
C
1
φ
R
–
A
VCO
ω
R C
2
n
φ
+
ζ
V
2
1
R
ASSUMING GAIN A IS VERY LARGE, THEN:
2
R sC + 1
2
C
Z(s) =
R sC
1
NOTE:
For (B), R is frequently split into two series resistors; each resistor is equal to R divided by 2. A capacitor C is then placed from the
1
1
C
midpoint to ground to further filter the error pulses. The value of C should be such that the corner frequency of this network does not
C
significantly affect ω .
n
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K
φ
K
φ
(Phase Detector Gain) = I
(Phase Detector Gain) = V+/2π volts per radian for φ and φ
/2π amps per radian for PD
PDout
out
R
V
2π∆f
VCO
K
VCO
(VCO Transfer Function) =
radians per volt
∆V
VCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ω ≈ (2πf /50)
n
R
where f is the frequency at the phase detector input. Larger ω values result in faster loop lock times and, for similar sideband filtering,
R
R
n
higher f –related VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate f –related VCO sidebands. This
R
additional filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253, An Improved PLL Design Method Without ω and ζ, Motorola Semiconductor Products, Inc., 1995.
n
MOTOROLA
MC145220
19
+V
NOTE 6
NOTE 5
Q1
R1
+V
MC145220
1
2
REF
REF
D
20
in
in
MCU
19
CLK
LD
out
3
4
18
LD
LOW–PASS
FILTER
17
LOW–PASS
FILTER
PD
out
/
φ
PD /φ
out R
R
′
5
6
16
15
Rx/
φ
Rx /φ
V
V
GND
GND
VCO
VCO′
7
14
f
f
in
in
in
in
8
9
13
12
f
f
+V
+V
BUFFER
BUFFER′
V+
V+
NOTE 4
10
11
OUTPUT
OUTPUT′
OUTPUT A
(PORT)
ENB
GENERAL PURPOSE
DIGITAL OUTPUT
NOTES:
1. ThePD
out
outputisfedtoanexternalloopfilter. SeethePhase–LockedLoop — Low–PassFilterDesignpageforadditionalinforma-
tion.
2. For optimum performance, bypass the V+ and V+ pins to GND and GND with low–inductance capacitors.
3. The R counter is programmed for a divide value = REF /f . Typically, f is the tuning resolution required for the VCO. Also, the VCO
in
R
R
frequency divided by f = N = N P + A; this determines the values (N, A) that must be programmed into the N and A counters,
R
T
respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).
4. Pull–up voltage must be at the same potential as the V+ pin or less. Pull–up device other than a resistor may be used. (Pull–up device
not required when Output A is configured as f , f ′, f , f ′, DATA OUT.)
R
R
V V
5. LD and LD′ are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”.
6. Use of Q1 is optional and depends on loading.
Figure 21. Application Showing Use of the Two Single–Ended Phase/Frequency Detectors
MC145220
20
MOTOROLA
+V
NOTE 6
NOTE 5
Q1
R1
+V
MC145220
1
2
REF
REF
D
20
in
in
MCU
19
CLK
LD
out
3
4
18
LD
LOW–PASS
FILTER
17
LOW–PASS
FILTER
PD
out
/
φ
PD /φ
out R
R
′
5
6
16
15
Rx/
φ
Rx /φ
V
V
GND
GND
VCO
VCO′
7
14
f
f
in
in
in
in
8
9
13
12
f
f
+V
+V
BUFFER
BUFFER′
V+
V+
NOTE 4
10
11
OUTPUT
OUTPUT′
OUTPUT A
(PORT)
ENB
GENERAL PURPOSE
DIGITAL OUTPUT
NOTES:
1. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
R
V
foradditionalinformation.Theφ andφ outputsswingrail–to–rail.Therefore,theusershouldbecarefulnottoexceedthecommon
R
V
mode input range of the op amp used in the combiner/loop filter.
2. For optimum performance, bypass the V+ and V+ pins to GND and GND with low–inductance capacitors.
3. The R counter is programmed for a divide value = REF /f . Typically, f is the tuning resolution required for the VCO. Also, the
in
R
R
VCOfrequencydividedbyf =N =N P+A;thisdeterminesthevalues(N,A)thatmustbeprogrammedintotheNandAcounters,
R
T
respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).
4. Pull–up voltage must be at the same potential as the V+ pin or less. Pull–up device other than a resistor may be used. (Pull–up
device not required when Output A is configured as f , f ′, f , f ′, DATA OUT.)
R
R
V V
5. LD and LD′ areopen–drainoutputs. Thisallowsthewired–ORconfigurationshown. NotethatR1andQ1formthe“pull–updevice”.
6. Use of Q1 is optional and depends on loading.
Figure 22. Application Showing Use of the Two Double–Ended Phase/Frequency Detectors
MOTOROLA
MC145220
21
+V
NOTE 6
NOTE 5
Q1
R1
+V
MC145220
1
2
REF
REF
D
20
in
in
MCU
19
CLK
LD
out
3
4
18
LD
LOW–PASS
FILTER
17
LOW–PASS
FILTER
PD
out
/
φ
PD ′/φ ′
out R
R
′
5
6
16
15
Rx/
φ
Rx /φ
V
V
GND
GND
VCO
VCO′
7
14
f
f
in
in
in
in
8
9
13
12
f
f
+V
+V
BUFFER
BUFFER′
V+
V+
NOTE 4
10
11
OUTPUT
OUTPUT
′
OUTPUT A
(PORT)
ENB
GENERAL PURPOSE
DIGITAL OUTPUT
NOTES:
1. See the Phase–Locked Loop — Low–Pass Filter Design page for additional information.
2. For optimum performance, bypass the V+ and V+ pins to GND and GND with low–inductance capacitors.
3. The R counter is programmed for a divide value = REF /f . Typically, f is the tuning resolution required for the VCO. Also, the
in
R
R
VCOfrequencydividedbyf =N = N P+A;thisdeterminesthevalues(N, A)thatmustbeprogrammedintotheNandAcounters,
R
T
respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).
4. Pull–up voltage must be at the same potential as the V+ pin or less. Pull–up device other than a resistor may be used. (Pull–up
device not required when Output A is configured as f , f ′, f , f ′, DATA OUT.)
R
R
V V
5. LD and LD′ are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”.
6. Use of Q1 is optional and depends on loading.
Figure 23. Application Showing Use of Both the Single– and Double–Ended Phase/Frequency Detectors
DEVICE #1
CLK ENB
DEVICE #2
CLK ENB
OUTPUT A
(DATA OUT)
OUTPUT A
(DATA OUT)
D
D
in
in
CMOS
MCU
OPTIONAL
NOTE: See related Figures 25, 26, and 27.
Figure 24. Cascading Two Devices
MC145220
22
MOTOROLA
Figure 25. Accessing the C or C′ Registers of
Two Cascaded MC145220 Devices
(32 Clock Cycles are Used)
MOTOROLA
MC145220
23
Figure 26. Accessing the A or A′ Registers of
Two Cascaded MC145220 Devices
(48 Clock Cycles are Used)
MC145220
24
MOTOROLA
Figure 27. Accessing the R Registers of
Two Cascaded MC145220 Devices
(40 Clock Cycles are Used)
MOTOROLA
MC145220
25
PACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 803C–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
–F–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.008)
PER SIDE.
20
1
11
10
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.006) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
–B–
J
G
MILLIMETERS
INCHES
DIM
A
B
C
D
E
MIN
12.35
5.10
1.95
0.35
–––
MAX
12.80
5.45
2.05
0.50
0.81
MIN
MAX
0.504
0.215
0.081
0.020
0.032
S 10 PL
0.486
0.201
0.077
0.014
–––
M
M
0.13 (0.005)
B
N
F
12.40*
0.488*
G
H
J
K
L
M
N
S
1.15
0.59
0.18
1.10
0.05
0
1.39
0.81
0.27
1.50
0.20
10
0.045
0.023
0.007
0.043
0.001
0
0.055
0.032
0.011
0.059
0.008
10
C
0.10 (0.004)
E
L
M
D 20 PL
–T–
SEATING
PLANE
0.50
7.40
0.85
8.20
0.020
0.291
0.033
0.323
M
S
S
0.13 (0.005)
T
B
A
*APPROXIMATE
DT SUFFIX
TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)
CASE 948D–03
A
NOTES:
20 X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
0.200 (0.008)
T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
20
11
10
L
B
PIN ONE
IDENTIFICATION
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -U-.
C
MILLIMETERS
INCHES
-U-
DIM
A
B
C
D
MIN
MAX
6.60
4.50
1.05
0.25
0.55
MIN
MAX
0.260
0.177
0.041
0.010
0.022
0.100 (0.004)
SEATING
PLANE
4.30
0.95
0.05
0.45
0.169
0.037
0.002
0.018
H
G
D
J
-T-
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
A
0.275
0.09
0.09
0.16
0.16
6.30
0.375
0.24
0.18
0.32
0.26
6.50
0.010
0.004
0.004
0.006
0.006
0.248
0.015
0.009
0.007
0.013
0.010
0.256
K
K1
J1
J
M
M
0
°
10
°
0
°
10°
A
F
SECTION A-A
MC145220
26
MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
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HOME PAGE: http://motorola.com/sps/
CUSTOMER FOCUS CENTER: 1–800–521–6274
MC145220/D
◊
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