MC14015B_14 [ONSEMI]
Dual 4-Bit Static Shift Register;
| 型号： | MC14015B_14 |
| 厂家： | 
ONSEMI |
| 描述： | Dual 4-Bit Static Shift Register |
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4−bit static shift register is constructed with
MOS P−Channel and N−Channel enhancement mode devices in
a single monolithic structure. It consists of two identical, independent
4−state serial−input/parallel−output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master−slave flip−flops. Data is shifted
from one stage to the next during the positive−going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial−to−parallel conversion where low power
dissipation and/or noise immunity is desired.
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SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAM
Features
16
• Diode Protection on All Inputs
14015BG
AWLYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Flip−Flop Design
1
• Logic State is Retained Indefinitely with Clock Level either High or
Low; Information is Transferred to the Output only on the
Positive-going Edge of the Clock Pulse
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
WW, W = Work Week
G
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
−0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
T
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
500
mW
°C
D
−55 to +125
−65 to +150
260
A
T
stg
Storage Temperature Range
°C
T
Lead Temperature
°C
L
(8−Second Soldering)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V and V
in
out
should be constrained to the range V ≤ (V or V ) ≤ V .
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2014 − Rev. 9
MC14015B/D
MC14015B
PIN ASSIGNMENT
BLOCK DIAGRAM
Q0
5
C
Q3
Q2
Q1
Q0
R
1
2
3
4
5
6
7
8
16
15
14
V
DD
B
7
D
D
R
Q1
4
B
B
B
Q2
3
A
A
9
6
C
13 Q0
12 Q1
11 Q2
10 Q3
B
B
B
A
R
Q3
10
A
A
Q0
Q1
Q2
Q3
13
12
11
2
D
15
D
C
A
V
SS
9
C
A
1
R
14
V
= PIN 16
= PIN 8
DD
V
SS
TRUTH TABLE
C
D
0
R
0
0
0
1
Q0
Q
n
0
Q
Q
n−1
n−1
1
1
X
X
No Change
0
No Change
0
X
X = Don’t Care
Q = Q0, Q1, Q2, or Q3, as applicable.
n
Q
= Output of prior stage.
n−1
ORDERING INFORMATION
Device
†
Package
Shipping
MC14015BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14015BDR2G
NLV14015BDR2G*
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14015B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
−55_C
25_C
Typ
125_C
V
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or .05 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc)
“1” Level
Source
Sink
V
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
O
IH
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
5.0
5.0
10
–3.0
–0.64
–1.6
−
−
−
−
–2.4
–0.51
−1.3
−3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
−0.36
–0.9
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
–4.2
−2.4
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
DD
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
I
T
5.0
10
15
I = (1.2 mA/kHz)f + I
T
DD
DD
DD
I = (2.4 mA/kHz)f + I
T
I = (3.6 mA/kHz)f + I
T
(C = 50 pF on all outputs, all
L
buffers switching)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.002.
T
L
DD
SS
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3
MC14015B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Typ
(Note 6)
Characteristic
Output Rise and Fall Time
Symbol
V
DD
Min
Max
Unit
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
t
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
, t
TLH THL
, t
= (0.55 ns/pF) C + 9.5 ns
TLH THL
L
Propagation Delay Time
Clock, Data to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 225 ns
= (0.66 ns/pF) C + 92 ns
L
= (0.5 ns/pF) C + 65 ns
L
5.0
10
15
−
−
−
310
125
90
750
250
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Reset to Q
t
t
t
, t
= (1.7 ns/pF) C + 375 ns
= (0.66 ns/pF) C + 147 ns
L
= (0.5 ns/pF) C + 95 ns
L
5.0
10
15
−
−
−
460
180
120
750
250
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Clock Pulse Width
t
5.0
10
15
400
175
135
185
85
55
−
−
−
ns
MHz
ms
WH
Clock Pulse Frequency
Clock Pulse Rise and Fall Times
Reset Pulse Width
f
cl
5.0
10
15
−
−
−
2.0
6.0
7.5
1.5
3.0
3.75
t
, t
5.0
10
15
−
−
−
−
−
−
15
5
4
TLH THL
t
5.0
10
15
400
160
120
200
80
60
−
−
−
ns
WH
Setup Time
t
su
5.0
10
15
350
100
75
100
50
40
−
−
−
ns
5. The formulas given are for typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14015B
V
DD
0.01 mF
I
PULSE
GENERATOR
2
D
500 mF
CERAMIC
V
DD
Q0
Q1
Q2
Q3
D
C
C
L
PULSE
GENERATOR
1
C
L
C
L
R
C
L
V
SS
1
f
CLOCK
DATA
50%
Figure 1. Power Dissipation Test Circuit and Waveform
t
t
THL
TLH
V
DD
DATA
90%
50%
10%
INPUT
0 V
t
su
V
t -
DD
t
t
THL
TLH
PULSE
GENERATOR
2
V
DD
90%
50%
10%
D
C
Q0
Q1
Q2
Q3
CLOCK
INPUT
C
L
0 V
SYNC
C
L
t
t
WL
WH
PULSE
GENERATOR
1
C
L
t
t
PHL
PLH
R
C
L
90%
50%
10%
V
SS
Q0
t
t
= t
= 50% Duty Cycle
WL
WH
t
t
THL
TLH
= t
≤ 20 ns
TLH
THL
Figure 2. Switching Test Circuit and Waveforms
V
DD
PULSE
GENERATOR
2
V
DD
CLOCK
INPUT
D
C
50%
Q0
Q1
Q2
Q3
0 V
C
L
t
su
SYNC
C
L
PULSE
GENERATOR
1
C
t
h
L
R
V
C
DD
DATA
L
50%
INPUT
V
SS
0 V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
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5
MC14015B
CIRCUIT SCHEMATICS
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6
MC14015B
LOGIC DIAGRAMS
SINGLE BIT
Q
C
C
C
TO D OF
NEXT BIT
DATA
C
C
C
C
C
RESET
C
C
C
COMPLETE DEVICE
5
4
3
10
Q0
Q1
Q2
Q3
DATA INPUT BUFFER
D
7
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER
R
R
R
R
C
R
9
6
13
12
11
2
RESET INPUT BUFFER
DATA INPUT BUFFER
Q0
Q1
Q2
Q3
D
15
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER
RESET INPUT BUFFER
R
R
R
R
C
R
1
V
= PIN 16
= PIN 8
DD
V
SS
14
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7
MC14015B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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Phone: 81−3−5817−1050
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MC14015B/D
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