MC14016BCP [MOTOROLA]
Quad Analog Switch/Quad Multiplexer; 四路模拟开关/多路四核
| 型号： | MC14016BCP |
| 厂家： | 
MOTOROLA |
| 描述： | Quad Analog Switch/Quad Multiplexer |
| 文件： | 总9页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 632
The MC14016B quad bilateral switch is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
Each MC14016B consists of four independent switches capable of
controlling either digital or analog signals. The quad bilateral switch is used
in signal gating, chopper, modulator, demodulator and CMOS logic
implementation.
P SUFFIX
PLASTIC
CASE 646
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical
Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
•
•
For Lower R
MC14066B
, Use The HC4016 High–Speed CMOS Device or The
ON
T
A
= – 55° to 125°C for all packages.
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
BLOCK DIAGRAM
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
13
CONTROL 1
2
3
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
OUT 1
OUT 2
OUT 3
OUT 4
1
5
l
in
Input Current (DC or Transient),
per Control Pin
± 10
mA
IN 1
CONTROL 2
I
Switch Through Current
± 25
mA
mW
C
sw
4
6
P
D
Power Dissipation, per Package†
Storage Temperature
500
IN 2
T
stg
– 65 to + 150
260
CONTROL 3
9
T
L
Lead Temperature (8–Second Soldering)
C
8
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
IN 3
12
CONTROL 4
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
10
11
IN 4
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
V
V
= PIN 14
= PIN 7
DD
SS
voltages to this high-impedance circuit. For proper operation, V and
in
V
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
out
Unused inputs must always be tied to an appropriate logic voltage
Control
Switch
Off
level (e.g., either V
SS
or V ). Unused outputs must be left open.
DD
0 = V
SS
DD
1 = V
On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT
IN
CONTROL
LOGIC DIAGRAM RESTRICTIONS
V
≤ V ≤ V
SS
in DD
V
≤
V
≤ V
SS
out DD
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Input Voltage
Figure Symbol
Unit
Min
Max
Min
Max
Min
Max
1
V
5.0
10
15
—
—
—
—
—
—
—
—
—
1.5
1.5
1.5
0.9
0.9
0.9
—
—
—
—
—
—
Vdc
IL
IH
in
Control Input
V
5.0
10
15
—
—
—
—
—
—
3.0
8.0
13
2.0
6.0
11
—
—
—
—
—
—
—
—
—
Vdc
Input Current Control
—
—
I
15
—
±0.1
—
±0.00001 ±0.1
—
± 1.0 µAdc
Input Capacitance
Control
C
pF
in
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
5.0
5.0
0.2
—
—
—
—
—
—
—
—
—
—
—
—
Switch Input
Switch Output
Feed Through
Quiescent Current
(Per Package)
2,3
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
DD
“ON” Resistance
4,5,6
R
—
—
—
—
—
—
—
—
—
—
Ohms
ON
(V = V , R = 10 kΩ)
C
DD
L
(V = + 5.0 Vdc)
in
in
—
—
—
600
600
600
300
300
280
660
660
660
840
840
840
(V = – 5.0 Vdc) V
(V = ± 0.25 Vdc)
in
= – 5.0 Vdc
= – 7.5 Vdc
SS
5.0
7.5
10
(V = + 7.5 Vdc)
in
—
—
—
360
360
360
—
—
—
240
240
180
400
400
400
—
—
—
520
520
520
(V = – 7.5 Vdc) V
in
SS
(V = ± 0.25 Vdc)
in
(V = + 10 Vdc)
in
—
—
—
600
600
600
—
—
—
260
310
310
660
660
660
—
—
—
840
840
840
(V = + 0.25 Vdc) V
= 0 Vdc
= 0 Vdc
in
SS
(V = + 5.6 Vdc)
in
(V = + 15 Vdc)
in
—
—
—
360
360
360
—
—
—
260
260
300
400
400
400
—
—
—
520
520
520
(V = + 0.25 Vdc) V
in
SS
(V = + 9.3 Vdc)
in
15
∆ “ON” Resistance
—
—
∆R
Ohms
ON
Between any 2 circuits in a common
package
(V = V
DD
)
C
(V = ± 5.0 Vdc, V
= – 5.0 Vdc)
= – 7.5 Vdc)
5.0
7.5
—
—
—
—
—
—
15
10
—
—
—
—
—
—
in
SS
SS
(V = ± 7.5 Vdc, V
in
Input/Output Leakage Current
—
µAdc
(V = V
)
C
SS
7.5
7.5
—
—
±0.1
±0.1
—
—
±0.0015
±0.0015
±0.1
± 0.1
—
—
± 1.0
± 1.0
(V = + 7.5, V
= – 7.5 Vdc)
= + 7.5 Vdc)
in
out
(V = – 7.5, V
in out
NOTE: All unused inputs must be returned to V
DD
or V as appropriate for the circuit application.
SS
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**For voltage drops across the switch (∆V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn; i.e., the
switch
DD
DD
currentoutoftheswitchmaycontainbothV andswitchinputcomponents. ThereliabilityofthedevicewillbeunaffectedunlesstheMaximum
Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
MC14016B
66
MOTOROLA CMOS LOGIC DATA
ELECTRICAL CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
Characteristic
Propagation Delay Time (V = 0 Vdc)
Figure Symbol
Min
Typ #
Max
Unit
7
t
t
,
PLH
5.0
10
15
—
—
—
15
7.0
6.0
45
15
12
ns
SS
V
in
to V
out
PHL
(V = V , R = 10 kΩ)
DD
C
L
8
t
,
,
,
ns
Control to Output
(V 10 Vdc, R = 10 kΩ)
PHZ
t
5.0
10
15
—
—
—
34
20
15
90
45
35
PLZ
PZH
in
L
t
t
PZL
Crosstalk, Control to Output (V
= 0 Vdc)
= 10 kΩ,
9
—
5.0
10
15
—
—
—
30
50
100
—
—
—
mV
dB
SS
out
(V = V , R = 10 kΩ, R
DD in
C
f = 1.0 kHz)
Crosstalk between any two switches (V
SS
= 0 Vdc)
—
—
5.0
—
– 80
—
(R = 1.0 kΩ, f = 1.0 MHz,
L
V
out1
V
out2
crosstalk
20log
10
)
Noise Voltage (V
= 0 Vdc)
10,11
—
5.0
10
15
—
—
—
24
25
30
—
—
—
nV/√Cycle
SS
(V = V , f = 100 Hz)
C DD
(V = V , f = 100 kHz)
C DD
5.0
10
15
—
—
—
12
12
15
—
—
—
Second Harmonic Distortion (V
= – 5.0 Vdc)
—
—
—
5.0
—
0.16
—
%
SS
(V = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
in
R
= 10 kΩ, f = 1.0 kHz)
L
Insertion Loss (V = V , V = 1.77 Vdc,
DD in
12
5.0
dB
C
V
SS
= – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
V
V
out
in
I
20log
10
)
loss
—
—
—
—
2.3
0.2
0.1
—
—
—
—
(R = 1.0 kΩ)
(R = 10 kΩ)
(R = 100 kΩ)
(R = 1.0 MΩ)
L
L
L
L
0.05
Bandwidth (– 3.0 dB)
12,13
BW
5.0
5.0
MHz
(V = V , V = 1.77 Vdc, V
= – 5.0 Vdc,
C
DD in SS
RMS centered @ 0.0 Vdc)
(R = 1.0 kΩ)
—
—
—
—
54
40
38
37
—
—
—
—
L
(R = 10 kΩ)
L
(R = 100 kΩ)
L
(R = 1.0 MΩ)
L
OFF Channel Feedthrough Attenuation
(V = – 5.0 Vdc)
—
—
kHz
SS
V
V
out
in
–50dB)
(V = V , 20 log
C
SS 10
—
—
—
—
1250
140
18
—
—
—
—
(R = 1.0 kΩ)
L
(R = 10 kΩ)
L
(R = 100 kΩ)
L
2.0
(R = 1.0 MΩ)
L
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PIN ASSIGNMENT
IN 1
OUT 1
OUT 2
IN 2
1
2
3
4
14
13
12
11
V
DD
CONTROL 1
CONTROL 4
IN 4
CONTROL 2
CONTROL 3
5
6
10
9
OUT 4
OUT 3
V
7
8
IN 3
SS
MOTOROLA CMOS LOGIC DATA
MC14016B
67
V
C
I
S
V
V
out
in
V
IL
V
IL
: V is raised from V
SS
until V = V .
IL
C
C
: at V = V : I = ±10 µA with V = V , V
= V
or V = V , V
in DD out
= V
.
C
IL in SS out
S
DD
SS
V
IH
: When V = V to V , the switch is ON and the R
IH DD ON
specifications are met.
C
Figure 1. Input Voltage Test Circuit
10,000
V
= 15 Vdc
10 Vdc
5.0 Vdc
DD
V
T = 25°C
A
DD
1000
100
I
D
V
V
out
DD
TO ALL
10 k
10
4 CIRCUITS
PULSE
GENERATOR
CONTROL
INPUT
f
c
V
V
1.0
5.0 k 10 k
SS
in
100 k
1.0 M
10 M
50 M
P
= V x I
DD D
D
f , FREQUENCY (Hz)
c
Figure 2. Quiescent Power Dissipation
Test Circuit
Figure 3. Typical Power Dissipation per Circuit
(1/4 of device shown)
TYPICAL R
ON
versus INPUT VOLTAGE
700
600
700
600
R
T
= 10 kΩ
= 25°C
L
A
V
R
= 0 Vdc
SS
= 10 kΩ
L
T
= 25°C
A
500
400
300
200
500
400
V
V
= V
= 5.0 Vdc
= –5.0 Vdc
C
DD
V
= V = 10 Vdc
DD
C
SS
300
200
V
= V
= 15 Vdc
C
DD
V
V
= V
= 7.5 Vdc
C
DD
= –7.5 Vdc
SS
100
0
100
0
–10 –8.0
–4.0
0
4.0
8.0
10
0
2.0
6.0
10
14
18
20
V
, INPUT VOLTAGE (Vdc)
V
, INPUT VOLTAGE (Vdc)
in
in
Figure 4. V
SS
= – 5.0 V and – 7.5 V
Figure 5. V = 0 V
SS
MC14016B
68
MOTOROLA CMOS LOGIC DATA
V
out
R
C
L
L
V
in
V
out
20 ns
20 ns
V
R
DD
L
90%
50%
V
in
V
C
10%
V
SS
t
t
PHL
PLH
50%
V
out
V
in
Figure 6. R
Characteristics
Test Circuit
Figure 7. Propagation Delay Test Circuit
and Waveforms
ON
V
out
V
R
V
C
L
C
L
V
X
in
20 ns
V
DD
V
90%
out
50%
V
V
C
10%
10 k
15 pF
V
V
PHZ
C
SS
t
t
PZH
V
V
= V
= V
in
x
DD
SS
90%
t
10%
V
out
in
t
PZL
90%
PLZ
1 k
V
out
V
V
= V
in
x
SS
DD
10%
= V
Figure 8. Turn–On Delay Time Test Circuit
and Waveforms
Figure 9. Crosstalk Test Circuit
35
30
V
= 15 Vdc
DD
25
20
15
10
10 Vdc
5.0 Vdc
OUT
IN
QUAN–TECH
MODEL
2283
OR EQUIV
V
= V
DD
C
5.0
0
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 10. Noise Voltage Test Circuit
Figure 11. Typical Noise Characteristics
MOTOROLA CMOS LOGIC DATA
MC14016B
69
2.0
R
= 1 MΩ
AND 100 k
Ω
Ω
L
0
–2.0
–4.0
10 k
1.0 k
Ω
–3.0 dB (R = 1.0 M
Ω
Ω
)
)
L
V
out
–3.0 dB (R = 10 k
L
R
–6.0
–8.0
L
V
C
–3.0 dB (R = 1.0 k
Ω )
L
+ 2.5 Vdc
0.0 Vdc
–10
–12
V
in
– 2.5 Vdc
10 k
100 k
1.0 M
, INPUT FREQUENCY (Hz)
10 M
100 M
f
in
Figure 12. Typical Insertion Loss/Bandwidth
Characteristics
Figure 13. Frequency Response Test Circuit
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. ∆V Across Switch
MC14016B
70
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0–to–5 V
The example shows a 5 V
signal which allows no
p–p
margin at either peak. If voltage transients above V
Digital Control signal is used to directly control a 5 V
log signal.
ana-
and/or
p–p
DD
are anticipated on the analog channels, external
diodes (D ) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
below V
SS
x
The digital control logic levels are determined by V
and
volt-
DD
SS
V
. The V
voltage is the logic high voltage; the V
SS
age is logic low. For the example, V
DD
= +5 V logic high at
DD
= GND = 0 V logic low.
the control inputs; V
The absolute maximum potential difference between V
SS
The maximum analog signal level is determined by V
DD
is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
and V
DD
and V . The analog voltage must not swing higher than
SS
SS
V
or lower than V
.
V
and V
.
DD
SS
DD
SS
+5 V
V
V
SS
DD
+5.0 V
5 V
p–p
SWITCH
IN
+5 V
ANALOG SIGNAL
5 V
SWITCH
OUT
p–p
+2.5 V
GND
ANALOG SIGNAL
EXTERNAL
CMOS
0–TO–5 V DIGITAL
DIGITAL
CIRCUITRY
CONTROL SIGNALS
MC14016B
Figure A. Application Example
V
V
DD
DD
D
D
D
x
x
SWITCH
IN
SWITCH
OUT
D
x
x
V
V
SS
SS
Figure B. External Germanium or Schottky Clipping Diodes
MOTOROLA CMOS LOGIC DATA
MC14016B
71
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
7
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
–T–
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
G
N
M
D 14 PL
0.25 (0.010)
J 14 PL
0.25 (0.010)
L
M
N
0.300 BSC
7.62 BSC
0
15
0
15
M
S
T
A
M
S
T
B
0.020
0.040
0.51
1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
1
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
MC14016B
72
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE F
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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