MC10H351MELG [ONSEMI]
QUAD TTL/NMOS TO ECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20, LEAD FREE, EIAJ, SOP-20;型号: | MC10H351MELG |
厂家: | ONSEMI |
描述: | QUAD TTL/NMOS TO ECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20, LEAD FREE, EIAJ, SOP-20 光电二极管 输出元件 接口集成电路 锁存器 |
文件: | 总7页 (文件大小:145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC10H351
Quad TTL/NMOS to PECL*
Translator
Description
The MC10H351 is a quad translator for interfacing data between a
saturated logic section and the PECL section of digital systems when
only a +5.0 Vdc power supply is available. The MC10H351 has
TTL/NMOS compatible inputs and PECL complementary
open−emitter outputs that allow use as an inverting/non−inverting
translator or as a differential line driver. When the common strobe
input is at a low logic level, it forces all true outputs to the PECL low
logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic
state (≈ +4.1 V).
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MARKING DIAGRAMS*
MC10H352L
AWLYYWW
The MC10H351 can also be used with the MC10H350 to transmit
and receive TTL/NMOS information differentially via balanced
twisted pair lines.
CDIP−20
L SUFFIX
CASE 732
Features
MC10H352P
AWLYYWWG
• Single +5.0 Power Supply
• All V Pins Isolated On Chip
CC
• Differentially Drive Balanced Lines
• t = 1.3 nsec Typical
pd
• Pb−Free Packages are Available*
PDIP−20
P SUFFIX
CASE 738
10H351
ALYWG
SOEIAJ−20
CASE 967
1 20
10H351G
AWLYYWW
20
1
PLLC−20
FN SUFFIX
CASE 775
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
February, 2006 − Rev. 7
MC10H351/D
MC10H351
B IN
A IN
7
8
1
2
5
4
B OUT
B OUT
B OUT
1
2
20
19
18
17
16
15
14
13
12
11
ECL V
CC
B OUT
N.C.
C OUT
C OUT
D OUT
D OUT
A OUT
A OUT
3
A OUT
A OUT
4
D IN 12
C IN 14
16 D OUT
D OUT
5
17
19 C OUT
18 C OUT
6
V
2
CC
V
CC
COMMON
STROBE
9
B IN
7
C IN
N.C.
D IN
A IN
COMMON
STROBE
GND
8
V
(+5.0 VDC) = PINS 6, 11, 15, 20
GND = PIN 10
CC
9
10
TTL V
CC
Figure 1. Logic Diagram
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Figure 2. Dip Pin Assignment
Table 1. MAXIMUM RATINGS
Symbol
Characteristic
Rating
Unit
Vdc
Vdc
mA
V
Power Supply
Input Voltage (V = 5.0 V)
0 to +7.0
CC
V
0 to V
50
I
CC
CC
I
Output Current
− Continuous
− Surge
out
100
T
Operating Temperature Range
0 to +75
°C
°C
A
T
stg
Storage Temperature Range − Plastic
− Ceramic
−55 to +150
−55 to +165
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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2
MC10H351
Table 2. ELECTRICAL CHARACTERISTICS (V = V
= V
= 5.0 V 5.0%)†
CC
CC1
CC2
0°
25°
75°
Symbol
ECL
Characteristic
Power Supply
Min
−
Max
Min
−
Max
45
Min
−
Max
50
Unit
mA
mA
mA
50
20
Current
TTL
−
−
15
−
20
Reverse Current
I
R
Pins 7, 8, 12, 14
Pin 9
−
−
25
100
−
−
20
80
−
−
25
100
I
INH
Forward Current
mA
I
F
Pins 7, 8, 12, 14
Pin 9
−
−
−0.8
−3.2
−
−
−0.6
−2.4
−
−
−0.8
−3.2
I
INL
V
Input Breakdown
Voltage
5.5
−
5.5
−
5.5
−
Vdc
Vdc
Vdc
Vdc
(BR)in
V
Input Clamp Voltage
−
−1.5
4.16
3.37
−
−1.5
4.19
3.37
−
−1.5
4.27
3.37
I
(I = −18 mA)
in
V
High Output
Voltage (Note 1.)
3.98
3.05
4.02
3.05
4.08
3.05
OH
V
Low Output
OL
Voltage (1)
High Input Voltage
Low Input Voltage
V
2.0
−
2.0
−
2.0
−
Vdc
Vdc
IH
V
−
0.8
−
0.8
−
0.8
IL
†Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
Outputs are terminated through a 50 W resistor to V −2.0 Vdc.
CC
*Positive Emitter Coupled Logic
1. With V at 5.0 V. V /V change 1:1 with V .
CC
OH OL
CC
Table 3. AC PARAMETERS
0°
25°
75°
Symbol
Characteristic
Min
0.4
0.4
0.4
150
Max
2.2
1.9
1.9
−
Min
0.4
0.4
0.4
150
Max
2.2
2.0
2.0
−
Min
0.4
0.4
0.4
150
Max
2.1
2.1
2.1
−
Unit
ns
t
Propagation Delay (Note 2)
Rise Time (20% to 80%)
Fall Time (80% to 20%)
pd
t
r
t
f
ns
ns
f
Maximum Operating Frequency
MHz
max
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Propagation delay is measured on this circuit from +1.5 V on the input waveform to the 50% point on the output waveform.
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3
MC10H351
ORDERING INFORMATION
Device
†
Package
Shipping
MC10H351FN
PLLC−20
46 Units / Rail
46 Units / Rail
MC10H351FNG
PLLC−20
(Pb−Free)
MC10H351FNR2
PLLC−20
500 / Tape & Reel
500 / Tape & Reel
MC10H351FNR2G
PLLC−20
(Pb−Free)
MC10H351L
MC10H351M
MC10H351MG
CDIP−20
25 Unit / Rail
40 Unit / Rail
40 Unit / Rail
SOEIAJ−20
SOEIAJ−20
(Pb−Free)
MC10H351MEL
SOEIAJ−20
2000 / Tape & Reel
2000 / Tape & Reel
MC10H351MELG
SOEIAJ−20
(Pb−Free)
MC10H351P
PDIP−20
18 Unit / Rail
18 Unit / Rail
MC10H351PG
PDIP−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC10H351
PACKAGE DIMENSIONS
20 LEAD PLLC
CASE 775−02
ISSUE E
M
S
S
N
0.007 (0.180)
T L−M
B
Y BRK
−N−
S
S
N
0.007 (0.180) M T L−M
U
D
D
−L−
−M−
Z
W
20
1
S
S
S
N
0.010 (0.250)
T L−M
G1
X
V
VIEW D−D
M
M
S
S
S
S
A
R
0.007 (0.180)
0.007 (0.180)
T L−M
N
N
Z
T L−M
M
S
S
N
0.007 (0.180)
T L−M
H
C
K1
E
K
0.004 (0.100)
G
−T− SEATING
PLANE
J
M
S
S
N
0.007 (0.180)
T L−M
F
VIEW S
G1
VIEW S
S
S
S
0.010 (0.250)
T L−M
N
NOTES:
INCHES
MILLIMETERS
1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,
1982.
DIM
A
B
C
E
MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
2.79
0.48
0.385
0.385
0.165
0.090
0.013
2. DIMENSIONS IN INCHES.
3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM −T−, SEATING PLANE.
F
G
H
J
K
R
U
V
W
X
Y
0.050 BSC
1.27 BSC
5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER
THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
0.032
−−−
−−−
0.356
0.356
0.048
0.048
0.056
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
−−−
2
0.81
−−−
−−−
9.04
9.04
1.21
1.21
1.42
0.50
10
−−− 0.020
Z
2
10
0.330
−−−
_
_
_
_
G1 0.310
K1 0.040
7.88
1.02
8.38
−−−
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5
MC10H351
PACKAGE DIMENSIONS
SOEIAJ−20
CASE 967−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
20
11
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
e
A
DIM MIN
MAX
c
A
−−−
0.05
2.05
A
1
0.20 0.002
0.50 0.014
0.25 0.006
12.80 0.486
5.45 0.201
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
D
E
e
12.35
5.10
A
1
b
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
0.035
0
_
_
_
_
0.70
−−−
1
Z
0.81
−−− 0.032
CDIP−20
L SUFFIX
CERAMIC DIP PACKAGE
CASE 732−03
ISSUE E
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
20
1
11
10
B
C
INCHES
A
DIM MIN
MAX
0.990
0.295
0.200
0.022
0.065
A
B
C
D
F
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
0.100 BSC
0.020
0.008
0.125
0.050
0.012
0.160
N
K
L
J
0.300 BSC
H
K
M
G
M
N
0
_
0.010
15
0.040
D
_
SEATING
PLANE
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6
MC10H351
PACKAGE DIMENSIONS
PDIP−20
P SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
MILLIMETERS
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
−T−
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
T B
0.25 (0.010)
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
_
M
M
T A
0.25 (0.010)
MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
local Sales Representative.
MC10H351/D
相关型号:
MC10H351MG
QUAD TTL/NMOS TO ECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20, LEAD FREE, EIAJ, SOP-20
ONSEMI
MC10H351MG
QUAD TTL/NMOS TO ECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20, LEAD FREE, EIAJ, SOP-20
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