MC10123FN [ONSEMI]
Triple 4-3-3-Input Bus Driver; 三重4-3-3 ,输入总线驱动器型号: | MC10123FN |
厂家: | ONSEMI |
描述: | Triple 4-3-3-Input Bus Driver |
文件: | 总4页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC10123
Triple 4-3-3-Input Bus
Driver
The MC10123 consists of three NOR gates designed for bus driving
applications on card or between cards. Output low logic levels are
specified with V = –2.1 Vdc so that the bus may be terminated to
OL
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–2.0 Vdc. The gate output, when low, appears as a high impedance to
the bus, because the output emitter– followers of the MC10123 are
“turned–off.” This eliminates discontinuities in the characteristic
impedance of the bus.
MARKING
DIAGRAMS
16
The V level is specified when driving a 25–ohm load terminated
OH
CDIP–16
L SUFFIX
CASE 620
to –2.0 Vdc, the equivalent of a 50–ohm bus terminated at both ends.
Although 25 ohms is the lowest characteristic impedance that can be
driven by the MC10123, higher impedance values may be used with
this part. A typical 50–ohm bus is shown in Figure 1.
MC10123L
AWLYYWW
1
16
• P = 310 mW typ/pkg (No Load)
D
PDIP–16
P SUFFIX
CASE 648
MC10123P
AWLYYWW
• t = 3.0 ns typ
pd
• t , t = 2.5 ns typ (20%–80%)
r
f
1
1
DIP
PIN ASSIGNMENT
PLCC–20
FN SUFFIX
CASE 775
10123
AWLYYWW
V
B
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
C
C
C
C
B
OUT
IN
OUT
OUT
A
= Assembly Location
WL = Wafer Lot
YY = Year
A
A
IN
IN
WW = Work Week
A
IN
IN
ORDERING INFORMATION
A
IN
IN
IN
IN
Device
Package
Shipping
B
B
A
IN
MC10123L
CDIP–16
25 Units / Rail
V
EE
MC10123P
PDIP–16
PLCC–20
25 Units / Rail
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
MC10123FN
LOGIC DIAGRAM
FIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION)
4
5
1/3 MC10123
1/3 MC10123
1/3 MC10123
3
6
7
Z
= 50 Ω
9
10
11
O
2
50 Ω
50 Ω
V
V
= PIN 1
= PIN 16
= PIN 8
CC1
12
13
14
CC2
15
V
EE
RECEIVERS (MECL GATES)
–2.0
VDC
–2.0
VDC
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 7
MC10123/D
MC10123
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
–30°C
Max
82
+85°C
Min
Min
Max
75
Min
Max
82
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unit
mAdc
µAdc
µAdc
Vdc
I
E
8
4
4
3
3
3
3
71
I
350
220
220
inH
I
inL
0.5
Output Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
OH
–1.060
–2.100
–1.080
–0.890
–2.030
–0.960
–2.100
–0.980
–0.810
–2.030
–0.890
–2.100
–0.910
–0.700
–2.030
Output Voltage
V
OL
Vdc
Threshold Voltage
Threshold Voltage
V
OHA
Vdc
V
OLA
–2.100
–2.100
–2.100
Vdc
Switching Times (50Ω Load)
ns
Propagation Delay
t
t
3
3
1.2
1.2
4.6
4.6
1.2
1.2
3.0
3.0
4.4
4.4
1.2
1.2
4.8
4.8
4+3–
4–3+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
3
3
1.0
1.0
3.7
3.7
1.0
1.0
2.5
2.5
3.5
3.5
1.0
1.0
3.9
3.9
3+
t
3–
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V
IHmax
V
ILmin
V
V
V
EE
IHAmin
ILAmax
–30°C
+25°C
+85°C
–0.890
–0.810
–0.700
–1.890
–1.850
–1.825
–1.205
–1.105
–1.035
–1.500
–1.475
–1.440
–5.2
–5.2
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
Gnd
)
CC
Characteristic
Symbol
V
V
ILmin
V
V
V
EE
IHmax
IHAmin
ILAmax
Power Supply Drain Current
I
E
8
4,5,6,7,9
10,11,12
13,14
8
1, 16
Input Current
I
4
4
3
3
4
8
8
8
8
1, 16
1, 16
1, 16
1, 16
inH
I
4
inL
Output Voltage
Output Voltage
Logic 1
Logic 0
V
OH
V
4,5,6,7
9,12
OL
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
V
3
3
4,5,6,7
8
8
1, 16
1, 16
OHA
V
9,12
4,5,6,7
OLA
Switching Times
(50Ω Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t
t
3
3
4
4
3
3
8
8
1, 16
1, 16
4+3–
4–3+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
3
3
4
4
3
3
8
8
1, 16
1, 16
3+
t
3–
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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2
MC10123
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
–M–
–N–
M
S
S
N
0.007 (0.180)
T
L-M
U
D
D
–L–
Z
W
20
1
S
S
S
0.010 (0.250)
T
L-M
N
G1
X
V
A
VIEW D–D
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T
L-M
L-M
N
N
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
T
R
K1
K
C
E
M
S
S
N
0.007 (0.180)
T
L-M
F
0.004 (0.100)
VIEW S
G
–T– SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
S
S
S
0.010 (0.250)
T
L-M
N
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
---
0.032
---
---
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
---
2
0.81
---
---
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.356
0.356
0.048
0.048
0.056
0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
---
7.88
1.02
8.38
---
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3
MC10123
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
DIM MIN MAX
MILLIMETERS
MIN
19.05
6.10
---
MAX
19.93
7.49
5.08
0.50
A
B
C
D
E
F
0.750
0.240
---
0.785
0.295
0.200
0.020
–T–
SEATING
PLANE
0.015
0.39
K
N
0.050 BSC
1.27 BSC
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
G
0.300 BSC
7.62 BSC
M
S
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
D 16 PL
_
_
_
M
S
T A
0.25 (0.010)
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
–A–
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC10123/D
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