MC10121L [ONSEMI]
4-Wide OR-AND/OR-AND Gate; 4 ，宽OR- AND / OR- AND门
| 型号： | MC10121L |
| 厂家： | 
ONSEMI |
| 描述： | 4-Wide OR-AND/OR-AND Gate |
| 文件： | 总8页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10121
4-Wide OR-AND/OR-AND
Gate
The MC10121 is a basic logic building block providing the
simultaneous OR–AND/OR–AND–Invert function, useful in data
control and digital multiplexing applications.
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• P = 100 mW typ/pkg (No Load)
D
• t = 2.3 ns typ
pd
MARKING
DIAGRAMS
• t , t = 2.5 ns typ (20%–80%)
r
f
16
LOGIC DIAGRAM
CDIP–16
L SUFFIX
CASE 620
MC10121L
AWLYYWW
4
5
6
7
9
1
16
PDIP–16
P SUFFIX
CASE 648
MC10121P
AWLYYWW
2
3
10
1
1
11
12
13
14
15
V
V
= PIN 1
= PIN 16
= PIN 8
CC1
PLCC–20
FN SUFFIX
CASE 775
10121
CC2
V
EE
AWLYYWW
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
DIP
PIN ASSIGNMENT
V
A
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
ORDERING INFORMATION
A4
IN
IN
IN
IN
OUT
OUT
Device
Package
Shipping
A4
A4
A3
A3
A
MC10121L
CDIP–16
25 Units / Rail
A1
IN
IN
IN
IN
A1
MC10121P
PDIP–16
PLCC–20
25 Units / Rail
46 Units / Rail
A1
A2
V
IN
MC10121FN
A2 , A3
IN
IN
A2
IN
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 7
MC10121/D
MC10121
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
–30°C
Max
29
+85°C
Min
Min
Max
Min
Max
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unit
mAdc
µAdc
I
E
8
20
26
29
I
7
9
10
390
390
495
245
245
310
245
245
310
inH
I
inL
7
9
10
0.5
0.5
0.5
0.5
0.5
0.5
0.3
0.3
0.3
µAdc
Output Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
3
2
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Vdc
Vdc
Vdc
ns
OH
Output Voltage
V
3
2
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
OL
Threshold Voltage
Threshold Voltage
V
OHA
3
2
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
V
OLA
3
2
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Switching Times (50Ω Load)
Propagation Delay
t
t
t
3
3
2
2
1.4
1.4
1.4
1.4
3.6
3.6
3.6
3.6
1.4
1.4
1.4
1.4
2.3
2.3
2.3
2.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
3.5
3.5
3.5
3.5
4+3–
4–3+
4+2+
t
4–2–
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
3
2
0.9
0.9
4.1
4.1
1.1
1.1
2.5
2.5
4.0
4.0
1.1
1.1
4.6
4.6
3+
2+
t
t
3
2
0.9
0.9
4.1
4.1
1.1
1.1
2.5
2.5
4.0
4.0
1.1
1.1
4.6
4.6
3–
2–
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2
MC10121
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V
IHmax
V
ILmin
V
V
V
EE
IHAmin
ILAmax
–30°C
+25°C
+85°C
–0.890
–0.810
–0.700
–1.890
–1.850
–1.825
–1.205
–1.105
–1.035
–1.500
–1.475
–1.440
–5.2
–5.2
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
Gnd
)
CC
Characteristic
Power Supply Drain Current
Input Current
Symbol
V
V
ILmin
V
V
V
EE
IHmax
IHAmin
ILAmax
I
E
8
8
1, 16
I
7
9
10
7
9
10
8
8
8
1, 16
1, 16
1, 16
inH
I
inL
7
9
10
7
9
10
8
8
8
1, 16
1, 16
1, 16
Output Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
3
2
8
8
1, 16
1, 16
OH
4, 10, 13
4, 10, 13
Output Voltage
V
3
2
8
8
1, 16
1, 16
OL
Threshold Voltage
Threshold Voltage
V
OHA
3
2
4
4
8
8
1, 16
1, 16
10, 13
4
4
V
OLA
3
2
8
8
1, 16
1, 16
10, 13
Switching Times
(50Ω Load)
+1.11V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t
t
t
3
3
2
2
10, 13
10, 13
10, 13
10, 13
4
4
4
4
3
3
2
2
8
8
8
8
1, 16
1, 16
1, 16
1, 16
4+3–
4–3+
4+2+
t
4–2–
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
3
2
10, 13
10, 13
4
4
3
2
8
8
1, 16
1, 16
3+
2+
t
t
3
2
10, 13
10, 13
4
4
3
2
8
8
1, 16
1, 16
3–
2–
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10121
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
–M–
–N–
M
S
S
N
0.007 (0.180)
T
L-M
U
D
D
–L–
Z
W
20
1
S
S
S
0.010 (0.250)
T
L-M
N
G1
X
V
A
VIEW D–D
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T
L-M
L-M
N
N
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
T
R
K1
K
C
E
M
S
S
N
0.007 (0.180)
T
L-M
F
0.004 (0.100)
VIEW S
G
–T– SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
S
S
S
0.010 (0.250)
T
L-M
N
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
---
0.032
---
---
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
---
2
0.81
---
---
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.356
0.356
0.048
0.048
0.056
0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
---
7.88
1.02
8.38
---
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4
MC10121
PACKAGE DIMENSIONS
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
DIM MIN MAX
MILLIMETERS
MIN
19.05
6.10
---
MAX
19.93
7.49
5.08
0.50
A
B
C
D
E
F
0.750
0.240
---
0.785
0.295
0.200
0.020
–T–
SEATING
PLANE
0.015
0.39
K
N
0.050 BSC
1.27 BSC
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
G
0.300 BSC
7.62 BSC
M
S
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
D 16 PL
_
_
_
M
S
T A
0.25 (0.010)
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
–A–
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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5
MC10121
Notes
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6
MC10121
Notes
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7
MC10121
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC10121/D
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