LV8105W [ONSEMI]
Three-Phase Brushless Motor Predriver;
| 型号： | LV8105W |
| 厂家： | 
ONSEMI |
| 描述： | Three-Phase Brushless Motor Predriver 信息通信管理 |
| 文件： | 总21页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1271
LV8105W
Bi-CMOS IC
Three-Phase Brushless Motor Predriver
for Variable Speed Control
http://onsemi.com
Overview
The LV8105W is a predriver IC designed for variable speed control of 3-phase brushless motors. It can be used to
implement a high- and low-side output n-channel power FET drive circuit using a built-in charge pump circuit.
High-efficiency drive is possible through the use of low noise PWM drive and synchronous rectifying systems.
Functions
Speed discriminator and PLL speed control system
Built-in VCO circuit for generating the speed discriminator reference signal
Speed lock detection output
Hall bias switch
Braking circuit (short braking)
Full complement of on-chip protection circuits, including current limiter and lock protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
max
V
= VG
42
42
CC
CC
Charge pump output voltage
Output current
VG max
VG pin
V
I
I
max1
max2
Pins UL, VL, WL
-15 to 15
-20 to 20
0.45
mA
mA
W
O
O
Pins UH, VH, WH, UOUT, VOUT and WOUT
Independent IC
Allowable power dissipation
Pd max1
Pd max2
Topr
Mounted on the specified board *
1.30
W
Operating temperature
Storage temperature
-20 to +80
-55 to +150
C
C
Tstg
* Specified board:114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
SQFP48(7X7)
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
82008MSPC 20080710-S00008 No.A1271-1/21
LV8105W
Allowable Operating range at Ta = 25C
Parameter
Supply voltage range
Symbol
Conditions
Ratings
Unit
V
V
I
16 to 28
0 to -10
0 to -25
0 to 6
CC
5V constant voltage output current
HB pin output current
mA
mA
V
REG
HB
I
LD pin applied voltage
LD pin output current
V
LD
I
0 to 5
mA
V
LD
FGS pin applied voltage
FGS pin output current
V
0 to 6
FGS
I
0 to 5
mA
FGS
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta 25C, V
= 24V
CC
Ratings
typ
Parameter
Symbol
1
Conditions
Unit
min
max
Supply current 1
Supply current 2
I
I
7
3
8.8
3.8
mA
mA
CC
2
At stop
CC
5V Constant-voltage Output (VREG pin)
Output voltage
Line regulation
Load regulation
VREG
I
= 5mA
5.2
5.6
10
10
6.0
50
50
V
O
V (REG1)
V (REG2)
V
= 16 to 28V
mV
mV
CC
= -5 to -10mA
I
O
Output block / Conditions : apply a VG voltage of 33V
High level output voltage 1
Low level output voltage 1
High level output voltage 2
Low level output voltage 2
PWM frequency
V
V
V
V
1
Pins UL, VL and WL
Pins UL, VL and WL
Pins UH, VH and WH
Pins UH, VH and WH
I
I
= -2mA
= 2mA
= -2mA
VREG-0.65
0.35
VREG-0.5 VREG-0.35
V
V
OH
OH
1
0.5
VG-0.5
0.6
0.65
VG-0.35
0.8
OL
OL
I
2
VG-0.65
0.45
V
OH
OH
2
I
= 2mA
V
OL
OL
f (PWM)
f (REF)
VGOUT
51
64
77
kHz
Internal Oscillator
Oscillation frequency
Charge Pump Output (VG pin)
Output voltage
1.65
2.05
2.45
MHz
V
V
+8.0
V
+9.0
CC
V
+10.0
CC
CC
CP1 pin
High level output voltage
Low level output voltage
Charge pump frequency
Hall Amplifier
V
V
(CP1)
ICP1 = -2mA
ICP1 = 2mA
V
-1.35
0.5
V
-1.0
CC
V
-0.7
0.8
V
V
OH
CC
CC
(CP1)
0.65
128
OL
f (CP1)
102
154
kHz
Input bias current
IHB (HA)
VICM1
-2
0.3
0
-0.1
A
V
Common-mode input voltage range 1
Common-mode input voltage range 2
Hall input sensitivity
Hysteresis width
When using Hall elements
3.5
VICM2
At one-side input bias (Hall IC application)
SIN wave
VREG
V
50
5
mVp-p
mV
mV
mV
V (HA)
13
7
24
12
-2
IN
Input voltage Low High
Input voltage High Low
HB pin
VSLH
VSHL
2
-12
-6
Output voltage
VHBO
IHB = -15mA
V
-0.8
V
-0.5
V -0.35
CC
V
CC
CC
Output leakage current
FG Amplifier
IL (HB)
V
= 0V
-10
A
O
Input offset voltage
V
(FG)
-10
-1
10
1
mV
A
V
IO
Input bias current
IB (FG)
Reference voltage
VB (FG)
-5%
3.95
0.75
3
VREG/2
4.4
5%
4.85
1.65
High level output voltage
Low level output voltage
FG input sensitivity
V
(FG)
IFGI = -0.1mA, No load
IFGI = 0.1mA, No load
GAIN : 100 times
V
OH
OL
V
(FG)
1.2
V
mV
mV
kHz
dB
Schmitt width of the next stage
Operation frequency range
Open-loop gain
One-side hysteresis comparator
120
200
48
280
3
f
= 2kHz
45
FG
Continued on next page.
No.A1271-2/21
LV8105W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
(FGS)
Conditions
Unit
min
max
FGS output
Output saturation voltage
Output leakage current
CSD oscillator
V
I
= 2mA
0.2
0.4
10
V
OL
FGS
= 6V
IL (FGS)
V
A
O
High level output voltage
Low level output voltage
Amplitude
V
V
(CSD)
2.9
1.6
3.4
2.0
3.9
2.4
V
V
OH
(CSD)
OL
V (CSD)
ICHG1
ICHG2
f (CSD)
1.15
-13
1.4
1.65
-7
Vp-p
A
A
Hz
External capacitor charge current
External capacitor discharge current
Oscillation frequency
Speed Discriminator output
High level output voltage 1
Low level output voltage 1
High level output voltage 2
Low level output voltage 2
Counts
-10
10.5
78
7.5
13.5
C = 0.047F
V
V
V
V
1 (D)
VREG-1.25
0.65
VREG-1.0 VREG-0.75
V
V
V
V
OH
1 (D)
0.9
VREG-1.7
1.6
1.15
VREG-1.4
1.9
OL
2 (D)
VREG-2.0
1.3
OH
2 (D)
OL
512
LD output
Output saturation voltage
Output leakage current
Lock range
V
(LD)
ILD = 2mA
0.2
0.4
10
V
A
%
OL
IL (LD)
V
= 6V
O
-6.25
+6.25
Speed control PLL output
High level output voltage
Low level output voltage
Current control circuit
Drive gain
V
V
(P)
VREG-2.0
1.3
VREG-1.7
1.6
VREG-1.4
1.9
V
V
OH
(P)
OL
GDF
VRF
0.20
0.23
0.25
0.25
0.32
Current limiter operation
Limiter voltage
0.275
V
Integrator
Input offset voltage
Input bias current
V
(INT)
-10
-1
10
1
mV
A
V
IO
IB (INT)
Reference voltage
VB (INT)
-5%
3.95
0.75
45
VREG/2
4.4
5%
4.85
1.65
High level output voltage
Low level output voltage
Open-loop gain
V
(INT)
I
I = -0.1mA, No load
V
OH
OL
INT
INT
INT
V
(INT)
I
f
I = 0.1mA, No load
= 2kHz
1.2
V
48
dB
VCO Oscillator (C pin)
Oscillation frequency range
High level output voltage
Low level output voltage
Amplitude
f (C)
C = 120pF, R = 24k
FIL = 2.5V
0.15
2.71
2.20
0.44
1.54
3.61
3.00
0.68
MHz
V
V
(C)
(C)
3.16
2.60
0.56
OH
V
FIL = 2.5V
V
OL
V (C)
FIL = 2.5V
Vp-p
FIL pin
Output source current
Output sink current
RC pin
I
I
(FIL)
(FIL)
-15
6
-11
10
-6
A
A
OH
OL
15
Comparator voltage
Low-voltage protection circuit
Operation voltage
VRC
VREG0.59 VREG0.60 VREG0.61
V
VLVSD
8.00
0.25
8.54
0.34
9.00
0.45
V
V
Hysteresis width
VLVSD
Thermal shutdown operation
Thermal shutdown operation
temperature
TSD
Design target value*
Design target value*
150
175
30
C
C
Hysteresis width
TSD
Note : * These items are design target values and are not tested.
Continued on next page.
No.A1271-3/21
LV8105W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
CLK pin
Input frequency
fI (CLK)
3
kHz
V
High level input voltage range
Low level input voltage range
Input open voltage
V
V
V
V
(CLK)
(CLK)
(CLK)
(CLK)
2.0
0
VREG
1.0
IH
V
IL
VREG-0.5
0.18
VREG
0.36
-3
V
IO
IS
Hysteresis width
Design target value*
0.27
V
High level input current
Low level input current
Pull-up resistance
I
I
(CLK)
(CLK)
VCLK = 5V
VCLK = 0V
-22
-10
-93
60
A
A
k
IH
IL
-133
-70
RU (CLK)
45
75
S/S pin
High level input voltage range
Low level input voltage range
Input open voltage
V
V
V
V
(S/S)
(S/S)
(S/S)
(S/S)
2.0
0
VREG
1.0
V
V
IH
IL
VREG-0.5
0.18
VREG
0.36
-3
V
IO
IS
Hysteresis width
0.27
-10
-93
60
V
High level input current
Low level input current
Pull-up resistance
I
I
(S/S)
(S/S)
VS/S = 5V
VS/S = 0V
-22
A
A
k
IH
IL
-133
-70
RU (S/S)
45
75
F/R pin
High level input voltage range
Low level input voltage range
Input open voltage
V
V
V
V
(F/R)
(F/R)
(F/R)
(F/R)
2.0
0
VREG
1.0
V
V
IH
IL
VREG-0.5
0.18
VREG
0.36
-3
V
IO
IS
Hysteresis width
0.27
-10
-93
60
V
High level input current
Low level input current
Pull-up resistance
I
I
(F/R)
(F/R)
VF/R = 5V
VF/R = 0V
-22
A
A
k
IH
IL
-133
-70
RU (F/R)
45
75
BR pin
High level input voltage range
Low level input voltage range
Input open voltage
V
V
V
V
(BR)
(BR)
(BR)
(BR)
2.0
0
VREG
1.0
V
V
IH
IL
VREG-0.5
0.18
VREG
0.36
-3
V
IO
IS
Hysteresis width
0.27
-10
-93
60
V
High level input current
Low level input current
Pull-up resistance
I
I
(BR)
(BR)
VBR = 5V
VBR = 0V
-22
A
A
k
IH
IL
-133
-70
RU (BR)
45
75
Note : * These items are design target values and are not tested.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A1271-4/21
LV8105W
Package Dimensions
unit : mm (typ)
SQFP48(7X7)
Pd max – Ta
1.5
1.3
Specified board : 114.3 × 76.1 × 1.6mm3
glass epoxy
Mounted on a board
9.0
7.0
36
25
1.0
24
13
37
0.73
0.25
Independent IC
0.5
0.45
48
1
12
0.5
0.15
0.18
0
–
(0.75)
20
0
20
40
60
80
100
Ambient temperature, Ta – °C
Pin Assignment
36
35
34
33
32
31
30
29
28
27
26
25
NC 37
38
24 HB
23 IN3
22 IN3
21 IN2
20 IN2
19 IN1
18 IN1
+
-
V
CC
VG 39
+
-
CP2 40
CP1 41
NC 42
+
-
LV8105
VREG 43
GND2 44
GND1 45
C 46
+
-
17 FGIN
16 FGIN
15 FGOUT
14 LD
R 47
FIL 48
13 FGS
1
2
3
4
5
6
7
8
9
10
11
12
No.A1271-5/21
LV8105W
+
-
Three-phase logic truth table (A high level input is the state where IN > IN .)
F/R = “L”
F/R = “H”
Drive output
IN1
IN2
IN3
IN1
IN2
IN3
Upper gate
Lower gate
1
2
3
4
5
6
H
H
H
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
VH
WH
WH
UH
UH
VH
UL
UL
VL
H
H
H
L
L
L
L
H
H
H
L
VL
L
H
H
L
WL
WL
L
H
L
When F/R is “L”, the Hall input while the motor is rotating must be input in order from 1 to 6 of the above table.
When the Hall input is performed by the reverse order, it will not become the soft current-carrying output.
(The motor is driven by the 120 degrees current-carrying only.)
Also, when F/R is “H”, the Hall input while the motor is rotating must be input in order from 6 to 1 of the above table.
When the Hall input is performed by the reverse order, it will not become the soft current-carrying output.
(The motor is driven by the 120 degrees current-carrying only.)
S/S Input
BR Input
Input
High or Open
Low
Mode
Stop
Start
Input
High or Open
Low
Mode
Brake
Release
Current Control Characteristics
RF – INTOUT (typical characteristics)
0.3
0.25
0.2
GAIN = 0.25
0.1
0
1.5
2.0 2.2
2.5
3.0 3.2
3.5
4.0
INTOUT – V
No.A1271-6/21
LV8105W
Block Diagram
(Referance constants)
No.A1271-7/21
LV8105W
Relations Hall input with Drive output
(1) When F/R = ”L” and the soft current-carrying output.
IN1
IN2
IN3
(UH)
(VH)
(WH)
120 degrees
Current-carrying
(UL)
(VL)
(WL)
UH
VH
WH
Soft
Current-carrying
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-8/21
LV8105W
(2) When F/R = ”H” and the soft current-carrying output.
IN1
IN2
IN3
(UH)
(VH)
(WH)
120 degrees
Current-carrying
(UL)
(VL)
(WL)
UH
VH
WH
Soft
Current-carrying
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-9/21
LV8105W
(3) When F/R = ”L” and the 120 degrees current-carrying only.
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
(4) When F/R=”H” and the 120 degrees current-carrying only.
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-10/21
LV8105W
Pin Functions
Pin No.
Pin name
Pin function
Equivalent circuit
Reset circuit
1
CSD
Pin to set the operating time of the constraint
protection.
VREG
Connect a capacitor between this pin and GND.
This pin combines also functions as the logic circuit
block initial reset pin.
500Ω
1
3
RC
Pin to set the speed discriminator output amplitude
switching circuit.
VREG
Connect a capacitor between this pin and GND. And
connect a resistor between VREG and this pin.
1kΩ
3
4
INTOUT
Integrating amplifier output pin.
VREG
4
105kΩ
5
6
7
INTIN
INTREF
DOUT
Integrating amplifier inverting input pin.
500Ω
INTOUT
VREG
30kΩ
Integrating amplifier non-inverting input pin.
1/2 VREG potential.
500Ω
30kΩ
500Ω
6
5
Connect a capacitor between this pin and GND.
Speed discriminator output pin.
VREG
Acceleration high, deceleration low.
7
Continued on next page.
No.A1271-11/21
LV8105W
Continued from preceding page.
Pin No.
8
Pin name
POUT
Pin function
Equivalent circuit
Speed control PLL output pin.
VREG
Outputs the phase comparison result for CLK and
FG.
8
9
S/S
CLK
F/R
BR
Start / Stop control pin.
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Goes high when left open.
Low for start.
55kΩ
The hysteresis width is about 0.27V.
5kΩ
5kΩ
5kΩ
5kΩ
9
10
11
12
External clock signal input pin.
Low : 0V to 1.0V
VREG
VREG
VREG
High : 2.0V to VREG
Goes high when left open.
The hysteresis width is about 0.27V.
f = 3kHz, maximum.
55kΩ
55kΩ
55kΩ
10
11
12
Forward / reverse control pin.
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
Low for forward.
The hysteresis width is about 0.27V.
Brake pin (short braking operation).
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
High or open for brake mode operation.
The hysteresis width is about 0.27V.
Continued on next page.
No.A1271-12/21
LV8105W
Continued from preceding page.
Pin No.
13
Pin name
FGS
Pin function
Equivalent circuit
FG amplifier Schmitt output pin.
This is an open collector output.
VREG
13
14
LD
Lock detection output pin.
VREG
This is an open collector output.
Goes low when the motor speed is within the speed
lock range (6.25%).
14
15
FGOUT
FG amplifier output pin.
VREG
This pin is connected to the FG Schmitt comparator
circuit internally in the IC.
15
105kΩ
500Ω
FG Schmitt comparator
-
16
FGIN
FG amplifier inverting input pin.
FGOUT
VREG
30kΩ
+
17
FGIN
FG amplifier non-inverting input pin.
1/2 VREG potential.
500Ω
500Ω
17
16
Connect a capacitor between this pin and GND.
30kΩ
-
18
19
20
21
22
23
IN1
Hall input pins.
VREG
+
+
>
IN1
The input is seen as a high level input when IN
-
-
IN2
IN , and as a low level input for the opposite state.
+
IN2
If noise on the Hall signals is a problem, insert
-
+
-
IN3
capacitors between the corresponding IN and IN
+
IN3
inputs.
18 20 22
19 21 23
Continued on next page.
No.A1271-13/21
LV8105W
Continued from preceding page.
Pin No.
24
Pin name
HB
Pin function
Hall bias switch pin.
Equivalent circuit
V
CC
Goes off when the S/S pin is the stop state.
24
25
RFGND
Output current detection reference pin.
Connect to GND side of the current detection
resistor Rf.
VREG
2kΩ
25
26
RF
Output current detection pin.
VREG
Connect to the current detection resistor Rf.
Sets the the maximum output current IOUT to be
0.25/Rf.
5kΩ
26
28
31
34
UL
VL
Output pins for gate drive of the lower side N
channel power FET.
VREG
WL
28 31 34
Continued on next page.
No.A1271-14/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
Pin function
Equivalent circuit
30
33
36
UH
VH
Output pins for gate drive of the upper side N
channel power FET.
VG
WH
100Ω
30 33 36
29
32
35
UOUT
VOUT
WOUT
Pins to detect the source voltage of the upper side N
channel power FET.
100Ω
29 32 35
38
39
V
Power supply pin.
CC
Connect a capacitor between this pin and GND for
stabilization.
VG
CP2
CP1
Charge pump output pin.
V
CC
Connect a capacitor between this pin and V
.
CC
400Ω
100Ω
40
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP1.
39
40
41
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP2.
V
CC
41
43
VREG
5V constant voltage output pin (5.6V).
V
CC
Connect a capacitor between this pin and GND.
43
Continued on next page.
No.A1271-15/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
Pin function
Equivalent circuit
44
45
46
GND2
GND1
C
GND pins.
GND1 and GND2 are connected in the IC.
VCO oscillation pin.
VREG
Connect a capacitor between this pin and GND.
500Ω
46
47
R
Pin to set the charge/discharge current of the VCO
circuit.
VREG
Connect a resistor between this pin and GND.
500Ω
47
48
FIL
VCO PLL output filter pin.
VREG
500Ω
48
2
NC
No connection pins.
27
37
42
No.A1271-16/21
LV8105W
Description of LV8105W
1. Speed control circuit
This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a
motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed
control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal
once every one FG period. The FG servo frequency signal (f ) is controlled to have the equal frequency with the
FG
clock signal (f
CLK
) which is input through the CLK pin.
f
= f
FG CLK
2. VCO circuit
This IC has the VCO circuit to generate the reference signal of the speed discriminator circuit. The reference signal
frequency is calculated as follows.
f
= f
VCO CLK
512
f
: Reference signal frequency, f : Clock signal frequency
CLK
VCO
The components connected to the R, C and FIL pins must be connected to the GND1 pin (pin 45) with a line that is as
short as possible to reduce influence of noise.
3. Output drive circuit
This IC adopts a direct PWM drive method to reduce power loss in the output. An external output transistor is always
saturated while the transistor is on and driving force of the motor is adjusted by changing the duty that the output
transistor is on. The waveform of the coil current becomes trapezoidal with the current control and the overlap
switching of about 15 degrees. Therefore, it is possible to reduce the motor noise and the torque ripple when switching
the phase to which power is applied (Soft current-carrying).
When the 120 degrees current-carrying, the PWM switching is performed on the UL, VL and WL pins only. Also,
when the soft current-carrying, the PWM switching is performed on any the outputs (the UL, VL, WL, UH, VH and
WH pins). The PWM frequency is determined with 64kHz (typical) in the IC.
When the PWM switching of the upper side output is off, the lower side output is turned on. Also, when the PWM
switching of the lower side output is off, the upper side output is turned on (Synchronous rectification). The off-time of
the synchronous rectification is determined in the IC and varies from 1.2s to 3.1s.
4. Current limiter circuit
The current limiter circuit limits the (peak) current at the value I = V /Rf (V = 0.25V (typical), Rf : current
RF
RF
detection resistor). The current limitation operation consists of reducing the PWM output on-duty to suppress the
current.
High accuracy detection can be achieved by connecting the RF and RFGND pins lines near at the ends of the current
detection resistor (Rf).
5. Speed lock range
The speed lock range is less than 6.25% of the fixes speed. When the motor speed is in the lock range, the LD pin (an
open collector output) goes low. If the motor speed goes out of the lock range, the on-duty of the motor drive output is
adjusted according to the speed error to control the motor speed to be within the lock range.
As for the 120 degrees current-carrying and the soft current-carrying, when the motor speed goes out of the lock range,
the current-carrying becomes the 120 degrees current-carrying. When the motor speed is within the lock range, the
current-carrying becomes the soft current-carrying.
No.A1271-17/21
LV8105W
6. Speed discriminator output amplitude switching circuit
By the magnitude relation between the time t that is set by using the capacitor and resistor connected with the RC pin
and the clock period which is input through the CLK pin, the output amplitude of the speed discriminator switches as
follows.
<High level output voltage>
VREG-1.0V
<Low level output voltage>
When the clock period is smaller than t
When the clock period is bigger than t
0.9V
1.6V
VREG-1.7V
When connect a resistor R between the RC pin and VREG and a capacitor C between the RC pin and GND, the above
time t is calculated as follows.
t = 0.91 R C
By the variance of the IC, “0.91” of the above formula has varied from 0.885 to 0.935.
When switching the output amplitude of the speed discriminator by the input voltage to the RC pin is performed, input
that voltage to the RC pin through the resistor of 20k.
The output amplitude of the speed discriminator is switched by the input voltage as follows.
<High level output voltage>
VREG-1.0V
<Low level output voltage>
Low level input (0V to 2V),
High level input (4V to 6V),
0.9V
1.6V
VREG-1.7V
When there is no need for the speed discriminator output amplitude switching, connect the RC pin with GND. In this
instance, the high level output voltage of the speed discriminator becomes VREC-1.0V and the low level output voltage
of the speed discriminator becomes 0.9V.
7. Hall input signal
The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. The closer the input
wave-form is to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required
the closer the input waveform is to a triangular wave. Also, note that the input DC voltage must be set to be within the
common-mode input voltage range.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the
Hall sensor signal inputs as 0 to VREG level signals if the other side is held fixed at a voltage within the common-mode
input voltage range that applies when the Hall sensors are used.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins.
When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state.
The bias of the Hall element can be cut by supplying the bias of the Hall element from the HB pin while the S/S pin is
a stop mode(Hall bias switch).
The Hall input frequency range possible for the soft current-carrying is determined from 30Hz to 500Hz (IN1
frequency).
8. S/S switching circuit
When the S/S pin is set to the low level, S/S switching circuit is the start mode. Inversely, when the S/S pin is set to the
high level or open, S/S switching circuit is the stop mode. At the stop mode, all the outputs will be in the off state.
This IC will be in the power save state of decreasing the supply current at the stop mode.
9. Braking circuit
When the BR pin is set to the high level or open, the brake is on. Inversely, when the BR pin is set to the low level, the
brake is released. The brake becomes a short brake that turns on the lower side output transistors for all phases (the UL,
VL and WL side) and turns off the upper side output transistors for all phases (the UH, VH and WH side). Note that the
current limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed.
The current that flows in the output transistors during braking is determined by the motor back EMF voltage and the
coil resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors
used. (The higher the motor speed at which braking is applied, the more severe this problem becomes).
The braking function can be applied and released with the IC at the start mode. This means that motor startup and stop
control can be performed using the BR pin with the S/S pin held at the low level (the start mode). If the startup time
becomes excessive, it can be reduced by controlling the motor startup and stop with the BR pin rather than with the S/S
pin (Since the IC will be in the power save state at the stop mode, enough time for the VCO circuit to stabilize will be
required at the beginning of the motor start operation).
No.A1271-18/21
LV8105W
10. Forward/Reverse switching circuit
The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if
the motor direction is switched while the motor is turning.
• This IC is designed to avoid through currents when switching directions. However, increases in the motor supply
voltage (due to instantaneous return of the motor current to the power supply) during direction switching may cause
problems. The values of the capacitors inserted between power and ground must be increased if this increase is
excessive.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor
back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed
the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more
severe this problem becomes.)
11. Constraint protection circuit
The LV8105W includes an on-chip constraint protection circuit to protect the motor and the output transistors in motor
constraint mode. If the LD output remains high (indicating the unlocked state) for a fixed period in the motor drive state
(the S/S pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off.
This time can be set by adjusting the oscillation frequency of the CSD pin by using a external capacitor. By the
capacitance of the capacitor attached to the CSD pin, the set time is calculated as follows.
The set time (sec) = 60.8 C (F)
When a 0.047F capacitor is connected with the CSD pin, the set time becomes about 2.9sec.
By the variance of the IC, “60.8” of the above formula has varied from 40.8 to 80.8.
To restart a motor by cancelling the constraint protection function, any of the following operation is necessary.
• Put the S/S pin into the start state again after the stop state (about 1ms or more).
• Put the BR pin into the brake release state again after the braking state (about 1ms or more).
• Turn on the power supply again after the turn off state.
When the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function
are operating, the constraint protection function does not operate even if the motor does not rotate.
The oscillation waveform of the CSD pin is used as the reference signal for some circuits in addition to the motor
constraint protection circuit. Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function
is unnecessary. If the constraint protection circuit is not used, the oscillation of the CSD pin must be stopped by
connecting a 220k resistor and a 0.01F capacitor in parallel between the CSD pin and GND. However, in that case,
the clock disconnection protection circuit will no longer function. Also, the synchronous rectification does not operate
in any of the following cases.
• When the motor does not rotate in the motor constrained state since the motor is started up by the S/S or the BR input,
the PWM switching is performed by using the current limiter circuit. But, the synchronous rectification does not
operate when the oscillation of the CSD pin is stopped.
The CSD pin combines also functions as the initial reset pin. The time that the CSD pin voltage is charged to about
1.25V is determined as the initial reset. At the initial reset, all the outputs will be in the off state.
12. Clock disconnection protection circuit
If the clock input through the CLK pin goes to the no input state in the motor drive state (the S/S pin : start, the BR pin :
brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the clock is resupplied, the
clock disconnection protection function is cancelled.
When the clock period is longer than about thirty-fourth part of the constraint protection set time, the clock
disconnection protection circuit judges the clock input to be the no input state and this protection function will operate.
13. Thermal shutdown circuit
If the junction temperature rises to the specified temperature (TSD) in the motor drive state (the S/S pin : start, the BR
pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the junction
temperature falls to more than the hysteresis width (TSD), the thermal shutdown function is cancelled.
No.A1271-19/21
LV8105W
14. Low-voltage protection circuit
The LV8105W includes a low-voltage protection circuit to protect against incorrect operation when the V
power is
CC
voltage falls under the specified
applied or if the power supply voltage falls below its operating level. When the V
CC
voltage rises to more than the hysteresis width
voltage (VLVSD), all the outputs will be in the off state. If the V
CC
(VLVSD), the low-voltage protection function is cancelled.
15. Power supply stabilization
Since this IC is used in applications that flow the large output current, the power supply line is subject to fluctuations.
Therefore, capacitors with capacitance adequate to stabilize the power supply voltage must be connected between the
V
pin and GND. If diodes are inserted in the power supply line to prevent the IC destruction due to reverse power
CC
supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger
capacitance will be required.
16. Ground lines
The signal system GND and the output system GND must be separated, and connected to one GND at the connector. As
the large current flows to the output system GND, this GND line must be made as short as possible.
Output system GND : GND for Rf and V
CC
line capacitors
Signal system GND : GND for the IC and external components
17. Integrating amplifier
The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed
command voltage. At that time it also sets the control loop gain and the frequency characteristics. External components
of the integrating amplifier must be placed as close to the IC as possible to reduce influence of noise.
18. FG amplifier
The FG amplifier normally makes up a filter amplifier to reject noise. Since a clamp circuit has been added at the FG
amplifier output, the output amplitude is clamped at about 3.2Vp-p, even if the amplifier gain is increased.
After the FG amplifier, the Schmitt comparator on one side hysteresis(200mV (typical)) is inserted. The Schmitt
+
comparator output (FGS output) becomes high level when the FG amplifier output is lower than the FGIN voltage,
and becomes low level when the FG amplifier output is higher to more than Schmitt width as compared with the FGIN
+
voltage. Therefore, it is desirable that the amplifier gain be set so that the output amplitude is over 1.0Vp-p at the lowest
controlled speed to be used.
+
The capacitor connected between the FGIN pin and GND is required for bias voltage stabilization. This capacitor
must be connected to the GND1 pin (pin 45) with a line that is as short as possible to reduce influence of noise.
As the FG amplifier and the FGS output are operating even if the S/S pin is the stop state, it is possible to monitor the
motor rotation by the FGS output.
No.A1271-20/21
LV8105W
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
50 / Tray Foam
SQFP48(7X7)
(Pb-Free)
LV8105W-MPB-E
SQFP48(7X7)
(Pb-Free)
LV8105W-TLM-E
1000 / Tape & Reel
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PS No.A1271-21/21
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