LMV393 [ONSEMI]
Single, Dual, Quad General Purpose, Low Voltage Comparators; 单，双，四通道通用，低电压比较器
| 型号： | LMV393 |
| 厂家： | 
ONSEMI |
| 描述： | Single, Dual, Quad General Purpose, Low Voltage Comparators |
| 文件： | 总21页 (文件大小：906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV331, LMV393, LMV339
Single, Dual, Quad General
Purpose, Low Voltage
Comparators
The LMV331 is a CMOS single channel, general purpose, low
voltage comparator. The LMV393 and LMV339 are dual and quad
channel versions, respectively. The LMV331/393/339 are specified
for 2.7 V to 5 V performance, have excellent input common−mode
range, low quiescent current, and are available in several space saving
packages.
The LMV331 is available in a 5−pin SC−70, a TSOP−5, and a
ULLGA8 package. The LMV393 is available in a 8−pin Micro8t,
SOIC−8, and a UDFN8 package, and the LMV339 is available in a
SOIC−14 and a TSSOP−14 package.
http://onsemi.com
5
1
1
SC−70
TSOP−5
CASE 419A
CASE 483
The LMV331/393/339 are cost effective solutions for applications
where space saving, low voltage operation, and low power are the
primary specifications in circuit design for portable applications.
1
1
ULLGA8
CASE 613AG
Micro8
CASE 846A
Features
• Guaranteed 2.7 V and 5 V Performance
• Input Common−mode Voltage Range Extends to Ground
• Open Drain Output for Wired−OR Applications
• Low Quiescent Current: 60 mA/channel TYP @ 5 V
• Low Saturation Voltage 200 mV TYP @ 5 V
• Propagation Delay 200 ns TYP @ 5 V
• These are Pb−Free Devices
8
8
1
1
SOIC−8
CASE 751
UDFN8
CASE 517AJ
Typical Applications
1
• Battery Monitors
1
• Notebooks and PDA’s
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
• General Purpose Portable Devices
• General Purpose Low Voltage Applications
ORDERING INFORMATION
+V
CC
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
R
1
V
V
CC
R
PULL−UP
−
V
IN
V
O
O
V
T2
V
T1
R
+
LOAD
V
+
0
V
IN
Figure 2. Hysteresis Curve
R3
R
2
Figure 1. Inverting
Comparator with Hysteresis
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
LMV331/D
October, 2009 − Rev. 3
LMV331, LMV393, LMV339
MARKING DIAGRAMS
SC−70
TSOP−5
UDFN8
CASE 419A
CASE 483
CASE 517AJ
5
3CAAYWG
CAMG
CCAMG
G
G
G
1
CA = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
CCA= Specific Device Code
M
= Date Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
G
= Pb−Free Package
(Note: Microdot may be in either location)
= Pb−Free Package
(Note: Microdot may be in either location)
Micro8
CASE 846A
SOIC−8
CASE 751
ULLGA8
CASE 613AG
8
8
1
V393
V393
AYWG
G
ALYW G
XXMG
G
1
1
A
= Assembly Location
= Year
= Work Week
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XX = Specific Device Code
Y
W
G
M
= Date Code
G
= Pb−Free Package
= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−14
TSSOP−14
CASE 751A
CASE 948G
14
14
LMV
339
LMV339
AWLYWWG
ALYWG
G
1
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PACKAGE PINOUTS
SC−70/TSOP−5
Micro8 / SOIC−8 / UDFN8
SOIC−14 / TSSOP−14
1
5
4
V
+IN
GND
−IN
CC
1
2
3
4
8
V
Output A
1
2
14
CC
Output 2
Output 1
Output 3
Output 4
GND
+
2
7
6
13
12
11
−
+
Output B
Inputs B
−
Inputs A
GND
−
3
OUTPUT
3
V
CC
+
5
ULLGA8
(Top Views)
4
5
− Input 1
+ Input 4
*
)
)
*
NC
(Top Views)
1
4
+ Input 1
10 − Input 4
IN−
8
7
OUT
1
2
3
− Input 2
6
7
9
8
+ Input 3
*
)
)
*
2
3
NC
IN+
6
+ Input 2
− Input 3
VCC+
4
5
VCC−/GND
(Top Views)
NC
NC − No Internal Connection
(Top Views)
http://onsemi.com
2
LMV331, LMV393, LMV339
MAXIMUM RATINGS
Symbol
Rating
Value
5.5
Unit
V
−
V
S
Voltage on any Pin (referred to V pin)
V
Input Differential Voltage Range
Supply Voltage
150
V
IDR
T
Maximum Junction Temperature
°C
°C
°C
V
J
T
Storage Temperature Range
−65 to 150
260
stg
T
Mounting Temperature (Infrared or Convection (1/16″ From Case for 30 Seconds))
L
V
ESD
ESD Tolerance (Note 1)
Machine Model
Human Body Model
100
1000
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage Temperature Range (Note 2)
Value
Unit
V
V
2.7 to 5.0
CC
JA
q
Thermal Resistance
SC−70
°C/W
280
333
340
238
212
350
156
190
TSOP−5
ULLGA8
Micro8
SOIC−8
UDFN8
SOIC−14
TSSOP−14
1. Human Body Model, applicable std. MIL−STD−883, Method 3015.7. Machine Model, applicable std. JESD22−A115−A (ESD MM std. of
JEDEC) Field−Induced Charge−Device Model, applicable std. JESD22−C101−C (ESD FICDM std. of JEDEC).
2. The maximum power dissipation is a function of T
, q . The maximum allowable power dissipation at any ambient temperature is
J(MAX) JA
P
= (T
− T )/ . All numbers apply for packages soldered directly onto a PC board.
q
J(MAX) A JA
D
http://onsemi.com
3
LMV331, LMV393, LMV339
+
−
2.7 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for T = 25°C, V = 2.7 V, V = 0 V, V
= 1.35 V unless
A
CM
otherwise noted.)
Parameter
Input Offset Voltage
Symbol
Condition
Min
Typ
1.7
5
Max
Unit
mV
mV/°C
nA
V
IO
9
Input Offset Voltage Average Drift
Input Bias Current (Note 3)
Input Offset Current (Note 3)
Input Voltage Range
T
C
V
IO
I
B
< 1
< 1
0 to 2
120
23
I
IO
nA
V
V
CM
SAT
Saturation Voltage
V
I
≤ 1 mA
mV
mA
mA
SINK
Output Sink Current
I
O
V
O
≤ 1.5 V
5
Supply Current
LMV331
LMV393
LMV339
I
40
70
140
100
140
200
CC
+
−
2.7 V AC ELECTRICAL CHARACTERISTICS (T = 25°C, V = 2.7 V, R = 5.1 kW, V = 0 V unless otherwise noted.)
A
L
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Propagation Delay − High to Low
t
Input Overdrive = 10 mV
Input Overdrive = 100 mV
1000
500
ns
PHL
Propagation Delay − Low to High
t
Input Overdrive = 10 mV
Input Overdrive = 100 mV
800
200
ns
PLH
3. Guaranteed by design and/or characterization.
http://onsemi.com
4
LMV331, LMV393, LMV339
+
−
5.0 V DC ELECTRICAL CHARACTERISTICS (All limits are guaranteed for T = 25°C, V = 5 V, V = 0 V, V
= 2.5 V unless
A
CM
otherwise noted.)
Parameter
Input Offset Voltage
Symbol
Condition
Min
Typ
1.7
Max
Unit
mV
V
IO
T = −40°C to +85°C
9
A
Input Offset Voltage Average Drift
Input Bias Current (Note 4)
Input Offset Current (Note 4)
Input Voltage Range
T = −40°C to +85°C
5
mV/°C
nA
A
I
T = −40°C to +85°C
A
< 1
B
I
IO
T = −40°C to +85°C
A
< 1
nA
V
CM
0 to 4.2
50
V
Voltage Gain (Note 4)
A
20
10
V/mV
mV
V
Saturation Voltage
V
I
≤ 4 mA
200
400
700
SAT
SINK
T = −40°C to +85°C
A
Output Sink Current
I
O
V
O
≤ 1.5 V
84
60
mA
Supply Current
Supply Current
Supply Current
LMV331
I
I
I
120
150
mA
CC
T = −40°C to +85°C
A
LMV393
LMV339
100
170
200
250
mA
mA
mA
CC
CC
T = −40°C to +85°C
A
300
350
T = −40°C to +85°C
A
Output Leakage Current (Note 4)
T = −40°C to +85°C
A
0.003
1
+
−
5.0 V AC ELECTRICAL CHARACTERISTICS (T = 25°C, V = 5 V, R = 5.1 kW, V = 0 V unless otherwise noted.)
A
L
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Propagation Delay − High to Low
t
Input Overdrive = 10 mV
Input Overdrive = 100 mV
1500
900
ns
PHL
Propagation Delay − Low to High
t
Input Overdrive = 10 mV
Input Overdrive = 100 mV
800
200
ns
PLH
4. Guaranteed by design and/or characterization.
http://onsemi.com
5
LMV331, LMV393, LMV339
TYPICAL CHARACTERISTICS
(V = 5.0 V, T = 25°C, R = 5 kW unless otherwise specified)
CC
A
L
30
20
10
0
50
45
40
35
30
25
20
15
10
5
−40°C
−40°C
25°C
25°C
85°C
85°C
0
0
1
2
3
4
5
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 3. LMV331Supply Current vs. Supply
Voltage (Output High)
Figure 4. LMV331Supply Current vs. Supply
Voltage (Output Low)
180
160
140
120
100
80
600
500
400
300
200
100
0
25°C
85°C
25°C
85°C
−40°C
−40°C
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 5. VSAT vs. Output Current at
CC = 2.7 V
Figure 6. VSAT vs. Output Current at
CC = 5.0 V
V
V
http://onsemi.com
6
LMV331, LMV393, LMV339
NEGATIVE TRANSITION INPUT − V = 2.7 V
CC
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
28 mV
Negative
Figure 7. 10 mV Overdrive
Timebase
2.00 kS
−200
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
11.5 mV
Negative
Figure 8. 20 mV Overdrive
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Negative
Figure 9. 100 mV Overdrive
http://onsemi.com
7
LMV331, LMV393, LMV339
POSITIVE TRANSITION INPUT − V = 2.7 V
CC
Timebase
2.00 kS
−400
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
=11.5 mV
Positive
Figure 10. 10 mV Overdrive
Timebase
1.00 kS
−300
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
−49.5 mV
Positive
Figure 11. 20 mV Overdrive
Timebase
1.00 kS
−150
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Positive
Figure 12. 100 mV Overdrive
http://onsemi.com
8
LMV331, LMV393, LMV339
NEGATIVE TRANSITION INPUT − V = 5.0 V
CC
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
28 mV
Negative
Figure 13. 10 mV Overdrive
Timebase
2.00 kS
−200
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
11.5 mV
Negative
Figure 14. 20 mV Overdrive
Timebase
5.00 kS
−600
500 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Negative
Figure 15. 100 mV Overdrive
http://onsemi.com
9
LMV331, LMV393, LMV339
POSITIVE TRANSITION INPUT − V = 5.0 V
CC
Timebase
2.00 kS
−400
200 ns/div
1.0 GS/s
Trigger
Stop
Edge
−11.5 mV
Positive
Figure 16. 10 mV Overdrive
Timebase
1.00 kS
−300
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
−49.5 mV
Positive
Figure 17. 20 mV Overdrive
Timebase
1.00 kS
−150
100 ns/div
1.0 GS/s
Trigger
Stop
Edge
18 mV
Positive
Figure 18. 100 mV Overdrive
http://onsemi.com
10
LMV331, LMV393, LMV339
APPLICATION CIRCUITS
+V
CC
Basic Comparator Operation
The basic operation of a comparator is to compare two
input voltage signals, and produce a digital output signal by
determining which input signal is higher. If the voltage on
the non−inverting input is higher, then the internal output
transistor is off and the output will be high. If the voltage on
the inverting input is higher, then the output transistor will
be on and the output will be low. The LMV331/393/339 has
an open−drain output stage, so a pull−up resistor to a positive
supply voltage is required for the output to switch properly.
The size of the pull−up resistor is recommended to be
between 1 kW and 10 kW. This range of values will balance
two key factors; i.e., power dissipation and drive capability
for interface circuitry.
R
1
R
PULL−UP
−
V
IN
V
O
R
+
LOAD
V
+
R3
Figure 19 illustrates the basic operation of a comparator
and assumes dual supplies. The comparator compares the
R
2
input voltage (V ) on the non−inverting input to the
IN
Figure 20. Inverting
Comparator with
Hysteresis
reference voltage (V ) on the inverting input. If V is less
REF
IN
than V , the output voltage (V ) will be low. If V is
REF
O
IN
greater than V , then V will be high.
REF
O
When V is less than the voltage at the non−inverting
IN
V
OUT
node, V , the output voltage will be high. When V is
+
IN
+
V
greater than the voltage at V , then the output will be low.
+
The hysteresis band (Figure 21) created from the resistor
network is defined as:
V
REF
DV) + VT1 * VT2
0 V
Time
where V and V are the lower and upper trip points,
T1
T2
respectively.
V
IN
+
V
V
CC
O
+V
IN
+
3.0 k
V
V
O
V
T2
V
T1
0
+V
REF
−
V
IN
Figure 19.
Figure 21.
Comparators and Stability
V
T1
is calculated by assuming that the output of the
A common problem with comparators is oscillation due to
their high gain. The basic comparator configuration in
Figure 19 may oscillate if the differential voltage between
the input pins is close to the device’s offset voltage. This can
happen if the input signal is moving slowly through the
comparator’s switching threshold or if unused channels are
connected to the same potential for termination of unused
channels. One way to eliminate output oscillations or
‘chatter’ is to include external hysteresis in the circuit
design.
comparator is pulled up to supply when high. The
resistances R and R can be viewed as being in parallel
1
3
which is in series with R (Figure 22). Therefore V is:
2
T1
VCC R2
VT1
+
ǒ
Ǔ
R1 ø R3 ) R2
V
T2
is calculated by assuming that the output of the
comparator is at ground potential when low. The resistances
R and R can be viewed as being in parallel which is in
2
3
series with R (Figure 23). Therefore V is:
1
T2
ǒ
Ǔ
VCC R2 ø R3
Inverting Configuration with Hysteresis
An inverting comparator with hysteresis is shown in
Figure 20.
VT2
+
ǒ
Ǔ
R1 ) R2 ø R3
http://onsemi.com
11
LMV331, LMV393, LMV339
V
O
HIGH
V LOW
O
When V is much less than the voltage at the inverting
IN
input (V ), then the output is low. R can then be viewed
as being connected to ground (Figure 26). To calculate the
REF
2
+V
CC
+V
CC
voltage required at V to trip the comparator high, the
IN
following equation is used:
R1
Vref (R1 ) R2)
R1
R3
Vin1
+
V
T2
R2
When the output is high, V must less than or equal to
IN
V
T1
R2
R3
V
(V ≤ V ) before the output will be low again
REF
IN
REF
(Figure 27). The following equation is used to calculate the
R2
voltage at V to switch the output back to the low state:
IN
Vref (R1 ) R2) * VCCR1
Vin2
+
R2
Figure 22.
Figure 23.
V
HIGH
V
LOW
O
O
Non−inverting Configuration with Hysteresis
A non−inverting comparator is shown in Figure 24.
+V
CC
V
IN1
+V
CC
R2
R1
V = V
V = V
A
REF
A
REF
R
V
REF
PULL−UP
R1
R2
−
V
O
V
IN2
V
IN
V
A
Figure 26.
Termination of Unused Inputs
Figure 27.
R
+
LOAD
R1
Proper termination of unused inputs is a good practice to
keep the output from ‘chattering.’ For example, if one
channel of a dual or quad package is not being used, then the
inputs must be connected to a defined state. The
R2
Figure 24.
recommended connections would be to tie one input to V
and the other input to ground.
CC
The hysteresis band (Figure 25) of the non−inverting
configuration is defined as follows:
DVin + VCCR1ńR2
V
CC
V
O
V
IN2
V
IN1
0
V
IN
Figure 25.
http://onsemi.com
12
LMV331, LMV393, LMV339
ORDERING INFORMATION
†
Order Number
Number of Channels
Specific Device Marking
Package Type
Shipping
LMV331SQ3T2G
Single
Single
Single
Dual
CCA
SC−70
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
(Pb−Free)
LMV331SN3T1G
LMV331MU3TBG*
LMV393DMR2G
LMV393DR2G
3CA
3C
TSOP−5
(Pb−Free)
ULLGA8
(Pb−Free)
V393
V393
CA
Micro8
(Pb−Free)
Dual
SOIC−8
(Pb−Free)
LMV393MUTAG
LMV339DR2G
Dual
UDFN8
(Pb−Free)
Quad
Quad
LMV339
SOIC−14
(Pb−Free)
LMV339DTBR2G
LMV
339
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact factory.
http://onsemi.com
13
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
http://onsemi.com
14
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
SOLDERING FOOTPRINT*
_
_
2.50
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
UDFN8 1.8x1.2, 0.4P
CASE 517AJ−01
ISSUE O
NOTES:
A B
E
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.10
C
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
NOTE 5
0.10
C
TOP VIEW
(A3)
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
MILLIMETERS
0.05
C
C
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
A
A
0.05
A3
b
b2
D
E
e
0.127 REF
0.15
0.25
A1
SEATING
PLANE
C
0.30 REF
SIDE VIEW
1.80 BSC
1.20 BSC
0.40 BSC
e/2
DETAIL A
8X L
L
0.45
0.55
0.03
e
L1 0.00
L2
(b2)
0.40 REF
4
5
1
MOUNTING FOOTPRINT*
SOLDERMASK DEFINED
(L2)
8
8X
8X b
7X
0.22
0.66
M
M
C A B
0.10
0.05
BOTTOM VIEW
NOTE 3
C
1.50
1
0.32
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
D
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
H
E
E
MILLIMETERS
INCHES
NOM
−−
0.003
0.013
0.007
0.118
DIM
A
A1
b
c
D
MIN
−−
0.05
0.25
0.13
2.90
2.90
NOM
−−
MAX
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
PIN 1 ID
1.10
0.15
0.40
0.23
3.10
3.10
e
0.08
b 8 PL
0.33
M
S
S
0.08 (0.003)
T B
A
0.18
3.00
E
3.00
0.118
e
L
0.65 BSC
0.55
4.90
0.026 BSC
0.021
0.193
0.40
4.75
0.70
5.05
0.016
0.187
0.028
0.199
SEATING
PLANE
H
−T−
E
A
0.038 (0.0015)
L
A1
c
SOLDERING FOOTPRINT*
1.04
0.38
8X
8X 0.041
0.015
3.20
4.24
5.28
0.126
0.167 0.208
0.65
6X0.0256
SCALE 8:1
mm
inches
ǒ
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
18
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
ULLGA8, 1.5x1.5, 0.5P
CASE 613AG−01
ISSUE O
A
B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
MILLIMETERS
PIN ONE
E
DIM MIN
−−−
A1 0.00
0.20
b1 0.30
MAX
0.40
0.05
0.30
0.40
REFERENCE
A
b
0.10
C
D
E
e
L
L1
L3
1.50 BSC
1.50 BSC
0.50 BSC
0.25 0.35
0.05 REF
0.15 REF
0.10
C
TOP VIEW
SIDE VIEW
0.05
0.05
C
C
A
8X
MOUNTING FOOTPRINT*
SEATING
PLANE
C
A1
8X
0.51
7X
0.32
PACKAGE
OUTLINE
b1
e
8X L
3
1
1.65
L3
1
0.50
PITCH
0.42
7
5
8X b
DIMENSIONS: MILLIMETERS
L1
0.10 C A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
C
0.05
BOTTOM VIEW
http://onsemi.com
19
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
20
LMV331, LMV393, LMV339
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
LMV331/D
相关型号：
©2020 ICPDF网 联系我们和版权申明