LC450029PKB_17 [ONSEMI]
Duty General-Purpose LCD Driver;
| 型号： | LC450029PKB_17 |
| 厂家： | 
ONSEMI |
| 描述： | Duty General-Purpose LCD Driver CD |
| 文件： | 总25页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC450029PKB
1/4 and 1/3-Duty General-Purpose
LCD Driver
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Overview
The LC450029PKB is 1/4 duty and 1/3 duty general-purpose microcontroller-
controlled LCD drivers that can be used in applications such as frequency
display in products with electronic tuning. In addition to being capable to drive
up to 208 segments directly. The internal oscillation circuit helps to reduce the
number of external resistors and capacitors required. The chip shape is slim for
COG (Chip-On-Glass) implementation. The operating temperature range is
from 40C to +105C
Application
Car or general consumer electronic LCD display equipment.
Features
Selectable 1/4-duty or 1/3-duty drive by the serial control data
When 1/4-duty: Capable of driving up to 208 segments
When 1/3-duty: Capable of driving up to 159 segments
1/3-bias only
Serial data input supports CCB* format communication with the system
controller. (For 5 V operation only)
The power-saving mode is selectable by the serial control data, and supports
low power consumption.
Adjustable the frame frequency of the common and segment output waveforms
by the serial control data
Selectable the internal oscillator operating or external clock operating mode by
the serial control data
High generality, since display data is displayed directly without the
intervention of a decoder circuit.
The
pad allows all LCD segments to be forced to the off state.
INH
With a built-in oscillator circuit
(External resistors and capacitors are unnecessary.)
The stability of the LCD bias voltage is high by a built-in LCD bias generator
with voltage-follower buffers.
Shipping form: Chip with Au bumps in tray.
Allowable operating voltage (V , V I)
: +4.5 V to +6.0 V
DD DD
Allowable wide operating temperature ranges
: 40C to +105C
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
June 2017 - Rev. 1
1
Publication Order Number :
LC450029PKB/D
LC450029PKB
Specifications
Absolute Maximum Ratings at Ta = 25C, V
= 0 V
SS
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum supply voltage
V
V
max,
V
=V I
DD DD
DD
DD
0.3 to +6.5
0.3 to +6.5
I max
Input voltage
V
V
V
I
1
2
CE, CL, DI,
OSCI
INH
IN
V
0.3 to V I+0.3
IN
DD
Output voltage
Output current
S1 to S53, COM1 to COM4
S1 to S53
0.3 to V +0.3
V
OUT
DD
1
300
3
A
mA
C
C
OUT
OUT
I
2
COM1 to COM4
Operating temperature
Storage temperature
Topr
Tstg
40 to +105
55 to +125
(Note) Power supply pads (V , V I) should connect all pads to the same power supply.
DD DD
(See sample applications circuits)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40 to +105C, V
SS
= 0 V
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
Unit
V
min
4.5
max
6.0
V
V
,
I
V
=V I
DD DD
DD
DD
Input high-level voltage
Input low-level voltage
V
V
V
V
1
2
CE, CL, DI,
INH
OSCI: External clock operating mode
CE, CL, DI,
0.8V
0.8V
6.0
IH
DD
V
V
0.2V
0.2V
I
IH
DD
0
DD
1
INH
I
IL
DD
V
2
OSCI: External clock operating mode
0
I
IL
DD
External
clock
operating
f
OSCI: External clock operating mode
[Figure 4]
CK
10
300
50
600
70
kHz
%
frequency
External clock duty cycle
D
OSCI: External clock operating mode
[Figure 4]
CK
30
Data setup time
Data hold time
CE wait time
tds
tdh
tcp
tcs
tch
tH
tL
tr
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 2] [Figure 3]
[Figure 5] [Figure 6]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
tf
switching time
tc
, CE
INH
INH
10
(Note) Power supply pads (V , V I) should connect all pads to the same power supply.
DD DD
(See sample applications circuits)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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2
LC450029PKB
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Hysteresis
Symbol
Pin
Conditions
Unit
V
min
max
V 1
H
CE, CL, DI,
OSCI
INH
INH
0.1V
I
I
DD
V 2
H
External clock operating mode
0.1V
DD
Input high-level
current
I
I
1
CE, CL, DI,
OSCI
V = 6.0 V
I
5.0
IH
IH
A
A
2
V = V I, External clock
DD
operating mode
I
5.0
Input low-level
current
I
I
1
CE, CL, DI,
OSCI
V = 0 V
I
INH
5.0
5.0
IL
IL
2
V = 0 V, External clock
I
operating mode
Output high-
level voltage
V
V
1
2
S1 to S53
I
I
= 20 A
V
OH
O
O
DD
0.9
V
V
COM1
= 100 A
V
DD
0.9
OH
to COM4
S1 to S53
Output low-level
voltage
V
V
1
I
I
= 20 A
0.9
0.9
DD
OL
OL
O
O
2
COM1
= 100 A
to COM4
S1 to S53
Output middle-
level voltage *1
V
V
V
V
1
2
3
4
I
I
I
I
= ±20 A
= ±20 A
= ±100 A
= ±100 A
2/3V
2/3V
MID
MID
MID
MID
O
O
O
O
DD
0.9
+0.9
S1 to S53
1/3V
1/3V
DD
DD
0.9
+0.9
V
COM1
2/3V
2/3V
DD
DD
to COM4
COM1
0.9
+0.9
1/3V
1/3V
DD
DD
to COM4
Internal
0.9
+0.9
Oscillator
fosc
Internal oscillator operating
mode
210
300
40
390
100
kHz
frequency
oscillator circuit
Current drain
(Total value of
I
I
1
V
V
, V
I
<Power-saving mode>
DD
DD DD
V
= V I = 6.0 V
DD
DD
V
and V I)
DD
DD
2
DD
, V
DD DD
I
<Internal oscillator operating mode>
= V I = 6.0 V
V
200
170
400
340
DD
DD
Driver outputs are open.
A
I
3
DD
V
, V
DD DD
I
<External clock operating mode>
V
= V I = 6.0 V
DD
DD
= 300 kHz
f
CK
Driver outputs are open.
*1: Excluding the amount of voltage drop of the LCD BIAS GENERATOR which generates V 1 and V 2.
DD DD
(See Figure 1.)
V
DD
Excluding the amount of voltage drop of the LCD BIAS GENERATOR
To Common drivers and Segment drivers
LCD BIAS
GENERATOR
V
SS
V
1
DD
V
2
DD
[Figure 1]
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LC450029PKB
(1) When CL is stopped at the low level
V
1
IH
CE
V
1
IL
tH
tL
V
1
IH
CL 50%
V
1
IL
tr
tf
tcp tcs
tch
V
1
1
IH
DI
V
IL
tds
tdh
[Figure 2]
(2) When CL is stopped at the high level
V
1
IH
CE
V 1
IL
tL
tH
V
1
IH
50%
IL
CL
DI
V
1
tf
tr
tcp tcs
tch
V
1
IH
V
1
IL
tds
tdh
[Figure 3]
(3) OSCI pad clock timing in external clock operating mode
1
t
H
t
L
CK
CK
f
=
[kHz]
CK
t
t
H+t
L
L
CK
CK
CK
V
2
IH
50%
IL
OSCI
t
H
V
2
CK
H+t
D
=
100[%]
CK
CK
[Figure 4]
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4
LC450029PKB
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CONTROL
REGISTER
CLOCK
GENERATOR
OSCI
V
DD
SHIFT REGISTER
LCD BIAS
GENERATOR
CCB INTERFACE
+
-
+
-
V
SS
V
I
DD
REGULATOR
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5
LC450029PKB
Pad Functions
Handling
when
Symbol
Pad No.
Function
Active
-
I/O
O
unused
Common driver outputs.
COM1 to
COM4
The frame frequency is fo[Hz].
2 to 5
OPEN
OPEN
COM4 pad outputs the V
SS
level in 1/3-duty.
Segment outputs for displaying the display data transferred by serial data input.
S51 pad outputs the V level in 1/4-duty.
SS
S52 pad and S53 pad output the V
S1 to S53
6 to 58
-
O
level at the control data DN=“0”.
SS
level at external clock operating mode.
S53 pad outputs the V
SS
Display off control input
• INH = low (V ) ...Display forced off (V
level Output)
)
SS
SS
S1 to S53 = low (V
)
SS
COM1 to COM4 = low (V
SS
The internal oscillator stops.
Stops inputting external clock.
Serial data transfer can be used.
• INH = high (V )...Display on
DD
GND
INH
61
L
I
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(V )
SS
(External clock operating mode)
While display on, LCD outputs force off (V
by the control data BU=“1”.
level output)
SS
While display on, LCD outputs off (off waveforms output)
by the control data SC=“1”.
Serial data transfer inputs. Must be connected to the controller.
CE: Chip enable
CE
DI
62
63
64
H
-
I
I
I
GND
(V
DI: Transfer data
)
SS
CL
CL: Synchronization clock
VLOGIC
65
Used to monitor pad for the power supply voltage of the logic circuit.
-
-
O
-
OPEN
-
Power supply pad. A power voltage of 4.5 to 6.0V must be applied to these
pads.
V
I
66 to 71
DD
This pad can also be used as the external clock input pad when the external
clock operating mode is selected by control data.
GND
OSCI
72
-
I
(V
)
SS
This pad must be connected to GND at internal oscillator operating mode.
V
73 to 90
91
Ground pad. Must be connected to ground.
-
-
-
-
-
SS
V
V
2
Used to monitor pad for the LCD drive bias voltage (1/3 V ).
DD
O
O
OPEN
OPEN
DD
1
92
Used to monitor pad for the LCD drive bias voltage (2/3 V ).
DD
DD
Power supply pad. A power voltage of 4.5 to 6.0V must be applied to these
pads.
V
93 to 105
-
-
-
-
DD
DUMMY
1, 59,
Dummy pad. Must not be used.
OPEN
OPEN
60, 106
(Note)
Power supply pads (V , V I) should connect all pads to the same power supply.
DD DD
(See sample applications circuits)
GND pad (V ) should connect all pads to the GND.
SS
When logic input pads (INH, CE, DI, CL, OSCI) are not used, must be fixed to GND (V ).
SS
Must not use monitor pads (VLOGIC, V 1, V 2) in an external circuit.
DD DD
Must not connect dummy pad (DUMMY) mutually. Moreover, never use it in an external circuit.
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LC450029PKB
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D53 D54
D105 D106
D47 D48 D49 D50 D51 D52
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EXF
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
18 bits
Display data
52 bits
DD
2 bits
8 bits
1
0
0
0
0
0
1
0
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
52 bits
Fixed data
18 bits
DD
2 bits
1
0
0
0
0
0
1
0
D151 D152
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
48 bits
Fixed data
22 bits
DD
2 bits
1
0
0
0
0
0
1
0
D153 D154
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
56 bits
Fixed data
14 bits
DD
2 bits
Note: DD is the direction data.
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LC450029PKB
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52
0
0
0
0
0
0
EXF
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
18 bits
Display data
52 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
0
0
1
0
D53 D54
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
52 bits
Fixed data
18 bits
DD
2 bits
8 bits
0
0
0
0
1
0
0
0
0
0
1
0
D105 D106
D151 D152
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
48 bits
Fixed data
22 bits
DD
2 bits
8 bits
D199 D200 D201 D202
D205 D206 D207 D208
1
0
0
0
0
0
1
0
D153 D154
D203 D204
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
56 bits
Fixed data
14 bits
DD
2 bits
8 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D208 ............ Display data
• EXF ....................... Ratio of dividing frequency in external clock operating mode setting control data
• DT ......................... 1/4-duty drive or 1/3-duty drive switching control data
• DN ......................... The number of the maximum display segments setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off (off waveform output) control data
• BU ......................... Normal mode/power-saving mode control data
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LC450029PKB
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
0
0
0
0
0
0
0
0
EXF
0
0
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
16 bits
Display data
54 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
0
0
1
0
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
54 bits
Fixed data
16 bits
DD
2 bits
1
0
0
0
0
0
1
0
D155 D156 D157 D158 D159
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
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LC450029PKB
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
0
0
0
0
0
0
0
0
EXF
0
0
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
16 bits
Display data
54 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
0
0
1
0
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
54 bits
Fixed data
16 bits
DD
2 bits
1
0
0
0
0
0
1
0
D155 D156 D157 D158 D159
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D208 ............ Display data
• EXF ....................... Ratio of dividing frequency in external clock operating mode setting control data
• DT ......................... 1/4-duty drive or 1/3-duty drive switching control data
• DN ......................... The number of the maximum display segments setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off (off waveform output) control data
• BU ......................... Normal mode/power-saving mode control data
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LC450029PKB
Serial Data Transfer Example
1. 1/4 duty
• When 153 or more segments are used
All 320 bits (include CCB address) of serial data must be sent.
8 bits
72 bits
1
0
0
0
0
0
1
0
D1 D2
D53 D54
D105 D106
D153 D154
D47 D48 D49 D50 D51 D52
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EXF
0
0
0
0
0
0
0
0
0
0
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
1
1
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
D151 D152
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 153 segments are used
One of 80, 160 and 240 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D52 display data, the control data and DD=“00”) must always
be sent.
8 bits
72 bits
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52
0
0
0
0
0
0
EXF
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
2. 1/3 duty
• When 109 or more segments are used
All 240 bits (include CCB address) of serial data must be sent.
8 bits
72 bits
1
0
0
0
0
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
0
0
0
EXF
0
0
0
0
0
0
0
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
D155 D156 D157 D158 D159
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 109 segments are used
Either 80 or 160 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D54 display data, the control data and DD=“00”) must always
be sent.
8 bits
0
72 bits
1
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
EXF
0
0
0
DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
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11
LC450029PKB
Control Data Functions
(1) EXF … Ratio of dividing frequency in external clock operating mode setting control data
This control data sets the ratio of dividing frequency of the external clock which input into the OSCI pad, when the
external clock operating mode (OC=“1”) is set. However, this data is effective only when external clock operating
mode (OC= “1”) is set. The frame frequency is adjustable by setting EXF, FC0 to FC2 and OC.
EXF
Ratio of dividing frequency in external clock operating mode
0
f
/ 8
CK
f
1
CK
(2) DT …1/4-duty drive or 1/3-duty drive switching control data
This control data bit selects either 1/4-duty drive or 1/3-duty drive.
DT
Drive scheme
1/4-duty drive
1/3-duty drive
S51 pad’s state
0
Low (V ) level output
SS
1
S51 (segment output)
(3) DN …The number of the maximum display segments setting control data
This control data bit sets the number of the maximum display segments.
The number of the maximum display segments
Pad’s state
DN
1/4 duty
1/3 duty
S52
S53
0
1
Up to 200 segments
Up to 208 segments
Up to 153 segments
Up to 159 segments
“L” (V
)
“L” (V
)
SS
SS
S53 (segment output)
S52 (segment output)
(Note) S53 pad outputs V level in external clock operating mode.
SS
(4) FC0 to FC2 …Common/segment output waveform frame frequency control data
These control data bits set the frame frequency of the common and segment output waveforms. The frame frequency
is adjustable by setting EXF, FC0 to FC2 and OC.
Control data
Frame frequency fo[Hz]
External clock operating mode
(The control data
External clock operating mode
(The control data
Internal oscillator operating mode
(The control data OC=“0”,
fosc=300[kHz]typ)
FC0
FC1
FC2
OC=“1”, EXF=“0”)
OC=“1”, EXF=“1”)
Case is f =300[kHz].
CK
Case is f =38[kHz].
CK
fosc/6144 =48.8[Hz]typ
fosc/4608 =65.1[Hz]typ
fosc/3072 =97.7[Hz]typ
fosc/2304 =130.2[Hz]typ
fosc/1536 =195.3[Hz]typ
fosc/1152 =260.4[Hz]typ
fosc/768 =390.6[Hz]typ
fosc/3072 =97.7[Hz]typ
f
f
f
/6144 =48.8[Hz]
/4608 =65.1[Hz]
/3072 =97.7[Hz]
f
f
f
/768 =49.5[Hz]
/576 =66.0[Hz]
/384 =99.0[Hz]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CK
CK
CK
CK
CK
CK
f
f
f
/2304 =130.2[Hz]
/1536 =195.3[Hz]
/1152 =260.4[Hz]
/768 =390.6[Hz]
f
f
f
/288 =131.9[Hz]
/192 =197.9[Hz]
/144 =263.9[Hz]
/96 =395.8[Hz]
CK
CK
CK
CK
CK
CK
f
f
CK
CK
f
/3072 =97.7[Hz]
f
/384 =99.0[Hz]
CK
CK
(5) OC …Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
Internal oscillator operating mode
External clock operating mode
S53 pad’s state
0
S53 (segment output)
1
Low (V ) level output
SS
(6) SC … Segment on/off (off waveform output) control data
This control data bit controls the on/off (off waveform output) state of all the segments.
SC
Display state
0
On
1
Off of all the segments (off waveform output)
(7) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
0
Normal mode
Power-saving mode
All of the common and segment output pads output the V
SS
In this mode, the internal oscillator circuit stops oscillation if the IC is in the internal oscillator operating mode
(OC=0), and the IC stops receiving external clock signals if the IC is in the external clock operating mode (OC=1).
level.
1
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12
LC450029PKB
Display Data and Output Pad Correspondence (1/4 Duty)
Output pad
COM1
COM2
COM3
COM4
Output pad
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
COM1
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
-
COM2
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
-
COM3
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
-
COM4
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
-
S1
D1
D2
D3
D4
S2
D5
D6
D7
D8
S3
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
S4
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
D201
D205
D202
D206
D203
D207
D204
D208
(Note) In external clock operating mode, S53 pad outputs V level. When DN is “0”, S52 pad and S53 pad output
SS
V
level. When duty is 1/4, S51 pad outputs V level.
SS
SS
For example, the table below lists the output states for the S21 output pad.
Display data
Output pad (S21) state
D81
0
D82
0
D83
0
D84
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
The LCD segment corresponding to COM4 is on.
0
0
0
1
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
The LCD segment corresponding to COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM2, COM3, and COM4 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1, COM3, and COM4 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM4 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
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13
LC450029PKB
Display Data and Output Pad Correspondence (1/3 Duty)
Output pad
COM1
COM2
COM3
Output pad
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
COM1
D82
COM2
D83
COM3
D84
S1
D1
D2
D3
S2
D4
D5
D6
D85
D86
D87
S3
D7
D8
D9
D88
D89
D90
S4
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D91
D92
D93
S5
D94
D95
D96
S6
D97
D98
D99
S7
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
(Note) In external clock operating mode, S53 pad outputs V level. When DN is “0”, S52 pad and S53 pad output
SS
V
level.
SS
For example, the table below lists the output states for the S21 output pad.
Display data
Output pad (S21) state
D61
0
D62
0
D63
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segment corresponding to COM3 is on.
0
0
1
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segment corresponding to COM1 is on.
1
0
0
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
0
1
1
1
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14
LC450029PKB
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
Frame frequency fo[Hz]
V
V
V
V
V
V
V
V
DD
DD
DD
SS
1
2
COM1
COM2
COM3
COM4
DD
DD
DD
SS
1
2
V
DD
V
DD
V
DD
V
SS
1
2
V
V
V
V
DD
DD
DD
SS
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
1
2
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when only LCD segments
corresponding to COM1 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when only LCD segments
corresponding to COM2 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when only LCD segments
corresponding to COM3 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
V
V
V
V
DD
DD
DD
SS
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
1
2
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when only LCD segments
corresponding to COM4 are on.
V
V
V
V
DD
DD
DD
SS
1
2
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
V
V
V
V
DD
DD
DD
SS
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
1
2
(Note) The frame frequency fo[Hz] is adjustable by setting control data (EXF, FC0 to FC2 and OC).
(See “Control Data Functions” for details)
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15
LC450029PKB
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
Frame frequency fo[Hz]
V
V
V
V
DD
DD
DD
SS
1
2
COM1
COM2
COM3
V
V
V
V
DD
DD
DD
SS
1
2
V
V
V
V
DD
DD
DD
SS
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when only LCD segments
corresponding to COM1 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when only LCD segments
corresponding to COM2 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when only LCD segments
corresponding to COM3 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
1
2
V
V
V
V
DD
DD
DD
SS
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are on.
1
2
(Note) The frame frequency fo[Hz] is adjustable by setting control data (EXF, FC0 to FC2 and OC).
(See “Control Data Functions” for details)
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16
LC450029PKB
INH
Display Control and the
Pad
Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to
D159 and the control data) is undefined when power is first applied. Applications should set the INH pad low at the
same time as power is applied to turn off the display (This sets the S1 to S53 and COM1 to COM4 pads the V level.)
SS
and during this period send serial data from the controller. The controller should then set the INH pad high after the data
transfer has completed. This procedure prevents meaningless display at power on. V
and V I are connected with
DD
DD
the same power supply. The timing of turn on and turn off for V
(See from Figure 5 to Figure 8)
and V I should be same time.
DD
DD
1/4 duty
t2
t1
V
=V I
DD DD
tc
INH
CE
V
1
IL
V
1
IL
Initialization of display data
and control data
Update display data
ON
S1 to S53
COM1 to COM4
OFF (V
level output)
OFF (V
level output)
SS
SS
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10s or more.
[Figure 5]
1/3 duty
t2
t1
V
=V I
DD DD
tc
INH
CE
V
1
IL
V
1
IL
Initialization of display data
and control data
Update display data
ON
S1 to S53
COM1 to COM4
OFF (V
level output)
OFF (V
level output)
SS
SS
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10s or more.
[Figure 6]
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17
LC450029PKB
In external clock operating mode
t1
t2
V
=V I
DD DD
OSCI
tc
V
1
IL
INH
CE
V
1
IL
Update display data
ON
Initialization of display data
and control data (OC=1)
S1 to S53
COM1 to COM4
OFF (V
level output)
OFF (V
level output)
SS
SS
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10s or more.
OSCI pad should be input an external clock at INH is high level.
[Figure 7]
All segments off (off waveforms output)
V
=V I
DD DD
INH
CE
SC=1
SC=0
Initialization of display data
and control data (SC=0)
V
V
SS
SS
COM1
S1
V
V
SS
SS
level output)
OFF (V
OFF
(off waveforms output)
ON
ON
OFF
level output)
SS
(V
SS
[Figure 8]
Power-saving mode
V
=V I
DD DD
INH
CE
BU=1
BU=0
Initialization of display data
and control data (BU=0)
OFF
level output)
OFF
level output)
OFF
level output)
S1 to S53
COM1 to COM4
(V
(V
(V
ON
SS
ON
SS
SS
Power-saving mode
[Figure 9]
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18
LC450029PKB
Notes on Controller Transfer of Display Data
When using the LC450029PKB in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and
in 1/3 duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer
all of the display data within 30ms to maintain the quality of displayed image.
About peripheral circuit of the input pad
(1) Processing of unused OSCI pad
When OSCI pad is not to be used, select the internal oscillator operating mode (control data OC=“0”), and OSCI pad
is connected to GND.
OSCI
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19
LC450029PKB
Sample Applications Circuit 1
1/4 duty, Display data (D1 to D208), Internal oscillator operating mode
+5V
V
I
*4
OSCI
COM1
COM2
COM3
COM4
S1
DD
*2
*2
C
C
V
V
DD
1
2
S2
S3
S4
(OPEN)
(OPEN)
DD
V
V
DD
SS
S5
VLOGIC
(OPEN)
S50
S51
S52
S53
INH
CE
CL
DI
(OPEN) *3
Controller
Sample Applications Circuit 2
1/4 duty, Display data (D1 to D204), External clock operating mode
+5V
V
I
OSCI
COM1
COM2
COM3
COM4
S1
DD
*2
*2
C
C
V
V
DD
1
2
S2
S3
S4
(OPEN)
(OPEN)
DD
V
V
DD
SS
S5
VLOGIC
INH
(OPEN)
S50
S51
S52
S53
(OPEN) *3
(OPEN) *5
CE
CL
DI
Controller
*2 Connect capacitors between a power supply line and GND for noise removal and power supply stabilization.
Determine the value of a capacitor, after an actual circuit board estimates.
*3 In 1/4 duty, S51 pad outputs V level.
SS
*4 When OSCI pad is not to be used, select the internal oscillator operating mode (control data OC=“0”),
and OSCI pad is connected to GND.
*5 In external clock operating mode, S53 pad outputs V level.
SS
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20
LC450029PKB
Sample Applications Circuit 3
1/3 duty, Display data (D1 to D159), Internal oscillator operating mode
V
I
+5V
OSCI
DD
COM1
COM2
COM3
COM4
S1
*2
*2
C
C
(OPEN) *6
V
V
DD
1
2
S2
(OPEN)
(OPEN)
DD
S3
V
V
DD
SS
S4
S5
VLOGIC
INH
(OPEN)
S50
S51
S52
S53
CE
CL
DI
Controller
*2 Connect capacitors between a power supply line and GND for noise removal and power supply stabilization.
Determine the value of a capacitor, after an actual circuit board estimates.
*6 In 1/3 duty, COM4 pad outputs V level.
SS
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21
LC450029PKB
The Notes on Use
Important things for stability operation of IC are shown as follows. The contents indicated below do not guarantee IC
operation and the characteristic. Moreover, the example of an application circuit written in these specifications is for
explaining internal operation and usage. Therefore, please perform the design in consideration of the specification of
operation and terms and conditions in the actual LCD panel.
(1) The design of power supply
All power supply pads are connected to the power supply, and do not set open.
(2) ITO (Indium Tin Oxide) wiring
By designing the wire of power supply (V , V I, V ) wide and short, make the parasitic resistance of ITO
DD DD SS
wiring into the minimum.
(3) Signal wiring and connection
The DUMMY pad does not connect to anywhere, and sets open.
(4) Processing of unused input pad
For CMOS process, if an input pad is in open state, operation of IC may become unstable, or unnecessary power
supply current may flow through it. Please be sure to connect the empty pad of a logic input to V
.
SS
(5) The measure against shading
The optical irradiation to IC causes the mis-operation of IC. When IC is implemented, take the measures against
shading about the surface, back and side of IC.
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22
LC450029PKB
PAD Locations (Bump Side View)
MODEL NAME
Alignment Mark #3
(C-Type)
(0, 0)
Alignment Mark #1
(A-Type)
Y
Alignment Mark #2
(B-Type)
X
Chip dimensions (X, Y, S are based on the dicing center.)
X=1.00mm Y=4.08mm S=4.08mm2 Wafer thickness=400m (typ)
Au Bump dimensions (typ)
Size
Item
PAD No.
X [m]
Y [m]
S [m2]
1 to 59
60 to 106
108
68
27
42
2916
Bump Size
2856
10 to 58
50
-
-
-
Min. Bump Pitch
1 to 9, 59 to 106
10 to 58, 66 to 71,
73 to 90, 93 to 105
1 to 9, 59 to 65, 72,
91 to 92, 106
23
-
Min. Bump Clearance
Bump Height
-
-
-
All pads
17
Alignment marks
(1) A-Type
(2) B-Type
(3) C-Type
10
30
50
80
20
50
Unit: m
60
80
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23
LC450029PKB
Center coordinates of PADs
(All x/y coordinates represent the position of the center of each PAD)
PAD
PAD
X
Y
PAD
PAD
X
Y
PAD
No.
PAD
X
Y
No.
Name
[m]
[m]
No.
Name
[m]
[m]
Name
[m]
[m]
1
DUMMY
COM1
COM2
COM3
COM4
S1
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
1950
1369
1276
1183
1090
932
856
780
704
607
557
507
457
407
357
307
257
207
157
107
57
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
S36
S37
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
-380
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
-943
-993
81
82
V
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
10
SS
2
V
75
SS
3
S38
-1043
-1093
-1143
-1193
-1243
-1293
-1343
-1393
-1443
-1493
-1543
-1593
-1643
-1693
-1743
-1793
-1950
-1943
-1665
-1525
-1385
-1245
-1161
-1071
-1006
-941
83
V
140
SS
4
S39
84
V
205
SS
5
S40
85
V
270
SS
6
S41
86
V
335
SS
7
S2
S42
87
V
400
SS
8
S3
S43
88
V
465
SS
9
S4
S44
89
V
530
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
S5
S45
90
V
595
SS
S6
S46
91
V
V
2
668
DD
S7
S47
92
1
739
DD
S8
S48
93
V
811
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
S9
S49
94
V
876
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S50
95
V
V
V
V
V
V
V
V
V
V
V
941
S51
96
1006
1071
1136
1201
1266
1331
1396
1461
1526
1591
1943
S52
97
S53
98
DUMMY
DUMMY
INH
99
100
101
102
103
104
105
106
7
CE
-43
DI
-93
CL
-143
-193
-243
-293
-343
-393
-443
-493
-543
-593
-643
-693
-743
-793
-843
-893
VLOGIC
V
V
V
V
V
V
I
I
I
I
I
I
DUMMY
DD
DD
DD
DD
DD
DD
-876
-811
-746
OSCI
-650
V
-510
SS
V
-445
SS
V
-380
SS
V
-315
SS
V
-250
SS
V
-185
SS
V
-120
SS
V
-55
SS
Center coordinates of alignment marks
(All x/y coordinates represent the position of the center of each alignment mark)
Alignment mark
TYPE
X [m]
Y [m]
1
2
3
A
B
C
400
400
-380
-1800
1790
1800
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24
LC450029PKB
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
1 / Waffle Pack
Wafer
(Pb-Free)
LC450029PKB-XT
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
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25
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