LC450210PCH-T3 [ONSEMI]
Duty Dot Matrix LCD Controller Driver;
| 型号： | LC450210PCH-T3 |
| 厂家： | 
ONSEMI |
| 描述： | Duty Dot Matrix LCD Controller Driver CD |
| 文件： | 总53页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC450210PCH
1/8 to 1/16 Duty Dot Matrix LCD
Controller Driver
Overview
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The LC450210PCH is the 1/8 to 1/16 duty dot matrix LCD controller driver. By
controlling this driver with a microcontroller, it is used in applications such as
character display and simple graphic display etc. This driver can drive a LCD
panel of up to 3,200 dots (16 16 dot font: 1-line display of up to 12 digits and
128 segments, 5 7 dot font: 2-line display of up to 40 digits). The operating
temperature range is from 40 to +105C.
Features
1. Selectable duty ratio by serial data: 1/8 duty to 1/16 duty
1/8 duty: 8 200 = 1,600 dots
1/9 duty: 9 200 = 1,800 dots
1/10 duty: 10 200 = 2,000 dots
1/11 duty: 11 200 = 2,200 dots
1/12 duty: 12 200 = 2,400 dots
1/13 duty: 13 200 = 2,600 dots
1/14 duty: 14 200 = 2,800 dots
1/15 duty: 15 200 = 3,000 dots
1/16 duty: 16 200 = 3,200 dots
2. Selectable LCD bias voltage ratio by serial data: 1/4 bias or 1/5 bias
3. Selectable inversion drive of LCD drive waveform by serial data: line inversion or frame inversion
4. Adjustable frame frequency of common and segment output waveforms and clock frequency of voltage booster by
serial data, for preventing interference with the frequency of the backlight.
5. Selectable operation modes by serial data: power-saving mode (maintains display data),
the state of display (ON, all ON, all OFF, all forced OFF)
6. Built-in oscillator circuit (built-in resistor and capacitor for oscillation)
7. Selectable fundamental clock operating modes by serial data: internal oscillator operating mode or external clock
operating mode
8. Input of serial data supports CCB* format (for 5 V and 3 V)
9. Selectable voltage range of power supply for logic block by setting REGE pad
(V ): +4.5 V to +5.5 V (5 V power supply (REGE = VDD))
DD
+2.7 V to +3.6 V (3 V power supply (REGE = VSS))
10. Built-in quadruple and quintuple voltage booster with discharge function
Base voltage of boosting (V
2): +3.2 V (Typ.)
(5 V power supply (REGE = VDD))
BTI
BTI
(V
1=V
2): +2.7 V to V [V] (3 V power supply (REGE = VSS))
BTI
DD
11. Power supply for LCD driver block (V
): +16.0 V (Typ.)
(V
(V
= 5 V, Quintuple voltage booster is used.)
= 3.3 V, Quintuple voltage booster is used.)
LCD
DD
DD
+16.5 V
+4.5 V to +16.5 V (range with external power supply)
12. Built-in contrast adjuster
LCD drive bias voltage (V
LCD
0): +4.65 V to +13.5 V (Typ.) (V
= 5 V, Quintuple voltage booster is used.)
= 3.3 V, Quintuple voltage booster is used.)
DD
DD
+4.65 V to +14.1 V
+4.65 V to +14.1 V
(V
(V
= 16.5 V with external power supply)
LCD
____
13. The initialization of this driver and the prevention of an unintended display are controllable by setting RES pad.
14. Wide range of operating temperature: 40 to +105C
15. CMOS process and chip with Au bumps
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 53 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
August 2017 - Rev. 2
1
Publication Order Number :
LC450210PCH/D
LC450210PCH
Specifications
Absolute Maximum Ratings at Ta = 25C, V
= 0 V
SS
Parameter
Symbol
Conditions
Ratings
0.3 to +6.0
Unit
V
VDD,
REGE = VDD
VDD,
V
max
DD
Supply voltage
0.3 to +4.2
REGE = VSS
V
V
max
VLCD (Note.1)
0.3 to +17.0
0.3 to +4.2
LCD
__
CE, CL, DI, RES, TSIN1 to TSIN4, OSCI
____
1
IN
CE, CL, DI, RES, TSIN1 to TSIN4, OSCI,
0.3 to +6.0
Supply more than 2.7 V to V
before V 1 is input.
IN
DD
Input voltage
V
V
V
2
3
4
VBTI1
0.3 to V +0.3
IN
IN
IN
DD
REGE
0.3 to +6.0
V
V
VLCD5 (Note.1)
VLCD
0.3 to V
0.3 to V
0.3 to V
+0.3
+0.3
+0.3
LCD
LCD
LCD
1
OUT
V
V
2
3
S1 to S200, COM1 to COM16
CP12N, CP34N, VLOGIC, TSOUT1 to TSOUT3, TSO,
≤ 3.9V (REGE=VSS)
OUT
OUT
Output voltage
V
0.3 to V +0.3
DD
V
DD
CP12N, CP34N, VLOGIC, TSOUT1 to TSOUT3, TSO,
> 3.9V (REGE=VDD)
0.3 to +4.2
V
DD
V
1
CP1P, CP2P, CP3P, CP4P
VLCD0, VLCD1, VLCD2, VLCD3, VLCD4 (Note.1)
VBTI2,
0.3 to V
0.3 to V
+0.3
+0.3
INOUT
LCD
V
V
2
3
INOUT
INOUT
LCD
Input / Output voltage
V
0.3 to V
1+0.3
BTI
V
1 ≤ 3.9 V (REGE = VSS)
BTI
VBTI2,
1 > 3.9 V (REGE = VDD)
-0.3 to +4.2
V
BTI
I
I
I
1
2
3
VLCD
8
OUT
OUT
OUT
Output current
S1 to S200
COM1 to COM16
0.3
1
mA
Operating temperature
Storage temperature
Topr
Tstg
40 to +105
°C
°C
55 to +125
(Note.1) Follow a condition of V
V
LCD
0 > V 1 > V 2 > V
LCD LCD LCD
3 > V 4 > V 5.
LCD LCD
LCD
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
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2
LC450210PCH
Allowable Operating Ranges at Ta = 40 to +105C, V
SS
= 0 V
Ratings
Typ.
Parameter
Symbol
Conditions
Unit
V
Min.
4.5
Max.
5.5
VDD,
REGE = VDD
VDD,
V
DD
Supply voltage
2.7
4.5
3.6
REGE = VSS
VLCD,
V
V
16.5
LCD
When VLCD is supplied from the outside.
VBTI1,
1
V
= 4.5 V to 5.5 V (REGE = VDD),
4.5
2.7
2.7
V
V
V
V
BTI
DD
DD
DD
Quadruple/Quintuple voltage booster is used.
VBTI1, VBTI2 (VBTI1 = VBTI2),
Input base voltage for
voltage booster
V
= 2.7 V to 3.6 V (REGE = VSS),
DD
(≤ 3.6)
Quadruple voltage booster is used.
VBTI1, VBTI2 (VBTI1 = VBTI2),
V
V
2
BTI
V
DD
(≤ 3.3)
V
= 2.7 V to 3.3 V (REGE = VSS),
DD
Quintuple voltage booster is used.
VLCD0,
4.5
V
LCD
(Note. 1)
0
V
V
V
LCD
Contrast adjuster is not used.
(Note. 1)
(Note. 1)
(Note.1)
V
V
V
V
1
2
3
4
LCD
LCD
LCD
LCD
Input voltage for LCD
drive bias voltage
generator
VLCD1, VLCD2, VLCD3, VLCD4,
LCD drive bias voltage generator is not used.
0
V
5
VLCD5
LCD
(Note.1)
____
CE, CL, DI, RES, OSCI
0.5V
5.5
DD
DD
V
= 4.5 V to 5.5 V (REGE = VDD)
____
CE, CL, DI, RES, OSCI
DD
V
V
V
V
1
Input High-level
voltage
IH
V
V
0.8V
0.8V
3.6
5.5
V
= 2.7 V to 3.6 V (REGE = VSS)
DD
REGE
CE, CL, DI, RES, TSIN1 to TSIN4, OSCI
2
IH
DD
0
____
0.2V
DD
V
= 4.5 V to 5.5 V (REGE = VDD)
____
CE, CL, DI, RES, TSIN1 to TSIN4, OSCI
DD
1
Input Low-level
voltage
IL
IL
0
0
0.2V
0.2V
DD
DD
V
= 2.7 V to 3.6 V (REGE = VSS)
DD
2
REGE
External clock
input frequency
OSCI,
f
100
30
300
50
600
70
kHz
%
CK
[Fig.1]
External clock operating mode
OSCI,
External clock duty
D
CK
[Fig.1]
External clock operating mode
Data setup time
Data hold time
CE wait time
tds
tdh
tcp
tcs
tch
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
160
160
160
160
160
ns
ns
ns
ns
ns
CE setup time
CE hold time
High-level
tH
tL
CL
CL
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
160
160
ns
ns
clock pulse width
Low-level
clock pulse width
Rise time
Fall time
tr
tf
CE, CL, DI
CE, CL, DI
[Fig.2], [Fig.3]
[Fig.2], [Fig.3]
160
160
ns
ns
____
RES
Reset pulse
twres
[Fig.5] to [Fig.8]
1.0
ms
minimum width
(Note.1) Follow a condition of V
LCD
V
LCD
0 > V 1 > V 2 > V
LCD LCD LCD
3 > V 4 > V 5.
LCD LCD
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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3
LC450210PCH
Electrical Characteristics in the Allowable Operating Ranges
Ratings
Typ.
Parameter
Symbol
PAD
Conditions
Unit
V
Min.
Max.
V
V
= 4.5 V to 5.5 V (REGE = VDD)
= 2.7 V to 3.6 V (REGE = VSS)
0.03V
DD
DD
CE, CL, DI,
____
RES, OSCI
Hysteresis
V
H
0.05V
DD
DD
V = 3.6 V
I
5.0
CE, CL, DI,
____
RES, OSCI
I
I
1
2
Input High-level
current
IH
V = 5.5 V,
I
Supply more than 2.7 V to V
A
A
5.0
5.0
before V is input.
I
DD
REGE
V = 5.5 V
I
IH
CE, CL, DI,
____
RES,
Input Low-level
current
I
1
V = 0 V
5.0
IL
I
TSIN1 to TSIN4,
REGE, OSCI
V
= 5.5 V, V 1 = 5.5 V, REGE = VDD,
BTI
DD
Quadruple voltage booster is used.
Contrast adjuster is used.
2,050
2,550
4,100
5,100
LCD drive bias voltage generator is used.
Common and segment outputs are open.
display on (normal display)
I
1
VBTI1
BTI
V
= 5.5 V, V 1 = 5.5 V, REGE = VDD,
BTI
DD
Quintuple voltage booster is used.
Contrast adjuster is used.
LCD drive bias voltage generator is used.
Common and segment outputs are open.
display on (normal display)
Input current for
voltage booster
V
= 3.6 V, V
1 = V 2 = 3.6 V,
BTI
DD
REGE = VSS,
BTI
A
Quadruple voltage booster is used.
Contrast adjuster is used.
2,000
4,000
LCD drive bias voltage generator is used.
Common and segment outputs are open.
display on (normal display)
I
2
VBTI2
BTI
V
= 3.3 V, V
1 = V 2 = 3.3 V,
BTI
DD
REGE = VSS,
BTI
Quintuple voltage booster is used.
Contrast adjuster is used.
2,500
5,000
LCD drive bias voltage generator is used.
Common and segment outputs are open.
display on (normal display)
ON-resistance of
segment driver
output
V
V
V
= 4.5 V (with external supply),
0 = 4.5 V (with external input),
LCD
LCD
LCD
R
R
S1 to S200
20
20
k
k
ONS
1 to V
5 = 1/5 bias (with external input)
LCD
ON-resistance of
common driver
output
V
V
V
= 4.5 V (with external supply),
0 = 4.5 V (with external input),
LCD
LCD
LCD
COM1 to COM16
ONC
1 to V
5 = 1/5 bias (with external input)
LCD
V
1 = 4.5 V to 5.5 V (REGE = VDD)
BTI
Voltage booster is used.
V
2
VBTI2
Contrast adjuster is not used.
LCD drive bias voltage generator is not used.
No-load.
3.09
3.2
3.3
BTI
Quadruple voltage booster is used.
Contrast adjuster is not used.
LCD drive bias voltage generator is not used.
No-load.
Output voltage
(V
(V
24)
0.4
(V
BTI
24)
V
BTI
V
V
24
BTI
+0.4
V
VLCD
LCD
Quintuple voltage booster is used.
Contrast adjuster is not used.
LCD drive bias voltage generator is not used.
No-load.
25)
0.4
BTI
25
16.5
390
BTI
Oscillator
frequency
Internal clock
generator
fosc
Internal oscillator operating mode
210
300
kHz
Continued on next page.
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LC450210PCH
Continued from preceding page.
Ratings
Typ.
Parameter
Symbol
PAD
Conditions
Unit
Min.
Max.
<Power-saving mode>
= 3.6 V (REGE = VSS),
V
DD
communication inactive,
Input level is V or V
15
.
SS DD
I
1
DD
V
DD
< Power-saving mode >
= 5.5 V (REGE = VDD),
V
DD
communication inactive,
50
120
500
Input level is V
or V .
DD
SS
<Normal mode>
V
= 3.6 V (REGE = VSS),
DD
display on (normal display),
internal oscillator operating mode,
communication inactive,
100
150
Power current
A
Input level is V
SS
or V .
DD
I
2
DD
V
DD
< Normal mode >
= 5.5 V (REGE = VDD),
V
DD
display on (normal display),
internal oscillator operating mode,
communication inactive,
600
Input level is V
SS
or V .
DD
< Normal mode >
= 16.5 V (with external supply),
V
LCD
display on (normal display),
I
V
Voltage booster is not used.
500
1,000
LCD
LCD
Contrast adjuster is used.
LCD drive bias voltage generator is used.
Common and segment outputs are open.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC450210PCH
(1) Clock timing of OSCI pad in the external clock operating mode
1
t
H
t
L
CK
CK
f
=
=
[kHz]
CK
CK
t
t
H+t
L
L
CK
CK
CK
CK
V
1
IH
50%
IL
OSCI
t
H
V
1
CK
H+t
D
x 100[%]
[Fig.1]
(2) When CL is stopped at the low level
V
1
IH
CE
V
1
IL
tL
tH
V
1
IH
50%
CL
DI
V
1
IL
tf
tr
tcp tcs
tch
V
V
1
IH
1
IL
tds
tdh
[Fig.2]
(3) When CL is stopped at the high level
V
1
IH
CE
V
1
IL
tL
tH
V
1
IH
50%
IL
CL
DI
V
1
tf
tr
tcp tcs
[Fig.3]
tch
V
1
IH
V
1
IL
tds
tdh
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LC450210PCH
Block Diagram
REGE
VBTI1
VBTI2
VOLTAGE
BOOSTER
CP1P
CP12N
CP2P
COMMON DRIVER
SEGMENT DRIVER
CP3P
CP34N
CP4P
LACTH
VLCD
CONTRAST
ADJUSTER
DISPLAY DATA
RAM
ADDRESS
COUNTER
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
(16 200 bits)
LCD DRIVE
BIAS VOLTAGE
GENERATOR
INSTRUCTION REGISTER & DECODER
SHIFT REGISTER
____
RES
VDD
TIMING
GENERATOR
REGULATOR
CLOCK
GENERATOR
CCB INTERFACE
VSS
TSIN1 to 4
TSOUT1 to 3
TSO
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LC450210PCH
Pad Functions
Handling
when
Pad Name
Pad No.
Function
Active
I/O
-
unused
This is a power supply for logic block.
REGE = VDD: Supply a voltage from 4.5 V to 5.5 V to VDD.
REGE = VSS: Supply a voltage from 2.7 V to 3.6 V to VDD.
In addition, make sure to connect a capacitor between VDD and VSS.
VDD
231 to 234
-
-
226 to 229,
235 to 243
VSS
Make sure to connect VSS to ground.
-
-
-
-
This is a monitor of a regulator output for logic power supply.
Do not use VLOGIC with an external circuit.
This is an input for controlling the regulator of logic power supply and the regulator of
voltage booster.
VLOGIC
216
O
OPEN
Depending on specification of power supply, make sure to connect REGE to VDD or
VSS.
REGE = VDD: 5 V Power supply is used.
The regulator of logic power supply runs.
The regulator of voltage booster runs.
REGE
230
-
I
-
REGE = VSS: 3 V Power supply is used.
The regulator of logic power supply stops.
The regulator of voltage booster stops.
S1 to 200
2 to 201
These are segment driver outputs.
-
-
O
O
OPEN
OPEN
COM1 to 8,
COM9 to16
313 to 320,
210 to 203
These are common driver outputs.
This is an input for a base voltage for voltage booster.
< When voltage booster is used >
Make sure to connect a capacitor between VBTI1 and VSS.
REGE = VDD: Input the voltage from 4.5 V to V [V] to VBTI1.
DD
REGE = VSS: Connect VBTI1 to VBTI2, and Input the voltage from 2.7 V to V [V] to
DD
VBTI1
244 to 248
-
I
OPEN
VBTI1.
(When quadruple booster is used : V
When quintuple booster is used : V
1 ≤ 3.6 V,
BTI
1 ≤ 3.3 V)
BTI
< When voltage booster is not used >
Make sure to open VBTI1.
This is an input-output for a base voltage for voltage booster.
< When voltage booster is used >
Make sure to connect a capacitor between VBTI2 and VSS.
REGE = VDD: VBTI2 outputs a base voltage for voltage booster.
REGE = VSS: Connect VBTI1 to VBTI2, and Input the voltage from 2.7 V to V [V] to
DD
VBTI2
249 to 253
-
I/O
OPEN
VBTI1.
(When quadruple booster is used : V
When quintuple booster is used : V
1 ≤ 3.6 V,
BTI
1 ≤ 3.3 V)
BTI
< When voltage booster is not used >
Make sure to open VBTI2.
These are Input-outputs for voltage booster.
< When quadruple voltage booster is used >
Make sure to connect a capacitor between CP1P(+) and CP12N(-).
Make sure to connect a capacitor between CP2P(+) and CP12N(-).
Make sure to connect a capacitor between CP3P(+) and CP34N(-).
Make sure to connect CP4P and VLCD.
CP1P,
CP12N,
CP2P,
CP3P,
CP34N,
CP4P
254 to 257,
258 to 264,
265 to 268,
269 to 272,
273 to 279,
280 to 283
-
I/O
OPEN
< When quintuple voltage booster is used >
Make sure to connect a capacitor between CP1P(+) and CP12N(-).
Make sure to connect a capacitor between CP2P(+) and CP12N(-).
Make sure to connect a capacitor between CP3P(+) and CP34N(-).
Make sure to connect a capacitor between CP4P(+) and CP34N(-).
< When voltage booster is not used >
Make sure to open CP1P, CP12N, CP2P, CP3P, CP34N and CP4P.
Continued on next page.
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LC450210PCH
Continued from preceding page.
Handling
when
Pad Name
Pad No.
Function
Active
I/O
I/O
unused
This is a power supply for LCD driver block.
Make sure to connect a capacitor between VLCD and VSS.
< When voltage booster is used >
(i) When quadruple booster is used: VLCD outputs the booster voltage (V
2 4).
BTI
VLCD
284 to 289
-
-
(ii) When quintuple booster is used: VLCD outputs the booster voltage (V
2 5).
BTI
< When voltage booster is not used >
Supply a voltage from 4.5 V to 16.5 V to VLCD.
When contrast adjuster is used, follow a condition of V
LCD
≥ V 0 + 2.4 V.
LCD
This is an input-output for the LCD drive bias voltage (High level).
Make sure to connect a capacitor between VLCD0 and VLCD5.
< When contrast adjuster is used >
VLCD0 outputs the LCD drive bias voltage (High level) set by “Set of display contrast”
instruction (CT0 to CT5).
VLCD0
290 to 294
-
I/O
OPEN
Follow a condition of V
0 ≤ V - 2.4 V.
LCD
LCD
< When contrast adjuster is not used >
Input the LCD drive bias voltage (High level) to V
0 from the outside, and follow a
LCD
condition of V
1 < V
0 ≤ V .
LCD
LCD
LCD
This is an input-output for the LCD drive bias voltage (3/4 level, 4/5 level).
Make sure to connect a capacitor between VLCD1 and VLCD5.
< When LCD drive bias voltage generator is used >
(i) When 1/4 bias is used: VLCD1 outputs the LCD drive bias voltage (3/4 V
0).
LCD
(ii) When 1/5 bias is used: VLCD1 outputs the LCD drive bias voltage (4/5 V
0).
LCD
VLCD1
306 to 308
-
I/O
OPEN
OPEN
OPEN
< When LCD drive bias voltage generator is not used >
(i) When 1/4 bias is used: Input the LCD drive bias voltage (3/4 V
0) to VLCD1
2 < V
LCD
from the outside, and follow a condition of V
1
1
LCD
LCD
< V
0.
LCD
(ii) When 1/5 bias is used: Input the LCD drive bias voltage (4/5 V
0) to VLCD1
2 < V
LCD
from the outside, and follow a condition of V
LCD
LCD
< V
0.
LCD
This is an input-output for the LCD drive bias voltage (2/4 level, 3/5 level).
Make sure to connect a capacitor between VLCD2 and VLCD5.
< When LCD drive bias voltage generator is used >
(i) When 1/4 bias is used: VLCD2 outputs the LCD drive bias voltage (2/4 V
0).
LCD
(ii) When 1/5 bias is used: VLCD2 outputs the LCD drive bias voltage (3/5 V
0).
LCD
VLCD2
300 to 302
-
I/O
< When LCD drive bias voltage generator is not used >
(i) When 1/4 bias is used: Input the LCD drive bias voltage (2/4 V
0) to VLCD2
4 < V
LCD
from the outside, and follow a condition of V
2
2
LCD
LCD
< V
1.
LCD
(ii) When 1/5 bias is used: Input the LCD drive bias voltage (3/5 V
0) to VLCD2
3 < V
LCD
from the outside, and follow a condition of V
LCD
LCD
< V
1.
LCD
This is an input-output for the LCD drive bias voltage (2/5 level).
< When LCD drive bias voltage generator is used >
(i) When 1/4 bias is used: Make sure to open VLCD3.
(ii) When 1/5 bias is used: VLCD3 outputs the LCD drive bias voltage (2/5 V
0).
LCD
Make sure to connect a capacitor between VLCD3 and
VLCD5.
VLCD3
303 to 305
-
I/O
< When LCD drive bias voltage generator is not used >
(i) When 1/4 bias is used: Make sure to open VLCD3.
(ii) When 1/5 bias is used: Make sure to connect a capacitor between VLCD3 and
VLCD5. Input the LCD drive bias voltage (2/5 V
0) to
4 <
LCD
VLCD3 from the outside, and follow a condition of V
LCD
V
3 < V 2.
LCD LCD
Continued on next page.
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9
LC450210PCH
Continued from preceding page.
Handling
when
Pad Name
Pad No.
Function
Active
I/O
unused
This is an input-output for the LCD drive bias voltage (1/4 level, 1/5 level).
Make sure to connect a capacitor between VLCD4 and VLCD5.
< When LCD drive bias voltage generator is used >
(i) When 1/4 bias is used: VLCD4 outputs the LCD drive bias voltage (1/4 V
0).
LCD
(ii) When 1/5 bias is used: VLCD4 outputs the LCD drive bias voltage (1/5 V
0).
LCD
VLCD4
309 to 311
-
I/O
OPEN
< When LCD drive bias voltage generator is not used >
(i) When 1/4 bias is used: Input the LCD drive bias voltage (1/4 V
0) to VLCD4
5 < V
LCD
from the outside, and follow a condition of V
LCD
4
LCD
< V
2.
LCD
(ii) When 1/5 bias is used: Input the LCD drive bias voltage (1/5 V
0) to VLCD4
5 < V
LCD
from the outside, and follow a condition of V
4
LCD
LCD
< V
3.
LCD
This is an input-output for the LCD drive bias voltage (Low level).
VLCD5
OSCI
295 to 299
221
-
I
I
VSS
VSS
Make sure to connect VLCD5 to VSS even if the LCD drive bias generator is not used.
This is an input for the external clock, when external clock operating mode is selected.
By “Set of display method” instruction,
-
OC = 0 (internal oscillator operating mode): Make sure to connect OSCI to VSS.
OC = 1 (external clock operating mode): OSCI is used to input the external clock.
These are Inputs for transferring serial data. These pads are connected to a controller.
CE
CL
DI
218
220
219
H
I
I
I
CE: Chip enables.
CL: Synchronous clock.
DI: Transfer data.
VSS
VSS
-
This is an input for reset of this LSI.
____
RES = VSS: The state of this LSI is reset.
____
RES
217
L
I
Refer to about the “System Reset”.
____
RES = VDD: Normal state.
TSIN1 to
TSIN4
These are inputs for a test.
222 to 225
212 to 214
215
-
-
-
I
VSS
Make sure to connect these pads to VSS.
These are outputs for a test.
Make sure to open these pads.
These are output for a test.
Make sure to open this pad.
These are dummy pads.
TSOUT1 to
TSOUT3
O
O
OPEN
OPEN
TSO
DUMMY
1, 202, 211, 312 These pads are not available. Don’t connect between dummy pads.
Moreover, don’t use them with an external circuit.
-
-
OPEN
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10
LC450210PCH
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11
LC450210PCH
Transfer Format of Serial Data
This LSI has several internal registers. These internal registers are written by CCB interface. Structure of transfer bits
consists of CCB address and instruction data. First 8 bits are CCB address. The subsequent bits are instruction data. The
bit number of instruction data is different depending on an instruction, and these bits are from 16 bits to 272 bits.
The serial data is taken by the positive edge of the CL signal, which is latched by the negative edge of the CE signal.
When the number of data in CE = “High level” period is different from the defined number, LSI does not execute the
instruction and holds the old state. For more information about the number of instruction data, refer to “Instruction
Table”.
(1) When CL is stopped at the low level
CE
CL
0
1
0
0
1
1
0
1
D0
D1 D2 D3 D4
D270 D271
DI
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits (fixed)
Instruction data
272 bits (Max.)
(2) When CL is stopped at the high level
CE
CL
0
1
0
0
1
1
0
1
D0 D1 D2 D3 D4
D270 D271
DI
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits (fixed)
Instruction data
272 bits (Max.)
• B0 to B3, A0 to A3 ········· CCB address is “B2H”
• D0 to D271 ········· Instruction data (from 16 bits to 272 bits)
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LC450210PCH
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13
LC450210PCH
Explanation of Instruction Data
1. “Set of display method” instruction
The display method is set by “Set of display method” instruction.
____
After having reset a system by RES = “Low level”, make sure to execute “Set of display method” first.
Instruction data (32 bits)
D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
OC
0
1
0
DBC CTC0 CTC1
0
DT0 DT1 DT2 DT3 DR WVC
(LSB) (MSB)
1
0
CDIR SDIR
1
0
DBF0 DBF1 DBF2
(LSB) (MSB)
0
FC0 FC1 FC2 FC3
(LSB) (MSB)
0
0
0
1
(1-1) OC ··· This is control data to set a fundamental clock operating mode.
Internal oscillator operating mode and external clock operating mode are set by this control data.
When the internal oscillator operating mode is set, clock generator begins to run after power-saving mode is
canceled (BU = “0”).
OC
0
Fundamental clock operating mode
Internal oscillator operating mode
External clock operating mode
The state of OSCI
Make sure to connect OSCI to VSS.
1
Input the clock f from 100 to 600 [kHz].
CK
(1-2) DBC ··· This is control data to set a state of voltage booster.
Run or Stop of voltage booster is set by this control data.
About the combination of DBC, CTC0 and CTC1, refer to the following table.
(1-3) CTC0, CTC1 ··· These are control data to set a state of contrast adjuster and LCD drive bias voltage generator.
Run or Stop of contrast adjuster and LCD drive bias voltage generator is set by these control data.
About the combination of DBC, CTC0 and CTC1, refer to the following table.
DBC CTC0 CTC1 Voltage booster
Contrast adjuster LCD drive bias voltage generator
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Stop
Stop
Stop
Stop
Run
Run
Run
Run
Stop
Stop
Run
Run
Stop
Stop
Run
Run
Stop
Run
Stop
Run
Stop
Run
Stop
Run
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14
LC450210PCH
About the state of Voltage booster, VBTI1, VBTI2 and VLCD, refer to the following table.
The state of
The state of VBTI1
The state of VBTI2
The state of VLCD
voltage booster
Supply a voltage from
4.5 V to 16.5 V to VLCD
from the outside.
Unused
Make sure to open VBTI1.
< REGE = VDD >
Make sure to open VBTI2.
< REGE = VDD >
Input the voltage from 4.5 V to V [V] to
DD
VBTI1.
VBTI2 outputs a base voltage for voltage
booster.
Quadruple voltage
booster is used.
VLCD outputs the
< REGE = VSS >
< REGE = VSS >
(V 2 4) voltage
BTI
Connect VBTI1 to VBTI2.
Connect VBTI1 to VBTI2, and Input the
voltage from 2.7 V to V [V] (≤3.6 V) to
DD
VBTI1.
< REGE = VDD >
< REGE = VDD >
Input the voltage from 4.5 V to V [V] to
DD
VBTI1.
VBTI2 outputs a base voltage for voltage
booster.
Quintuple voltage
booster is used.
VLCD outputs the
(V 2 5) voltage
< REGE = VSS >
< REGE = VSS >
BTI
Connect VBTI1 to VBTI2.
Connect VBTI1 to VBTI2, and Input the
voltage from 2.7 V to V [V] (≤3.3 V) to
DD
VBTI1.
(Note.1) During (1) or (2) time, voltage booster stops forcibly and is the discharge state. In the discharge state, the
electric potential of VLCD is same as VBTI1.
____
(1) The period of RES = “Low level” (Regardless of the setting of voltage booster)
(2) DBC = “1” is set by “Set of display method” instruction, and power-saving mode (BU = “1”) is set by
“Control of display ON / OFF” instruction.
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LC450210PCH
(Note.2) The peripheral circuit of VBTI1, VBTI2, CP1P, CP12N, CP2P, CP3P, CP34N, CP4P and VLCD is as follows.
Only changing the connection of CP4P, a multiple of the voltage booster is selectable.
< 5 V Power supply (REGE=VDD),
< 3 V Power supply (REGE=VSS),
Quadruple voltage booster is used (DBC=“1”) >
Quadruple voltage booster is used (DBC=“1”) >
+4.5V to V [V]
DD
+2.7V to V [V]
DD
VBTI1
VBTI2
VBTI1
VBTI2
(≤5.5V)
(≤3.6V)
Cbt
Cbt
Cbt
D
D
CP1P
CP1P
+
+
C1
C2
C1
C2
CP12N
CP12N
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
CP2P
CP3P
CP2P
CP3P
+
+
+
+
C3
C3
CP34N
CP4P
CP34N
CP4P
VLCD
VLCD
+
+
Cvl
Cvl
< 5 V Power supply (REGE=VDD),
< 3 V Power supply (REGE=VSS),
Quintuple voltage boost is used (DBC=“1”) >
Quintuple voltage boost is used (DBC=“1”) >
+4.5V to V [V]
+2.7V to V [V]
DD
VBTI1
VBTI2
DD
VBTI1
VBTI2
(≤5.5V)
(≤3.3V)
Cbt
Cbt
D
Cbt
D
CP1P
+
CP1P
+
C1
C2
C1
C2
CP12N
CP12N
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ C4 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ C4 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
CP2P
CP3P
+
+
CP2P
CP3P
+
+
C3
C4
C3
C4
CP34N
CP4P
CP34N
CP4P
+
+
VLCD
VLCD
+
+
Cvl
Cvl
< 5 V Power supply (REGE=VDD),
< 3 V Power supply (REGE=VSS),
Voltage booster is not used (DBC=“0”) >
Voltage booster is not used (DBC=“0”) >
+4.5V to +5.5V
+2.7V to +3.6V
VDD
VDD
Cbt
Cbt
VBTI1
VBTI2
VBTI1
VBTI2
CP1P
CP1P
CP12N
CP12N
open
open
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
CP2P
CP3P
CP2P
CP3P
CP34N
CP4P
CP34N
CP4P
+4.5V to +16.5V
+4.5V to +16.5V
VLCD
VLCD
+
+
Cvl
Cvl
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16
LC450210PCH
About the state of contrast adjuster, LCD drive bias voltage generator and the state from VLCD1 to VLCD4, refer to the
following table.
The state of
The state of LCD drive
bias voltage generator
The state of VLCD0
The state from VLCD1 to VLCD4
contrast adjuster
Input LCD drive bias voltage (Middle level) to pads
from VLCD1 to VLCD4 from the outside.
Input LCD drive bias voltage (High level)
to VLCD0 from the outside.
Unused
Use
Unused
(When 1/4 bias is used, make sure to open VLCD3.)
VLCD0 outputs the LCD drive bias
voltage (High level) set by “Set of display
contrast” instruction (CT0 to CT5). Make
sure to connect a capacitor between
VLCD0 and VLCD5.
Input LCD drive bias voltage (Middle level) to pads
from VLCD1 to VLCD4 from the outside.
Unused
(When 1/4 bias is used, make sure to open VLCD3.)
Pads from VLCD1 to VLCD4 outputs LCD drive bias
voltage (Middle level).
Input LCD drive bias voltage (High level)
to VLCD0 from the outside.
Unused
Use
Use
Make sure to connect a capacitor between pads
from VLCD1 to VLCD4 and VLCD5.
(When 1/4 bias is used, make sure to open VLCD3.)
Pads from VLCD1 to VLCD4 outputs LCD drive bias
voltage (Middle level).
VLCD0 outputs the LCD drive bias
voltage (High level) set by “Set of display
contrast” instruction (CT0 to CT5). Make
sure to connect a capacitor between
VLCD0 and VLCD5.
Use
Make sure to connect a capacitor between pads
from VLCD1 to VLCD4 and VLCD5.
(When 1/4 bias is used, make sure to open VLCD3.)
(Note.1) During (1) or (2) or (3) time, contrast adjuster and LCD drive bias voltage generator stop forcibly, and are
the discharge state. In the discharge state, the electric potential of VLCD0, VLCD1, VLCD2, VLCD3 and
VLCD4 are same as VLCD5.
____
(1) The period of RES = “Low level” (Regardless of the setting of contrast adjuster and LCD drive bias
voltage generator)
(2) CTC0 = “1” is set by “Set of display method” instruction, and power-saving mode (BU = “1”) is set by
“Control of display ON / OFF” instruction.
(3) CTC1 = “1” is set by “Set of display method” instruction, and power-saving mode (BU = “1”) is set by
“Control of display ON / OFF” instruction.
(Note.2) When 1/4 bias is set (DR = “0”), set a peripheral circuit from VLCD0 to VLCD5 as follows.
< Contrast adjuster and LCD drive bias voltage
generator are used. (CTC0,CTC1=“1,1”) >
< Contrast adjuster is not used, and LCD drive bias
voltage generator is used. (CTC0,CTC1=“0,1”) >
VLCD0
+4.5V to V
[V]
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
LCD
Cvm
Cvm
Cvm
Cvm
VLCD1
Cvm
VLCD2
Cvm
open
open
Cvm
VLCD3
VLCD4
VLCD5
Cvm
0.1[F] ≤ Cvm ≤ 0.47[F]
0 ≤ V -2.4[V]
0.1[F] ≤ Cvm ≤ 0.47[F]
V
LCD
LCD
< Contrast adjuster is used, and LCD drive bias voltage
generator is not used. (CTC0,CTC1=“1,0”) >
< Contrast adjuster and LCD drive bias voltage
generator are not used. (CTC0,CTC1=“0,0”) >
VLCD0
Cvm
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
+4.5V to V
[V]
LCD
Cvm
Cvm
Cvm
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
3/4V
2/4V
0[V]
0[V]
3/4V
2/4V
0[V]
LCD
LCD
LCD
Cvm
Cvm
0[V]
0[V]
LCD
open
Cvm
open
Cvm
1/4V
0[V]
1/4V
LCD
LCD
0.1[F] ≤ Cvm ≤ 0.47[F]
0 ≤ V -2.4[V]
0.1[F] ≤ Cvm ≤ 0.47[F]
V
LCD
LCD
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17
LC450210PCH
(Note.3) When 1/5 bias is set (DR=“1”), set a peripheral circuit from VLCD0 to VLCD5 as follows.
< Contrast adjuster is not used, and LCD drive bias
voltage generator is used. (CTC0,CTC1=“0,1”) >
< Contrast adjuster and LCD drive bias voltage
generator are used. (CTC0,CTC1=“1,1”) >
+4.5V to V
[V]
VLCD0
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
LCD
Cvm
Cvm
Cvm
Cvm
Cvm
Cvm
VLCD1
Cvm
VLCD2
Cvm
VLCD3
Cvm
VLCD4
Cvm
VLCD5
0.1[F] ≤ Cvm ≤ 0.47[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
V
0 ≤ V
-2.4[V]
LCD
LCD
< Contrast adjuster is used, and LCD drive bias voltage < Contrast adjuster and LCD drive bias voltage
generator is not used. (CTC0,CTC1=“1,0”) >
generator are not used. (CTC0,CTC1=“0,0”) >
VLCD0
Cvm
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
+4.5V to V
[V]
LCD
Cvm
Cvm
Cvm
Cvm
Cvm
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
4/5V
3/5V
2/5V
1/5V
0[V]
0[V]
0[V]
0[V]
4/5V
3/5V
2/5V
1/5V
0[V]
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Cvm
Cvm
Cvm
Cvm
0[V]
0[V]
0[V]
0.1[F] ≤ Cvm ≤ 0.47[F]
0 ≤ V -2.4[V]
0.1[F] ≤ Cvm ≤ 0.47[F]
V
LCD
LCD
(1-4) DT0 to DT3 ··· These are control data to set duty from 1/8 to 1/16.
Duty from 1/8 to 1/16 is set by these control data.
The state from COM1 to COM16
Pads which output scan pulse
Pads which output pulse of display off
DT0 DT1 DT2 DT3
Duty
Normal scan
CDIR = “0”
Reversed scan
CDIR = “1”
Normal scan
CDIR = “0”
Reversed scan
CDIR = “1”
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
X
0
0
0
0
0
0
0
0
1
1/8 duty
1/9 duty
COM1 to COM8
COM1 to COM9
COM1 to COM10
COM1 to COM11
COM1 to COM12
COM1 to COM13
COM1 to COM14
COM1 to COM15
COM1 to COM16
COM16 to COM9
COM16 to COM8
COM16 to COM7
COM16 to COM6
COM16 to COM5
COM16 to COM4
COM16 to COM3
COM16 to COM2
COM16 to COM1
COM9 to COM16
COM10 to COM16
COM11 to COM16
COM12 to COM16
COM13 to COM16
COM14 to COM16
COM15, COM16
COM16
COM8 to COM1
COM7 to COM1
COM6 to COM1
COM5 to COM1
COM4 to COM1
COM3 to COM1
COM2, COM1
COM1
1/10 duty
1/11 duty
1/12 duty
1/13 duty
1/14 duty
1/15 duty
1/16 duty
-
-
X: don’t care
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LC450210PCH
(1-5) DR ··· This is control data to set 1/4 bias or 1/5 bias.
1/4 bias or 1/5 bias is set by this control data.
DR
Bias
VLCD1 voltage
VLCD2 voltage
VLCD3 voltage
VLCD4 voltage
0
1
1/4 bias
1/5 bias
3/4 V
4/5 V
0
0
2/4 V
3/5 V
0
0
Make sure to open VLCD3
1/4 V
1/5 V
0
0
LCD
LCD
LCD
2/5 V
0
LCD
LCD
LCD
LCD
(1-6) WVC ··· This is control data to set inversion drive of LCD drive waveform.
Line inversion or frame inversion is set by this control data.
WVC
LCD drive waveform
Line inversion
0
1
Frame inversion
(1-7) CDIR ··· This is control data to set scan direction of common outputs.
Scan direction of common outputs is set by this control data.
CDIR
Scan direction of common outputs
0
1
Normal scan
(COM1 COM2 COM3 ······ COM15 COM16)
Reversed scan (COM16 COM15 COM14 ······ COM2 COM1)
(1-8) SDIR ··· This is control data to set a correspondence of a segment output and a column address of RAM.
A correspondence of a segment output and a column address of RAM are set by this control data.
Only just changing the setting of SDIR data does not change the display of LCD. When display data is
written to RAM, column address of RAM is converted. Then display data is saved to there.
SDIR
0
Correspondence of a segment output and a column address of RAM
Normal direction
(Column address “CRA0 to CRA7=00H, 01H, 02H, C5H, C6H, C7H” of RAM corresponds to segment output “S1, S2, S3, , S198,
S199, S200”.)
Reversed direction
1
(Column address “CRA0 to CRA7=00H, 01H, 02H, C5H, C6H, C7H” of RAM corresponds to segment output “S200, S199, S198, ,
S3, S2, S1”.)
(1-9) DBF0 to DBF2 ··· These are control data to set clock frequency of voltage booster.
A clock frequency of voltage booster is set by these control data.
DBF0 DBF1 DBF2
Clock frequency of voltage booster (fcp)
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
fosc/12 or f /12
CK
fosc/14 or f /14
CK
fosc/18 or f /18
CK
fosc/22 or f /22
CK
fosc/26 or f /26
CK
fosc/28 or f /28
CK
fosc/30 or f /30
CK
fosc/34 or f /34
CK
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LC450210PCH
(1-10) FC0 to FC3 ··· These are control data to set frame frequency of common and segment output waveforms.
A frame frequency of common and segment output waveforms are set by these control data.
Frame frequency fo[Hz]
FC0 FC1 FC2 FC3
1/8 duty
1/9 duty
1/10 duty
1/11 duty
1/12 duty
fosc(f )/4352
CK
< 68.9[Hz] >
fosc(f )/4320
CK
< 69.4[Hz] >
fosc(f )/4320
CK
< 69.4[Hz] >
fosc(f )/4400
CK
< 68.2[Hz] >
fosc(f )/4320
CK
< 69.4[Hz] >
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
fosc(f )/3712
CK
< 80.8[Hz] >
fosc(f )/3744
CK
< 80.1[Hz] >
fosc(f )/3760
CK
< 79.8[Hz] >
fosc(f )/3784
CK
< 79.3[Hz] >
fosc(f )/3744
CK
< 80.1[Hz] >
fosc(f )/2944
CK
< 101.9[Hz] >
fosc(f )/2952
CK
< 101.6[Hz] >
fosc(f )/2960
CK
< 101.4[Hz] >
fosc(f )/2992
CK
< 100.3[Hz] >
fosc(f )/2976
CK
< 100.8[Hz] >
fosc(f )/2368
CK
< 126.7[Hz] >
fosc(f )/2376
CK
< 126.3[Hz] >
fosc(f )/2400
CK
< 125.0[Hz] >
fosc(f )/2376
CK
< 126.3[Hz] >
fosc(f )/2400
CK
< 125.0[Hz] >
fosc(f )/1984
CK
< 151.2[Hz] >
fosc(f )/1944
CK
< 154.3[Hz] >
fosc(f )/2000
CK
< 150.0[Hz] >
fosc(f )/1936
CK
< 155.0[Hz] >
fosc(f )/1968
CK
< 152.4[Hz] >
fosc(f )/1696
CK
< 176.9[Hz] >
fosc(f )/1692
CK
< 177.3[Hz] >
fosc(f )/1720
CK
< 174.4[Hz] >
fosc(f )/1672
CK
< 179.4[Hz] >
fosc(f )/1728
CK
< 173.6[Hz] >
fosc(f )/1472
CK
< 203.8[Hz] >
fosc(f )/1476
CK
< 203.3[Hz] >
fosc(f )/1480
CK
< 202.7[Hz] >
fosc(f )/1496
CK
< 200.5[Hz] >
fosc(f )/1488
CK
< 201.6[Hz] >
fosc(f )/1312
CK
< 228.7[Hz] >
fosc(f )/1332
CK
< 225.2[Hz] >
fosc(f )/1320
CK
< 227.3[Hz] >
fosc(f )/1320
CK
< 227.3[Hz] >
fosc(f )/1320
CK
< 227.3[Hz] >
fosc(f )/1184
CK
< 253.4[Hz] >
fosc(f )/1188
CK
< 252.5[Hz] >
fosc(f )/1200
CK
< 250.0[Hz] >
fosc(f )/1188
CK
< 252.5[Hz] >
fosc(f )/1200
CK
< 250.0[Hz] >
fosc(f )/1088
CK
< 275.7[Hz] >
fosc(f )/1080
CK
< 277.8[Hz] >
fosc(f )/1080
CK
< 277.8[Hz] >
fosc(f )/1100
CK
< 272.7[Hz] >
fosc(f )/1104
CK
< 271.7[Hz] >
fosc(f )/1056
CK
< 284.1[Hz] >
fosc(f )/1044
CK
< 287.4[Hz] >
fosc(f )/1040
CK
< 288.5[Hz] >
fosc(f )/1056
CK
< 284.1[Hz] >
fosc(f )/1056
CK
< 284.1[Hz] >
fosc(f )/992
CK
< 302.4[Hz] >
fosc(f )/1008
CK
< 297.6[Hz] >
fosc(f )/1000
CK
< 300.0[Hz] >
fosc(f )/990
CK
< 303.0[Hz] >
fosc(f )/984
CK
< 304.9[Hz] >
fosc(f )/960
CK
< 312.5[Hz] >
fosc(f )/972
CK
< 308.6[Hz] >
fosc(f )/960
CK
< 312.5[Hz] >
fosc(f )/946
CK
< 317.1[Hz] >
fosc(f )/960
CK
< 312.5[Hz] >
fosc(f )/928
CK
< 323.3[Hz] >
fosc(f )/936
CK
< 320.5[Hz] >
fosc(f )/920
CK
< 326.1[Hz] >
fosc(f )/924
CK
< 324.7[Hz] >
fosc(f )/936
CK
< 320.5[Hz] >
fosc(f )/896
CK
< 334.8[Hz] >
fosc(f )/900
CK
< 333.3[Hz] >
fosc(f )/900
CK
< 333.3[Hz] >
fosc(f )/902
CK
< 332.6[Hz] >
fosc(f )/888
CK
< 337.8[Hz] >
fosc(f )/864
CK
< 347.2[Hz] >
fosc(f )/864
CK
< 347.2[Hz] >
fosc(f )/860
CK
< 348.8[Hz] >
fosc(f )/858
CK
< 349.7[Hz] >
fosc(f )/864
CK
< 347.2[Hz] >
Frame frequency fo[Hz]
FC0 FC1 FC2 FC3
1/13 duty
1/14 duty
1/15 duty
1/16 duty
fosc(f )/4264
CK
< 70.4[Hz] >
fosc(f )/4256
CK
< 70.5[Hz] >
fosc(f )/4320
CK
< 69.4[Hz] >
fosc(f )/4352
CK
< 68.9[Hz] >
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
fosc(f )/3744
CK
< 80.1[Hz] >
fosc(f )/3808
CK
< 78.8[Hz] >
fosc(f )/3720
CK
< 80.7[Hz] >
fosc(f )/3712
CK
< 80.8[Hz] >
fosc(f )/2964
CK
< 101.2[Hz] >
fosc(f )/2968
CK
< 101.1[Hz] >
fosc(f )/3000
CK
< 100.0[Hz] >
fosc(f )/2944
CK
< 101.9[Hz] >
fosc(f )/2392
CK
< 125.4[Hz] >
fosc(f )/2408
CK
< 124.6[Hz] >
fosc(f )/2400
CK
< 125.0[Hz] >
fosc(f )/2368
CK
< 126.7[Hz] >
fosc(f )/1976
CK
< 151.8[Hz] >
fosc(f )/1960
CK
< 153.1[Hz] >
fosc(f )/1980
CK
< 151.5[Hz] >
fosc(f )/1984
CK
< 151.2[Hz] >
fosc(f )/1716
CK
< 174.8[Hz] >
fosc(f )/1708
CK
< 175.6[Hz] >
fosc(f )/1710
CK
< 175.4[Hz] >
fosc(f )/1696
CK
< 176.9[Hz] >
fosc(f )/1482
CK
< 202.4[Hz] >
fosc(f )/1456
CK
< 206.0[Hz] >
fosc(f )/1500
CK
< 200.0[Hz] >
fosc(f )/1472
CK
< 203.8[Hz] >
fosc(f )/1326
CK
< 226.2[Hz] >
fosc(f )/1316
CK
< 228.0[Hz] >
fosc(f )/1350
CK
< 222.2[Hz] >
fosc(f )/1312
CK
< 228.7[Hz] >
fosc(f )/1196
CK
< 250.8[Hz] >
fosc(f )/1204
CK
< 249.2[Hz] >
fosc(f )/1200
CK
< 250.0[Hz] >
fosc(f )/1184
CK
< 253.4[Hz] >
fosc(f )/1118
CK
< 268.3[Hz] >
fosc(f )/1092
CK
< 274.7[Hz] >
fosc(f )/1080
CK
< 277.8[Hz] >
fosc(f )/1088
CK
< 275.7[Hz] >
fosc(f )/1040
CK
< 288.5[Hz] >
fosc(f )/1036
CK
< 289.6[Hz] >
fosc(f )/1050
CK
< 285.7[Hz] >
fosc(f )/1056
CK
< 284.1[Hz] >
fosc(f )/988
CK
< 303.6[Hz] >
fosc(f )/980
CK
< 306.1[Hz] >
fosc(f )/990
CK
< 303.0[Hz] >
fosc(f )/992
CK
< 302.4[Hz] >
fosc(f )/962
CK
< 311.9[Hz] >
fosc(f )/952
CK
< 315.1[Hz] >
fosc(f )/960
CK
< 312.5[Hz] >
fosc(f )/960
CK
< 312.5[Hz] >
fosc(f )/936
CK
< 320.5[Hz] >
fosc(f )/924
CK
< 324.7[Hz] >
fosc(f )/930
CK
< 322.6[Hz] >
fosc(f )/928
CK
< 323.3[Hz] >
fosc(f )/884
CK
< 339.4[Hz] >
fosc(f )/896
CK
< 334.8[Hz] >
fosc(f )/900
CK
< 333.3[Hz] >
fosc(f )/896
CK
< 334.8[Hz] >
fosc(f )/858
CK
< 349.7[Hz] >
fosc(f )/868
CK
< 345.6[Hz] >
fosc(f )/870
CK
< 344.8[Hz] >
fosc(f )/864
CK
< 347.2[Hz] >
(Note.1) The value of “< >” is a frame frequency when fosc(f ) is 300[kHz].
CK
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20
LC450210PCH
2. “Control of display ON / OFF” instruction
A state of display is set by “Control of display ON / OFF” instruction.
Instruction data (16 bits)
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
PNC
0
1
0
SC0
SC1
0
BU
0
0
1
0
0
0
1
0
(2-1) PNC ··· This is control data to set normal display or reversed display.
Normal display or reversed display is set by this control data. When a state of display is ON
(SC0, SC1=“0, 0”), the setting of PNC becomes effective.
PNC
Normal display or Reversed display
Display data Dn_m=“0”
Display data Dn_m=“1”
0
1
Normal display
OFF
ON
ON
Reversed display
OFF
(Note.1) Display data “Dn_m” is from D1_1 to D200_16.
(2-2) SC0, SC1 ··· These are control data to set a state of display.
A state of display is set by these control data.
SC0 SC1
The state of display
The state of segment outputs
The state of common outputs
0
1
0
1
0
0
1
1
ON
All OFF
Waveform corresponding to display data
OFF waveform
Scan pulse
Scan pulse
Scan pulse
All ON
ON waveform
All forced OFF
V
5 level
LCD
V
5 level
LCD
(2-3) BU ··· This is control data to set normal mode or power-saving mode.
Normal mode or power-saving mode (low current) is set by this control data.
The state of
Internal oscillator
LCD drive bias
BU
Mode
common and
Voltage booster
Contrast adjuster
(Reception state of the external
clock)
voltage generator
segment outputs
Run
(The external clock reception is
possible)
Normal
mode
Normal display
operation
These circuits can run
0
(depend on the setting of DBC,CTC0 and CTC1).
Stop and
discharge
(Note.1)
Stop and
discharge
(Note.1)
Stop and
discharge
(Note.1)
Stop
Power-saving
mode
1
V
5 level
(The external clock is not
received.)
LCD
(Note.1) During (1) or (2) or (3) or (4) time, voltage booster, contrast adjuster and LCD drive bias voltage generator
stop forcibly. And each circuit is the discharge state.
____
(1) The period of RES=“Low level” (Regardless of the setting of voltage booster, contrast adjuster or
LCD drive bias voltage generator)
In the discharge state, the electric potential of VLCD is same as VBTI1. And the electric potential of
VLCD0, VLCD1, VLCD2, VLCD3 and VLCD4 are same as VLCD5.
(2) DBC=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by
“Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD is
same as VBTI1.
(3) CTC0=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by
“Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD0 is
same as VLCD5.
(4) CTC1=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by
“Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD1,
VLCD2, VLCD3 and VLCD4 are same as VLCD5.
(Note.2) When the setting is changed from normal mode to power-saving mode (BU=“0”“1”), secure a stop
transition time more than 200 [msec]. When the setting is changed from power-saving mode to normal
mode (BU=“1”“0”), a time shown from (1) to (3) is needed for stabilization of each circuit.
(Refer to [Fig.9])
(1) When voltage booster, contrast adjuster and LCD drive bias voltage generator are used (DBC=“1”,
CTC0,CTC1=“1,1”), the stabilization time of these circuits is 200 [msec].
(2) When contrast adjuster and LCD drive bias voltage generator are used (DBC=“0”, CTC0,CTC1=“1,1”),
the stabilization time of these circuits is 20 [msec].
(3) When LCD drive bias voltage generator is used (DBC=“0”, CTC0,CTC1=“0,1”), the stabilization time
of this circuit is 20 [msec].
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21
LC450210PCH
3. “Set of line address” instruction
A line address of RAM to specify a start display position is set by “Set of line address” instruction.
Instruction data (16 bits)
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
LNA0 LNA1 LNA2 LNA3
(LSB) (MSB)
0
0
0
0
0
1
0
0
0
0
1
1
(3-1) LNA0 to LNA3 ··· These are control data to set a line address of RAM.
A line address of RAM to specify a start display position is set by these control data.
(ex.1) When a line address is “8H”, the relation between the common output and RAM at the normal scan
(CDIR=“0”) is as follows.
Line address of RAM
A start display position
LSB
MSB
LNA0 LNA1 LNA2 LNA3
1/8 duty
1/9 duty
1/10 duty
1/11 duty
1/12 duty
1/13 duty
1/14 duty
1/15 duty
1/16 duty
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
COM1
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM2
COM2
COM3
COM3
COM4
COM4
COM5
COM5
COM6
COM6
COM7
COM7
COM8
COM8
-
-
-
-
-
-
-
-
COM9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(ex.2) When a line address is “8H”, the relation between the common output and RAM at the reversed scan
(CDIR=“1”) is as follows.
Line address of RAM
A start display position
LSB
MSB
LNA0 LNA1 LNA2 LNA3
1/8 duty
1/9 duty
1/10 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
-
1/11 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
-
1/12 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
-
1/13 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
-
1/14 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
-
1/15 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
-
1/16 duty
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
COM16
COM16
COM15
COM15
COM14
COM14
COM13
COM13
COM12
COM12
COM11
COM11
COM10
COM10
COM9
COM9
-
-
-
-
-
-
-
-
COM8
COM8
-
-
-
-
-
-
-
COM7
COM6
-
COM5
-
-
COM4
-
-
-
COM3
-
-
-
-
COM2
-
-
-
-
-
COM1
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22
LC450210PCH
4. “Write display data to RAM (8 15 bits in a lump)” instruction
The page address and column address of RAM are set by the “Write display data to RAM (8 15 bits in a lump)”
instruction. And the display data of “8 15 bits (8 common outputs 15 segment outputs)” are written to the specified
page address and column address of RAM in a lump by this instruction.
Instruction data (144 bits)
D128
D129
D130
D131
D132
······
······
D243
D244
D245
D246
D247
Dn_m
Dn_m+1
Dn_m+2
Dn_m+3
Dn_m+4
Dn+14_m+3 Dn+14_m+4 Dn+14_m+5 Dn+14_m+6 Dn+14_m+7
(Note.1) n=1 to 186, n+14=15 to 200, m=1, 9
Instruction data (continuance)
D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
CRA0 CRA1 CRA2 CRA3CRA4 CRA5 CRA6 CRA7 PGA
(LSB) (MSB)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
(4-1) CRA0 to CRA7 ··· These are control data to set a column address of RAM.
The settable range of a column address from CRA0 to CRA7 is from 00H to C7H.
When a column address is set more than BAH, display data is written from start position and the
overflowed data from RAM is canceled.
(4-2) PGA ··· This is control data to set a page address of RAM.
(4-3) Dn_m, Dn_m+1 to Dn+14_m+7 ··· These are display data which are written to RAM.
A start position of writing to RAM is set by PGA and the data from CRA0 to
CRA7.
(ex.1) When a page address PGA is set to 0 and a column address from CRA0 to CRA7 is set to 00H, the relation between
instruction data and a direction of writing to RAM is as follows.
Column
C7H
00H
01H
0EH
address
0
Dn_m
Dn+1_m
Dn+14_m
Start position
of writing
Dn_m+1 Dn+1_m+1
Dn_m+7 Dn+1_m+7
Dn+14_m+1
End position
of writing
Dn+14_m+7
display data RAM
1
(ex.2) When a page address PGA is set to 1 and a column address from CRA0 to CRA7 is set to BAH, the relation between
instruction data and a direction of writing to RAM is as follows.
Column
address
C7H
00H
01H
BAH
BBH
0
Canceled
display data
Start position
of writing
display data RAM
Dn_m
Dn+1_m
Dn+13_m
Dn+14_m
1
Dn_m+1 Dn+1_m+1
Dn+13_m+1
Dn+14_m+1
Dn_m+7 Dn+1_m+7
Dn+13_m+7
Dn+14_m+7
End position
of writing
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23
LC450210PCH
5. “Write display data to RAM (16 16 bits in a lump)” instruction
The page address and column address of RAM are set by the “Write display data to RAM (16 16 bits in a lump)”
instruction. And the display data of “16 16 bits (16 common outputs 16 segment outputs)” are written to the
specified page address and column address of RAM in a lump by this instruction.
Instruction data (272 bits)
D0
D1
D2
D3
D4
······
······
D251
D252
D253
D254
D255
Dn_m
Dn_m+1
Dn_m+2
Dn_m+3
Dn_m+4
Dn+15_m+11 Dn+15_m+12 Dn+15_m+13 Dn+15_m+14 Dn+15_m+15
(Note.1) n=1 to 185, n+15=16 to 200, m=1
Instruction data (continuance)
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
CRA0CRA1 CRA2 CRA3 CRA4 CRA5CRA6 CRA7 PGA
(LSB) (MSB)
0
0
0
0
1
0
1
(5-1) CRA0 to CRA7 ··· These are control data to set a column address of RAM.
The settable range of a column address from CRA0 to CRA7 is from 00H to C7H.
When a column address is set more than B9H, display data is written from start position and the
overflowed data from RAM is canceled.
(5-2) PGA ··· This is control data to set a page address of RAM.
When PGA is set to 1, display data is written from start position and the overflowed data from RAM is
canceled.
(5-3) Dn_m, Dn_m+1 to Dn+15_m+15 ··· These are display data which are written to RAM.
The start position of writing to RAM is set by PGA and the data from CRA0 to
CRA7.
(ex.1) When a page address PGA is set to 0 and a column address from CRA0 to CRA7 is set to 04H, the relation between
instruction data and a direction of writing to RAM is as follows.
Column
address
00H 01H 02H 03H
04H
05H
13H
C7H
Dn_m
Dn+1_m
Dn+15_m
0
Start position
of writing
Dn_m+1 Dn+1_m+1
Dn+15_m+1
display data RAM
1
End position
of writing
Dn_m+15 Dn+1_m+15
Dn+15_m+15
(ex.2) When a page address PGA is set to 1 and a column address from CRA0 to CRA7 is set to B9H, the relation between
instruction data and a direction of writing to RAM is as follows.
Column
address
00H 01H 02H 03H
B9H
BAH
C7H
0
Canceled
display data
1
Dn_m
Dn+1_m
Dn+14_m
Dn+15_m
display data RAM
Dn_m+1 Dn+1_m+1
Dn+14_m+1
Dn+15_m+1
Start position
of writing
End position
of writing
Dn_m+7 Dn+1_m+7
Dn_m+8 Dn+1_m+8
Dn+14_m+7
Dn+14_m+8
Canceled
display data
Dn_m+15 Dn+1_m+15
Dn+14_m+15
Dn+15_m+7
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24
LC450210PCH
6. “Set of display contrast” instruction
When contrast adjuster is used, LCD drive bias voltage V
instruction.
0 (High level) is set by “Set of display contrast”
LCD
Instruction data (16 bits)
D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271
CT0
CT1
CT2
CT3
CT4
CT5
0
0
0
0
0
1
0
1
1
0
(LSB)
(MSB)
(6-1) CT0 to CT5 ··· These are control data to set a display contrast.
LCD drive bias voltage V 0 (High level) is set by these control data.
LCD
0 ≤ V
Follow a condition of V
LCD
- 2.4[V]. (Reference example: from (ex.1) to (ex.4))
LCD
(ex.1) V
1=V
BTI
2=3.3V, REGE=VSS,
BTI
(ex.2) V
1=5.0V, REGE=VDD,
BTI
BTI
Quintuple voltage booster and
contrast adjuster are used.
V
2=3.2V (Output, Typ.),
Quintuple voltage booster and
contrast adjuster are used.
V
0 [V]
LCD
V
0 [V]
LCD
V
V
2 5=16.50
LCD
BTI
V
V
2 x 5=16.00
LCD
BTI
2.4V
14.10
13.60
13.50
4.65
4.65
63
0 4
63
Value from CT0 to CT5
0
Value from CT0 to CT5
(ex.3) V
1=VBTI2=3.0V, REGE=VSS,
(ex.4) V
1=5.0V, REGE=VDD,
BTI
BTI
BTI
Quintuple voltage booster and
contrast adjuster are used.
V
2=3.2V (Output, Typ.),
Quadruple voltage booster and
contrast adjuster are used.
V
0 [V]
V
0 [V]
LCD
LCD
V
V
2 5=15.00
LCD
BTI
V
V
2 4=12.80
LCD
BTI
2.4V
2.4V
12.60
10.40
10.35
4.65
4.65
63
0
25
63
0
10
Value from CT0 to CT5
Value from CT0 to CT5
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25
LC450210PCH
Step voltage of LCD drive bias V
0 (High level) (Step voltage width: 0.15V (fixed))
LCD
V
0 level
V
0 level
LCD
LCD
Step
CT0 CT1 CT2 CT3 CT4 CT5
Step
CT0 CT1 CT2 CT3 CT4 CT5
(High level)
(High level)
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14.10 V
13.95 V
13.80 V
13.65 V
13.50 V
13.35 V
13.20 V
13.05 V
12.90 V
12.75 V
12.60 V
12.45 V
12.30 V
12.15 V
12.00 V
11.85 V
11.70 V
11.55 V
11.40 V
11.25 V
11.10 V
10.95 V
10.80 V
10.65 V
10.50 V
10.35 V
10.20 V
10.05 V
9.90 V
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9.30 V
9.15 V
9.00 V
8.85 V
8.70 V
8.55 V
8.40 V
8.25 V
8.10 V
7.95 V
7.80 V
7.65 V
7.50 V
7.35 V
7.20 V
7.05 V
6.90 V
6.75 V
6.60 V
6.45 V
6.30 V
6.15 V
6.00 V
5.85 V
5.70 V
5.55 V
5.40 V
5.25 V
5.10 V
4.95 V
4.80 V
4.65 V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
9.75 V
9.60 V
9.45 V
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26
LC450210PCH
1/8 to 1/16 Duty, 1/4 bias, Line inversion (DR=“0”, WVC=“0”, CDIR=“0”)
V
V
0
1
LCD
LCD
COM1
COM2
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
COM3
V
V
4
5
LCD
LCD
V
V
0
1
LCD
LCD
COM(n-1)
COM(n)
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
V
V
4
5
LCD
LCD
V
0
LCD
LCD
Segment driver output when all
LCD segments are off
V
2
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1 is
on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM2 is
on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1
and COM3 is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to
COM(n-1) is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM(n)
is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when all
LCD segments are on
V
2
LCD
LCD
V
5
To/n
Frame frequency: fo=1/To
To
1/n duty (n is integer from 8 to 16)
(Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display
method” instruction.
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27
LC450210PCH
1/8 to 1/16 Duty, 1/5 bias, Line inversion (DR=“1”, WVC=“0”, CDIR=“0”)
V
V
0
1
LCD
LCD
COM1
COM2
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
COM3
V
V
4
5
LCD
LCD
V
V
0
1
LCD
LCD
COM(n-1)
COM(n)
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
V
V
4
5
LCD
LCD
V
0
LCD
Segment driver output when all
LCD segments are off
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1 is
on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM2 is
on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1
and COM3 is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to
COM(n-1) is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM(n)
is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when all
LCD segments are on
V
V
2
3
LCD
LCD
V
5
LCD
To/n
Frame frequency: fo=1/To
To
1/n duty (n is integer from 8 to 16)
(Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display
method” instruction.
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28
LC450210PCH
1/8 to 1/16 Duty, 1/4 bias, Frame inversion (DR=“0”, WVC=“1”, CDIR=“0”)
V
V
0
1
LCD
LCD
COM1
COM2
COM3
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
V
V
4
5
LCD
LCD
V
V
0
1
LCD
LCD
COM(n-1)
COM(n)
V
V
V
V
4
5
0
1
LCD
LCD
LCD
LCD
V
V
4
5
LCD
LCD
V
0
LCD
LCD
Segment driver output when all
LCD segments are off
V
2
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1 is
on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM2 is
on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1
and COM3 is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to
COM(n-1) is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM(n)
is on
V
2
LCD
V
V
5
0
LCD
LCD
Segment driver output when all
LCD segments are on
V
2
LCD
LCD
V
5
To/n
To/n
Frame frequency: fo=1/To
To
To
1/n duty (n is integer from 8 to 16)
(Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display
method” instruction.
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29
LC450210PCH
1/8 to 1/16 Duty, 1/5 bias, Frame inversion (DR=“1”, WVC=“1”, CDIR=“0”)
V
V
0
1
LCD
LCD
COM1
COM2
COM3
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
V
V
4
5
LCD
LCD
V
V
0
1
LCD
LCD
COM(n-1)
COM(n)
V
V
4
5
0
1
LCD
LCD
V
V
LCD
LCD
V
V
4
5
LCD
LCD
V
0
LCD
V
V
2
3
LCD
LCD
Segment driver output when all
LCD segments are off
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1 is
on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM2 is
on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM1
and COM3 is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to
COM(n-1) is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
Segment driver output when LCD
segment corresponding to COM(n)
is on
V
V
2
3
LCD
LCD
V
V
5
0
LCD
LCD
V
V
2
3
LCD
LCD
Segment driver output when all
LCD segments are on
V
5
LCD
To/n
To/n
To
To
Frame frequency: fo=1/To
1/n duty (n is integer from 8 to 16)
(Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display
method” instruction.
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30
LC450210PCH
____
Caution About Using CE, CL, DI, RES and OSCI with 5 V signal
____
When CE, CL, DI, RES and OSCI are input the 5V signal, these input pads must be observed following points to
prevent destruction.
____
(1) Supply VDD (power supply for logic block) before inputting 5V signal to CE, CL, DI, RES and OSCI.
____
(2) Input 0V to CE, CL, DI, RES and OSCI before shutting down VDD (power supply for logic block).
Peripheral Circuit of OSCI
(1) Internal oscillator operating mode (OC=“0”)
When internal oscillator operating mode is set, make sure to connect OSCI to VSS.
OSCI
(2) External clock operating mode (OC=“1”)
When external clock operating mode is set, make sure to input the clock (f : 100 to 600 [kHz]) to OSCI from the
CK
outside.
External clock output pad
External oscillator
OSCI
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31
LC450210PCH
Power Supply Sequence
The following sequence must be observed when power supply is supplied and shut down. (Refer from [Fig.5] to
[Fig.8])
When voltage booster is used
< 5 V power supply REGE = VDD >
(1) When power supply is supplied:
Supply VDD (power supply for logic block).
Input a base voltage for voltage booster to VBTI1 after wait time for inputting voltage ( 0). Reset
____
cancellation with RES=“High level” (Reset pulse width ( 1[msec])).
Wait time for inputting serial data ( 1[msec]).
Set DBC to 1 by “Set of display method” instruction.
(2) When power supply is shut down:
Set BU to 1 by “Control of display ON / OFF” instruction.
____
Wait for stop transition time of each circuit ( 200[msec]). Reset with RES=“Low level”.
Stop inputting a base voltage for voltage booster to VBTI1.
Wait time for shutting down the power supply ( 0).
Shut down VDD (power supply for logic block).
< 3 V power supply REGE = VSS >
(1) When power supply is supplied:
Supply VDD (power supply for logic block).
Input a base voltage for voltage booster to VBTI1 and VBTI2 after wait time for inputting voltage ( 0).
____
Reset cancellation with RES=“High level” (Reset pulse width ( 1[msec])).
Wait time for inputting serial data ( 1[msec]).
Set DBC to 1 by “Set of display method” instruction.
(2) When power supply is shut down:
Set BU to 1 by “Control of display ON / OFF” instruction.
____
Wait for stop transition time of each circuit ( 200[msec]). Reset with RES=“Low level”.
Stop inputting a base voltage for voltage booster to VBTI1 and VBTI2.
Wait time for shutting down the power supply ( 0).
Shut down VDD (power supply for logic block).
When voltage booster is not used
(1) When power supply is supplied:
Supply VDD (power supply for logic block).
____
Reset cancellation with RES=“High level” (Reset pulse width ( 1[msec])).
Wait time for supplying voltage and wait time for inputting serial data ( 1[msec]).
Supply VLCD (power supply for LCD driver block).
Set DBC to 0 by “Set of display method” instruction.
(2) When power supply is shut down:
Set BU to 1 by “Control of display ON / OFF” instruction.
Wait for stop transition time of each circuit ( 200[msec]).
Shut down VLCD (power supply for LCD driver block).
Wait time for a reset ( 0).
____
Reset with RES=“Low level”.
Wait time for shutting down the power supply ( 0).
Shut down VDD (power supply for logic block).
(Note.1) Make sure to open VBTI1, VBTI2, CP1P, CP12N, CP2P, CP3P, CP34N and CP4P.
After the following page, examples of power supply sequence and set or cancel the power-saving mode during
supplying power.
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32
LC450210PCH
(ex.1) Voltage booster, contrast adjuster and LCD drive bias voltage generator are used.
twres
t4
t5
t6
t11
VDD (Power)
t9
V
____
RES (Input)
1
IH
V
1
IL
t2
VBTI1 (Input)
V
2 5, V
2 4
BTI
BTI
V
1
V
V
1
BTI
BTI
VLCD (Output)
Voltage booster is running.
VLCD0 (Output)
V
V
5
5
5
LCD
LCD
Contrast adjuster is running.
VLCD1 to VLCD4 (Output)
5
V
LCD
LCD
LCD drive bias voltage generator is running.
Run
Internal oscillator
(Internal oscillator
operating mode)
Stop
Stop
OSCI (Input)
(External clock
operating mode)
External clock receiver
(External clock
Disable
Enable
Disable
operating mode)
State of display
(common and segment
output pads)
ON
All forced OFF : Fixed low level(V
5)
All forced OFF : Fixed low level(V 5)
LCD
LCD
Instruction
(1) (2)(3) (4)
(5)
(6)
Instruction
(1) “Set of display method” is executed. (DBC=“1”, CTC0, CTC1=“1, 1”)
Make sure to execute “Set of display method” first.
When external clock operating mode is set, make sure to set OC to 1.
(2) “Set of display contrast” is executed.
(3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a
lump)” is executed.
(4) “Set of line address” is executed.
(5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”)
(6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”)
Constraint on the timing
Reset pulse width
Wait time for inputting voltage
: twres 1[msec]
: t2 0
Wait time for inputting serial data
: t9 1 [msec]
Stabilization time of voltage booster, contrast adjuster
and LCD drive bias voltage generator
Wait time for display on
: t4 200 [msec]
: t5 > 0
Stop transition time of voltage booster, contrast adjuster
and LCD drive bias voltage generator
Wait time for shutting down the power supply
: t6 200 [msec]
: t11 0
[Fig.5]
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33
LC450210PCH
(ex.2) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster and LCD drive bias
voltage generator are used.
twres
t12
t5
t13
t11
VDD (Power)
t9
____
RES (Input)
V
1
IH
V
1
V
1
IL
IL
t18
VLCD (Power)
Supplied from the outside.
Contrast adjuster is running.
t10
5
VLCD0 (Output)
V
V
V
V
5
LCD
LCD
VLCD1 to VLCD4 (Output)
5
5
LCD
LCD
LCD drive bias voltage generator is running.
Internal oscillator
(Internal oscillator
operating mode)
Stop
Run
Stop
OSCI (Input)
(External clock
operating mode)
External clock receiver
(External clock
Disable
Enable
Disable
operating mode)
State of display
(common and segment
output pads)
ON
All forced OFF : Fixed low level(V
5)
All forced OFF : Fixed low level(V 5)
LCD
LCD
(1) (2) (3) (4)
(5)
(6)
Instruction
Instruction
(1) “Set of display method” is executed. (DBC=“0”, CTC0, CTC1=“1, 1”)
Make sure to execute “Set of display method” first.
When external clock operating mode is set, make sure to set OC to 1.
(2) “Set of display contrast” is executed.
(3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a
lump)” is executed.
(4) “Set of line address” is executed.
(5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”)
(6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”)
Constraint on the timing
Reset pulse width
: twres 1 [msec]
: t10 1 [msec]
: t9 1 [msec]
Wait time for supplying voltage
Wait time for inputting serial data
Stabilization time of contrast adjuster
and LCD drive bias voltage generator
Wait time for display on
: t12 20 [msec]
: t5 > 0
Stop transition time of contrast adjuster
and LCD drive bias voltage generator
Wait time for shutting down the power supply
Wait time for a reset
: t13 200 [msec]
: t11 0
: t18 > 0
Follow a condition of V
V 0 > V
LCD
1 > V
LCD LCD
2 > V 3 > V
LCD
4 > V
LCD
5.
LCD
LCD
[Fig.6]
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34
LC450210PCH
(ex.3) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster is not used, and VLCD0
is input from the outside. LCD drive bias voltage generator is used.
twres
t12
t5
t13
t11
VDD (Power)
t9
____
RES (Input)
V
1
IH
V
1
V
1
IL
IL
t18
VLCD (Power)
VLCD0 (Input)
Supplied from the outside.
Input from the outside.
t10
VLCD1 to VLCD4 (Output)
V
5
LCD
V
5
LCD
LCD drive bias voltage generator is running.
Internal oscillator
(Internal oscillator
operating mode)
Stop
Run
Stop
OSCI (Input)
(External clock
operating mode)
External clock receiver
(External clock
Disable
Enable
Disable
operating mode)
State of display
(common and segment
output pads)
All forced OFF : Fixed low level(V
5)
All Forced OFF : Fixed low level(V 5)
LCD
ON
LCD
Instruction
(1) (2) (3) (4)
(5)
(6)
Instruction
(1) “Set of display method” is executed. (DBC=”0”, CTC0, CTC1=”0, 1”)
Make sure to execute “Set of display method” first.
When external clock operating mode is set, make sure to set OC to 1.
(2) “Set of display contrast” is executed.
(3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a
lump)” is executed.
(4) “Set of line address” is executed.
(5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”)
(6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”)
Constraint on the timing
Reset pulse width
Wait time for supplying voltage
Wait time for inputting serial data
: twres 1 [msec]
: t10 1 [msec]
: t9 1 [msec]
Stabilization time of LCD drive bias voltage generator : t12 20 [msec]
Wait time for display on : t5 > 0
Stop transition time of LCD drive bias voltage generator : t13 200 [msec]
Wait time for shutting down the power supply
: t11 0
Wait time for a reset
: t18 > 0
Follow a condition of V
V 0 > V
LCD
1 > V
LCD LCD
2 > V 3 > V
LCD
4 > V
LCD
5.
LCD
LCD
[Fig.7]
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35
LC450210PCH
(ex.4) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster and LCD drive bias
voltage generator are not used. From VLCD0 to VLCD4 is input from the outside.
twres
t14
t5
t15
t11
VDD (Power)
t9
____
RES (Input)
V
1
IH
V
1
V
1
IL
IL
t18
VLCD (Power)
VLCD0 (Input)
Supplied from the outside.
Input from the outside.
t10
VLCD1 to VLCD4 (Input)
VLCD1 to VLCD4 is input from the outside.
Internal oscillator
(Internal oscillator
operating mode)
Stop
Stop
Run
OSCI (Input)
(External clock
operating mode)
External clock receiver
(External clock
Disable
Enable
Disable
operating mode)
State of display
(common and segment
output pads)
All forced OFF : Fixed low level(V
5)
ON
All Forced OFF : Fixed low level(V 5)
LCD
LCD
Instruction
(1) (2) (3) (4)
(5)
(6)
Instruction
(1) “Set of display method” is executed. (DBC=“0”, CTC0, CTC1=“0, 0”)
Make sure to execute “Set of display method” first.
When external clock operating mode is set, make sure to set OC to 1.
(2) “Set of display contrast” is executed.
(3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a
lump)” is executed.
(4) “Set of line address” is executed.
(5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”)
(6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”)
Constraint on the timing
Reset pulse width
: twres 1 [msec]
Wait time for supplying voltage
Wait time for inputting serial data
Stabilization time of external power supply
Wait time for display on
: t10 1 [msec]
: t9 1 [msec]
: t14 Stabilization time of external power supply
: t5 > 0
Stop transition time of external power supply
Wait time for shutting down the power supply
Wait time for a reset
: t15 Stop time of external power supply
: t11 0
: t18 > 0
Follow a condition of V
V 0 > V
LCD
1 > V
LCD LCD
2 > V 3 > V
LCD
4 > V
LCD
5.
LCD
LCD
[Fig.8]
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36
LC450210PCH
(ex.5) Power-saving mode is set and canceled. (Voltage booster, contrast adjuster and LCD drive bias voltage generator
are used.)
Power-saving mode
t16
t4
t5
5.0V
VDD (Power)
High level
____
RES (Input)
5.0V
VBTI1 (Input)
V
2 5, V
2 4
BTI
V
2 5, V
2 4
BTI
BTI
BTI
VLCD (Output)
V
V
1
BTI
Voltage booster
is running.
Voltage booster
is running.
V
0
V
0
LCD
LCD
VLCD0 (Output)
5
5
LCD
Contrast adjuster
is running.
Contrast adjuster
is running.
VLCD1 to VLCD4 (Output)
V
LCD
LCD drive bias voltage
generator is running.
LCD drive bias voltage
generator is running.
Internal oscillator
(Internal oscillator
operating mode)
Run
Stop
Run
OSCI (Input)
(External clock
operating mode)
External clock receiver
(External clock
Enable
ON
Disable
Enable
operating mode)
State of display
(common and segment
output pads)
ON
All forced OFF : Fixed low level(V
5)
LCD
(2)
(3)
(1)
Instruction
Instruction
(1) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”)
(2) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“0”)
(3) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”)
Constraint on the timing
Stabilization time of voltage booster, contrast adjuster
and LCD drive bias voltage generator
Stop transition time of voltage booster, contrast adjuster
and LCD drive bias voltage generator
Wait time for display on
: t4 200 [msec]
: t16 200 [msec]
: t5 > 0
[Fig.9]
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37
LC450210PCH
System Reset
1. Reset function
____
This LSI can reset the system by RES pad.
2. State of each block during reset
(1) CLOCK GENERATOR, TIMING GENERATOR
____
These circuits are initialized forcibly during reset (RES=“Low level”).
(2) INSTRUCTION REGISTER & DECODER, CCB INTERFACE, SHIFT REGISTER
____
Contents of these circuits are initialized forcibly, and these circuits don't accept serial data during reset (RES
=“Low level”).
(3) ADDRESS COUNTOR
____
Contents of this circuit are initialized forcibly during reset (RES=“Low level”).
(4) DISPLAY DATA RAM
Contents of RAM are not affected by reset.
(5) LATCH
Contents of LATCH are not affected by reset.
(6) COMMON DRIVER, SEGMENT DRIVER
Common drivers and segment drivers output V
(RES=“Low level”).
5 level, the display of LCD is forced OFF during reset
LCD
____
(7) VOLTAGE BOOSTER
____
Voltage booster stops, and the electric potential of VLCD is same as VBTI1 during reset (RES=“Low level”).
(8) CONTRAST ADJUSTER
____
Contrast adjuster stops, and the electric potential of VLCD0 is same as VLCD5 during reset (RES=“Low level”).
(9) LCD DRIVE BIAS VOLTAGE GENERATOR
LCD drive bias voltage generator stops, and the electric potential of VLCD1, VLCD2, VLCD3 and VLCD4 are
____
same as VLCD5 during reset (RES=“Low level”).
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38
LC450210PCH
3. The state of PAD during reset
PAD
S1 to S200
COM1 to COM16
VLCD
The state during reset
PAD
The state during reset
V
5
5
VLCD1
VLCD2
VLCD3
VLCD4
V
V
V
V
5
5
5
5
LCD
LCD
LCD
LCD
LCD
V
V
V
LCD
1
BTI
VLCD0
5
LCD
REGE
V
V
1
2
BTI
BTI
VOLTAGE
BOOSTER
CP1P
CP12N
CP2P
COMMON DRIVER
SEGMENT DRIVER
CP3P
CP34N
CP4P
LACTH
V
LCD
CONTRAST
ADJUSTER
DISPLAY DATA
RAM
ADDRESS
COUNTER
V
0
1
2
3
4
5
LCD
LCD
LCD
LCD
LCD
LCD
( 16 200 bits )
LCD DRIVE
BIAS VOLTAGE
GENERATOR
V
V
V
V
V
INSTRUCTION REGISTER & DECODER
SHIFT REGISTER
____
RES
V
DD
TIMING
GENERATOR
REGULATOR
CLOCK
GENERATOR
CCB INTERFACE
V
SS
TSIN1 to 4
TSOUT1 to 3
TSO
The reset block
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39
LC450210PCH
Sample Circuits
Sample circuits are as follows.
LCD drive bias
voltage
Duty
Bias
1/5
VDD
5.0V
VLCD
Voltage booster
Contrast adjuster
Used
generator
VLCD is not supplied
from the outside.
Quintuple
Sample circuit (1)
1/8 to 1/16
Used
voltage boost
VLCD is not supplied
from the outside.
Quadruple
Sample circuit (2)
Sample circuit (3)
1/8 to 1/16
1/8 to 1/16
1/5
1/5
5.0V
3.0V
Used
Used
Used
Used
voltage boost
VLCD is not supplied
from the outside.
Quintuple
voltage boost
VLCD is supplied from
the outside.
Sample circuit (4)
Sample circuit (5)
Sample circuit (6)
1/8 to 1/16
1/8 to 1/16
1/8 to 1/16
1/5
1/5
1/5
5.0V
5.0V
5.0V
Unused
Unused
Unused
Used
Used
Used
(16.5V)
VLCD is supplied from
the outside.
Unused
Unused
(16.5V)
VLCD is supplied from
the outside.
Unused
(16.5V)
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40
LC450210PCH
Sample circuit (1)
1/8 to 1/16 Duty, 1/5 bias,
V
= 5.0 V, V
= 5.0 V,
DD
BTI1
Quintuple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used.
(REGE=VDD, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.)
+5.0V
+5.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
D
Cbt
Cbt
(*3)
S199
CP1P
(*4)
+
S198
C1
S197
CP12N
S196
C2
+
+
CP2P
CP3P
S6
S5
S4
S3
S2
S1
C3
C4
CP34N
CP4P
+
VLCD
VLCD0
VLCD1
VLCD2
VLCD3 (*1)
VLCD4
VLCD5
Cvm
Cvm
Cvm
Cvm
Cvm
+
Cvl
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ C4 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
(*3) Make sure to open unused common and segment drivers.
(*4) When “V
BTI
1 > 5.5V” is assumed during discharge of
capacitors for voltage booster, make sure to connect
4.5V ≤ V
V
1 ≤ V
≤ 5.5V
BTI
=16.0V[Typ.] (=V
DD
2 5)
BTI
a zener diode “D” between VBTI1 and VSS.
LCD
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41
LC450210PCH
Sample circuit (2)
1/8 to 1/16 Duty, 1/5 bias,
V
= 5.0 V, V
= 5.0 V,
DD
BTI1
Quadruple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used.
(REGE=VDD, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.)
+5.0V
+5.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
D
Cbt
Cbt
(*3)
S199
CP1P
(*4)
+
S198
C1
S197
CP12N
S196
C2
+
+
CP2P
CP3P
S6
S5
S4
S3
S2
S1
C3
CP34N
CP4P
VLCD
VLCD0
VLCD1
VLCD2
VLCD3 (*1)
VLCD4
VLCD5
Cvm
Cvm
Cvm
Cvm
Cvm
+
Cvl
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
(*3) Make sure to open unused common and segment drivers.
4.5V ≤ V
1 ≤ V
≤ 5.5V
2 4)
BTI
(*4) When “V
BTI
1 > 5.5V” is assumed during discharge of
BTI
=12.8V[Typ.] (=V
DD
V
capacitors for voltage booster, make sure to connect
a zener diode “D” between VBTI1 and VSS.
LCD
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42
LC450210PCH
Sample circuit (3)
1/8 to 1/16 Duty, 1/5 bias,
V
= 3.0 V, V
1 = V
BTI
2 = 3.0 V,
BTI
DD
Quintuple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used.
(REGE=VSS, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.)
+3.0V
+3.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
D
Cbt
(*3)
S199
(*4)
CP1P
+
S198
C1
C2
S197
CP12N
S196
+
+
CP2P
CP3P
S6
S5
S4
S3
S2
S1
C3
C4
CP34N
CP4P
+
VLCD
VLCD0
VLCD1
VLCD2
VLCD3 (*1)
VLCD4
VLCD5
Cvm
Cvm
Cvm
Cvm
Cvm
+
Cvl
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cbt ≤ 10[F]
1[F] ≤ C1 ≤ 10[F]
1[F] ≤ C2 ≤ 10[F]
1[F] ≤ C3 ≤ 10[F]
1[F] ≤ C4 ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
(*3) Make sure to open unused common and segment drivers.
0.1[F] ≤ Cvm ≤ 0.47[F]
2.7V ≤ V 1=V 2 ≤ V
(*4) When “V
BTI
1 > 3.6V” is assumed during discharge of
≤ 3.3V
capacitors for voltage booster, make sure to connect
a zener diode “D” between VBTI1 and VSS.
BTI
BTI
DD
2 5)
BTI
V
=15.0V[Typ.] (=V
LCD
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43
LC450210PCH
Sample circuit (4)
1/8 to 1/16 Duty, 1/5 bias,
V
= 5.0 V, V
= 16.5 V (Voltage booster is not used, and supply VLCD from the outside),
DD
LCD
Contrast adjuster and LCD drive bias voltage generator are used.
(REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.)
+5.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
(*3)
S199
CP1P
S198
OPEN
S197
CP12N
S196
CP2P
CP3P
S6
S5
S4
S3
S2
S1
CP34N
CP4P
VLCD
+16.5V
VLCD0
VLCD1
VLCD2
VLCD3 (*1)
VLCD4
VLCD5
Cvm
Cvm
Cvm
Cvm
Cvm
+
Cvl
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
4.5V ≤ V
≤ 16.5V
LCD
(*3) Make sure to open unused common and segment drivers.
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44
LC450210PCH
Sample circuit (5)
1/8 to 1/16 Duty, 1/5 bias,
V
= 5.0 V, V
= 16.5 V (Voltage booster is not used, and supply VLCD from the outside),
DD
LCD
Contrast adjuster is not used (Input the VLCD voltage to VLCD0 pad),
LCD drive bias voltage generator is used.
(REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“0, 1”, DR=“1”) is executed.)
+5.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
(*3)
S199
CP1P
S198
OPEN
S197
CP12N
S196
CP2P
CP3P
S6
S5
S4
S3
S2
S1
CP34N
CP4P
VLCD
+16.5V
VLCD0
VLCD1
VLCD2
VLCD3 (*1)
VLCD4
VLCD5
Cvm
Cvm
Cvm
Cvm
+
Cvl
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
4.5V ≤ V
≤ 16.5V
LCD
0=V
V
LCD
LCD
(*3) Make sure to open unused common and segment drivers.
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45
LC450210PCH
Sample circuit (6)
1/8 to 1/16 Duty, 1/5 bias,
V
= 5.0 V, V
= 16.5 V (Voltage booster is not used, and supply VLCD from the outside),
DD
LCD
Contrast adjuster and LCD drive bias voltage generator are not used (Input the voltage to VLCD0, VLCD1, VLCD2,
VLCD3 and VLCD4 from the outside.).
(REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“0, 0”, DR=“1”) is executed.)
+5.0V
VDD
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S200
REGE
+
Cvd
LCD panel
TSIN1 to TSIN4
VSS
1/8 duty
(8com 200seg)
to
1/16 duty
(16com 200seg)
VBTI1
VBTI2
(*3)
CP1P
CP12N
OPEN
S199
S198
CP2P
CP3P
S197
S196
CP34N
CP4P
VLCD
S6
S5
S4
S3
S2
S1
+16.5V
Cvl
+
5/5 V
4/5 V
3/5 V
2/5 V
1/5 V
0 (when 1/5 bias is used)
0 (when 1/5 bias is used)
0 (when 1/5 bias is used)
0 (when 1/5 bias is used)
0 (when 1/5 bias is used)
VLCD0
VLCD1
VLCD2
LCD
LCD
LCD
LCD
LCD
Cvm
Cvm
Cvm
Cvm
Cvm
(*1)
VLCD3
VLCD4
VLCD5
Input the external clock
From the controller
OSCI (*2)
__
VLOGIC
RES
CE
CL
TSOUT1 to TSOUT3
TSO
OPEN
DI
1[F] ≤ Cvd ≤ 10[F]
1[F] ≤ Cvl ≤ 10[F]
0.1[F] ≤ Cvm ≤ 0.47[F]
(*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3.
(*2) When the internal oscillator operating mode is set (OC=“0”),
make sure to connect OSCI to VSS.
4.5V ≤ V
≤ 16.5V
LCD
V
V
V
V
V
1 < V
0 ≤ V
1 < V
2 < V
3 < V
4 < V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
2 < V
3 < V
4 < V
5 < V
0
1
2
3
(*3) Make sure to open unused common and segment drivers.
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46
LC450210PCH
Caution
Caution is provided as follows for the stable operation of this LSI. However, caution does not provide any guarantee
for operation and characteristics of this LSI.
Moreover, examples of application circuit described are used only to explain internal operation and usage of this LSI.
Therefore, it is necessary to design an application or set, in consideration of an LCD specification and condition.
(1) Power supply pads
All power supply pads must be connected to the power supply, and don’t open.
(2) ITO (Indium Tin Oxide) line
Wire the ITO line for power supply and voltage booster as short and wide as possible, because it is necessary to
minimize the parasitic resistance of ITO line.
(3) Signal wiring and connection
DUMMY pads should be opened.
(4) Unused input pads
Unfixed input pads cause the unstable operation or the leak current of power supply, because this LSI adopts a
CMOS process. Make sure to connect the open pad of logic input to VDD or VSS.
(5) Protection from light
An exposure to the light may cause the malfunction of this LSI. Make sure to shut out the surface, side and back of
this LSI from the light when this LSI is mounted to the product.
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47
LC450210PCH
PAD Assignment (Bump Side View)
Unit: [m]
DUMMY PAD No.1
Alignment mark 2
PAD No.311 VLCD4
PAD No.310 VLCD4
PAD No.309 VLCD4
PAD No.308 VLCD1
PAD No.307 VLCD1
PAD No.306 VLCD1
PAD No.305 VLCD3
S1 PAD No.2
S2 PAD No.3
S3 PAD No.4
S4 PAD No.5
S5 PAD No.6
S6 PAD No.7
Bump shape A
Bump shape C
(Segment driver)
(Power supply, I/O)
+Y
68
170
27
23
+X
65
35
(0,0)
50
100
S = 4,590 [m2] (Typ.)
S = 4,420 [m2] (Typ.)
Chip name
PAD No.218 CE
PAD No.217 RES
PAD No.216 VLOGIC
PAD No.215 TSO
S195 PAD No.196
S196 PAD No.197
S197 PAD No.198
S198 PAD No.199
S199 PAD No.200
S200 PAD No.201
PAD No.214 TSOUT3
PAD No.213 TSOUT2
PAD No.212 TSOUT1
Alignment mark 3
Alignment mark 1
Bump shape B
(Common driver)
DUMMY PAD No.202
30
45
99
75
S = 4,455 [m2] (Typ.)
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48
LC450210PCH
Chip size (X, Y and S are based on the dicing center.)
X = 1.49 mm Y = 10.63 mm S = 15.8387 mm2 Chip thickness = 400 m
Au bump (Typ.)
Size
Item
PAD No.
1 to 202
Bump shape
A
X [m]
170
45
Y [m]
S [m2]
27
99
65
4,590
203 to 210,
313 to 320
Bump size
B
C
A
4,455
4,420
-
211 to 312
1 to 202
68
50
203 to 210,
313 to 320
Min. bump pitch
B
C
A
75
100
23
-
-
-
211 to 312
1 to 202
203 to 210,
313 to 320
Min. bump clearance
Bump height
B
C
30
35
-
-
211 to 312
All bumps
17
-
Alignment mark
Alignment mark 1
Alignment mark 2
Alignment mark 3
10
30
60
50
80
20
Unit: m
50
80
Center coordinates of alignment marks
Alignment mark
Alignment mark 1
Alignment mark 2
Alignment mark 3
X coordinate [m]
Y coordinate [m]
-628
-628
638
-5110
5110
-5070
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49
LC450210PCH
Center coordinates of PADs
X
Y
X
Y
PAD
No.
PAD
Bump
shape
PAD
PAD
Bump
shape
coordinate
coordinate
[m]
coordinate
[m]
coordinate
[m]
Name
No.
Name
[m]
1
DUMMY
S1
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
5216
4975
4925
4875
4825
4775
4725
4675
4625
4575
4525
4475
4425
4375
4325
4275
4225
4175
4125
4075
4025
3975
3925
3875
3825
3775
3725
3675
3625
3575
3525
3475
3425
3375
3325
3275
3225
3175
3125
3075
3025
2975
2925
2875
2825
2775
2725
2675
2625
2575
2525
2475
2425
2375
2325
2275
2225
2175
2125
2075
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
61
62
S60
S61
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
2025
1975
1925
1875
1825
1775
1725
1675
1625
1575
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2
3
S2
63
S62
4
S3
64
S63
5
S4
65
S64
6
S5
66
S65
7
S6
67
S66
8
S7
68
S67
9
S8
69
S68
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
S9
70
S69
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
71
S70
72
S71
73
S72
74
S73
75
S74
76
S75
77
S76
78
S77
79
S78
80
S79
81
S80
82
S81
83
S82
925
84
S83
875
85
S84
825
86
S85
775
87
S86
725
88
S87
675
89
S88
625
90
S89
575
91
S90
525
92
S91
475
93
S92
425
94
S93
375
95
S94
325
96
S95
275
97
S96
225
98
S97
175
99
S98
125
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
S99
75
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
25
-25
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
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50
LC450210PCH
X
Y
X
Y
PAD
No.
PAD
Bump
PAD
No.
PAD
Bump
shape
coordinate
[m]
coordinate
[m]
coordinate
[m]
coordinate
[m]
Name
shape
Name
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
S175
S176
S177
S178
S179
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-975
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
S180
S181
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-574.5
-135
-3975
-4025
-4075
-4125
-4175
-4225
-4275
-4325
-4375
-4425
-4475
-4525
-4575
-4625
-4675
-4725
-4775
-4825
-4875
-4925
-4975
-5216
-5182
-5182
-5182
-5182
-5182
-5182
-5182
-5182
-5197
-4900
-4800
-4700
-4600
-4500
-4400
-4300
-4200
-4100
-4000
-3900
-3800
-3700
-3600
-3500
-3400
-3300
-3200
-3100
-3000
-2900
-2800
-2700
-2600
-2500
-2400
-2300
-2200
-2100
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
-1025
-1075
-1125
-1175
-1225
-1275
-1325
-1375
-1425
-1475
-1525
-1575
-1625
-1675
-1725
-1775
-1825
-1875
-1925
-1975
-2025
-2075
-2125
-2175
-2225
-2275
-2325
-2375
-2425
-2475
-2525
-2575
-2625
-2675
-2725
-2775
-2825
-2875
-2925
-2975
-3025
-3075
-3125
-3175
-3225
-3275
-3325
-3375
-3425
-3475
-3525
-3575
-3625
-3675
-3725
-3775
-3825
-3875
-3925
S182
S183
S184
S185
S186
S187
S188
S189
S190
S191
S192
S193
S194
S195
S196
S197
S198
S199
S200
DUMMY
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
DUMMY
TSOUT1
TSOUT2
TSOUT3
TSO
-60
15
90
165
240
315
390
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
VLOGIC
_______
RES
CE
DI
CL
OSCI
TSIN1
TSIN2
TSIN3
TSIN4
VSS
VSS
VSS
VSS
REGE
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
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51
LC450210PCH
X
Y
X
Y
PAD
No.
PAD
Bump
shape
PAD
No.
PAD
Bump
shape
coordinate
[m]
coordinate
[m]
coordinate
[m]
coordinate
[m]
Name
Name
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
VSS
VSS
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
-2000
-1900
-1800
-1700
-1600
-1500
-1400
-1300
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
VLCD2
VLCD2
VLCD3
VLCD3
VLCD3
VLCD1
VLCD1
VLCD1
VLCD4
VLCD4
VLCD4
DUMMY
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
623.5
390
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5197
5182
5182
5182
5182
5182
5182
5182
5182
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
VSS
VBTI1
VBTI1
VBTI1
VBTI1
VBTI1
VBTI2
VBTI2
VBTI2
VBTI2
VBTI2
CP1P
315
CP1P
240
CP1P
165
CP1P
90
CP12N
CP12N
CP12N
CP12N
CP12N
CP12N
CP12N
CP2P
15
-60
-135
100
200
300
400
CP2P
500
CP2P
600
CP2P
700
CP3P
800
CP3P
900
CP3P
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
CP3P
CP34N
CP34N
CP34N
CP34N
CP34N
CP34N
CP34N
CP4P
CP4P
CP4P
CP4P
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD0
VLCD0
VLCD0
VLCD0
VLCD0
VLCD5
VLCD5
VLCD5
VLCD5
VLCD5
VLCD2
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52
LC450210PCH
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
960 / Waffle Pack
Chip with Au bumps
(Pb-Free)
LC450210PCH-T3
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in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
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53
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