FST3126MX [ONSEMI]
4 位总线开关;
| 型号： | FST3126MX |
| 厂家： | 
ONSEMI |
| 描述： | 4 位总线开关 开关 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FST3126
Product Preview
4-Bit Bus Switch
The ON Semiconductor FST3126 is a quad, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low R
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.
The device consists of four independent 1−bit switches with
separate Output/Enable (OE) pins. Port A is connected to Port B when
OE is high. If OE is low, the switch is high Z.
and adds
ON
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MARKING
DIAGRAMS
14
14
FST3126G
AWLYWW
1
Features
SOIC−14
D SUFFIX
CASE 751A
• R t 4 W Typical
ON
1
• Less Than 0.25 ns−Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
14
1
14
• Control Inputs are TTL/CMOS Compatible
• Pin−For−Pin Compatible With QS3126, FST3126, CBT3126
• All Popular Packages: SOIC−14 & TSSOP−14
• These are Pb−Free Devices
FST
3126
ALYWG
G
1
TSSOP−14
DT SUFFIX
CASE 948G
1
2
3
4
5
6
7
14
13
12
11
10
9
OE
1A
1B
OE
2A
V
CC
A
= Assembly Location
= Year
1
OE
4A
4B
OE
3A
3B
WL, L = Wafer Lot
Y
WW, W = Work Week
4
3
2
G or G = Pb−Free Package
2B
GND
(Note: Microdot may be in either location)
8
PIN NAMES
Figure 1. Pin Assignment for
SOIC and TSSOP
Pin
OE , OE , OE , OE
4
Description
Bus Switch Enables
1
2
3
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
NC
Bus A
Bus B
Not Connected
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
July, 2013 − Rev. P1
FST3126/D
FST3126
1
OE
1
2
4
3
1A
1B
2B
3B
4B
OE
2
5
6
2A
10
OE
3
9
8
3A
13
OE
4
12
11
4A
Figure 2. Logic Diagram
TRUTH TABLE
Inputs
Outputs
A, B
OE
L
Z
H
A = B
ORDERING INFORMATION
†
Device Order Number
Package
Shipping
FST3126DR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
FST3126DTR2G
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
FST3126
MAXIMUM RATINGS
Symbol
Parameter
Value
*0.5 to )7.0
*0.5 to )7.0
*0.5 to )7.0
*50
Unit
V
V
CC
DC Supply Voltage
V
DC Input Voltage
V
I
O
V
DC Output Voltage
V
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
V t GND
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
IK
I
I
V
t GND
O
*50
OK
I
128
O
I
$100
CC
I
$100
GND
T
*65 to )150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
L
T
)150
J
q
Thermal Resistance (Note 1)
SOIC
TSSOP
125
170
JA
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model
u4000
u300
u2000
V
I
Latchup Performance
Above V and Below GND at 85_C (Note 4)
$500
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.0
0
Max
5.5
Unit
V
V
CC
Supply Voltage
Operating, Data Retention Only
(Note 5)
V
I
Input Voltage
5.5
V
V
O
Output Voltage
(HIGH or LOW State)
0
5.5
V
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
−55
+125
_C
ns/V
A
Dt/DV
Switch Control Input
Switch I/O
0
0
5
DC
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
FST3126
DC ELECTRICAL CHARACTERISTICS
V
T = −55_C to +125_C
CC
A
Symbol
Parameter
Conditions
(V)
4.5
Min
Typ*
Max
Unit
V
V
Clamp Diode Resistance
High−Level Input Voltage
Low−Level Input Voltage
Input Leakage Current
I
= *18mA
*1.2
IK
IH
IN
V
4.0 to 5.5
4.0 to 5.5
5.5
2.0
V
V
IL
I
I
0.8
$1.0
$1.0
7
V
0 v V v 5.5 V
mA
mA
W
IN
I
OFF−STATE Leakage Current
Switch On Resistance (Note 6)
0 v A, B v V
5.5
OZ
CC
R
V
V
V
V
V
= 0 V, I = 64 mA
4.5
4
4
ON
IN
IN
IN
IN
IN
IN
= 0 V, I = 30 mA
4.5
7
IN
= 2.4 V, I = 15 mA
4.5
8
15
IN
= 2.4 V, I = 15 mA
4.0
11
20
IN
I
Quiescent Supply Current
= V or GND, I = 0
OUT
5.5
3
mA
CC
CC
DI
CC
Increase In I per Input
One input at 3.4 V, Other inputs at V or GND
5.5
2.5
mA
CC
CC
*Typical values are at V = 5.0 V and T = 25_C.
CC
A
6. Measured by the voltage drop between A and B pins at the indicated current through the switch.
AC ELECTRICAL CHARACTERISTICS
Limits
T = −55_C to +125_C
A
V
CC
= 4.5 to 5.5 V
V
= 4.0 V
CC
Symbol
Parameter
Conditions
V = OPEN
Figures
Min
Max
Min
Max
Unit
t
,
Prop Delay Bus to Bus
(Note 7)
3 and 4
0.25
0.25
ns
PHL
I
t
PLH
t
,
Output Enable Time
V = 7 V for t
PZL
3 and 4
3 and 4
1.0
1.5
4.5
5.7
5.0
6.2
ns
ns
PZH
I
t
V = OPEN for t
PZL
I
PZH
t
,
Output Disable Time
V = 7 V for t
I PLZ
PHZ
t
V = OPEN for t
PLZ
I
PHZ
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Control Pin Input Capacitance
Input/Output Capacitance
Conditions
Typ
3
Max
Unit
pF
C
V
V
= 5.0 V
IN
CC
C
= 5.0 V, OE = 0 V
5
pF
I/O
CC
8. T = )25_C, f = 1 MHz, Capacitance is characterized but not tested.
A
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4
FST3126
AC Loading and Waveforms
V
I
500 W
FROM
OUTPUT
UNDER
TEST
500 W
C *
L
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*C = 50 pF
L
Figure 3. AC Test Circuit
t = 2.5 nS
f
t = 2.5 nS
f
3.0 V
GND
90 %
1.5 V
90 %
1.5 V
SWITCH
INPUT
10 %
10 %
t
t
PLH
PLH
V
OH
OL
1.5 V
1.5 V
OUTPUT
V
Figure 4. Propagation Delays
t = 2.5 nS
f
t = 2.5 nS
f
3.0 V
90 %
1.5 V
90 %
1.5 V
ENABLE
INPUT
10 %
10 %
GND
t
t
PZL
PZL
OUTPUT
OUTPUT
1.5 V
V
+ 0.3 V
OL
V
OL
t
t
PZH
PHZL
V
OH
OH
V
− 0.3 V
1.5 V
Figure 5. Enable/Disable Delays
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5
FST3126
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
FST3126
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
−T−
H
G
DETAIL E
D
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
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FST3126/D
相关型号：
FST3126QSC
CBT/FST/QS/5C/B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO16, 0.150 INCH, MO-137, QSOP-16
ROCHESTER
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