FST32211G [FAIRCHILD]
40/48-Bit Bus Switch; 四十八分之四十零位总线开关
| 型号： | FST32211G |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 40/48-Bit Bus Switch |
| 文件： | 总6页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2001
Revised July 2002
FST32211
40/48-Bit Bus Switch
General Description
Features
I 4Ω switch connection between two ports
I Minimal propagation delay through the switch
I Low lCC
The Fairchild Switch FST32211 provides up to 48-bits of
high-speed CMOS TTL-compatible bus switching. The low
On Resistance of the switch allows inputs to be connected
to outputs without adding propagation delay or generating
additional ground bounce noise.
I Zero bounce in flow-through mode
I Control inputs compatible with TTL level
I Packaged in plastic Fine Pitch Ball Grid Array (FBGA)
The device can be organized as four 12-bit, two 24-bit, or
one 48-bit bus switch. When routed as a 40-bit bus switch,
the device can be organized as four 10-bit, two 20-bit or
one 40-bit bus switch. When OE1 is LOW, the switch is ON
and Port 1A is connected to Port 1B. When OE2 is LOW,
the switch is ON and Port 2A is connected to Port 2B.
When OE3 is LOW, the switch is ON and Port 3A is con-
nected to Port 3B. When OE4 is LOW, the switch is ON and
Port 4A is connected to Port 4B. When OE1, OE2, OE3, or
OE4 are HIGH, a high impedance state exists between the
A and B Ports.
Ordering Code:
Order Number
Package Number
Package Description
FST32211G
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Note 1)(Note 2)
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2002 Fairchild Semiconductor Corporation
DS500404
www.fairchildsemi.com
Connection Diagram
FBGA Pin Assignments
(40-Bit Routing)
1
2
3
4
5
6
A
B
C
D
E
F
1A2
1A4
1A6
1A8
1A1
1A3
1A5
1A7
NC
OE2
OE1
GND
GND
VCC
VCC
GND
GND
2B9
1B1
1B3
1B5
1B7
1B9
2B1
2B3
2B5
2B7
1B2
1B4
1B6
1B8
1B10
2B2
2B4
2B6
2B8
GND
GND
GND
VCC
VCC
VCC
GND
2A9
1A10 1A9
2A2
2A4
2A6
2A8
2A1
2A3
2A5
2A7
G
H
J
K
L
2A10 3A10
GND
GND
GND
VCC
VCC
GND
GND
GND
4A1
GND
GND
VCC
VCC
VCC
GND
GND
4B1
3B10 2B10
3A9
3A7
3A5
3A3
3A1
4A9
4A7
4A5
4A3
3A8
3A6
3A4
3A2
4A10
4A8
4A6
4A4
4A2
3B8
3B6
3B4
3B2
3B9
3B7
3B5
3B3
M
N
P
R
T
4B10 3B1
4B8
4B6
4B4
4B2
4B9
4B7
4B5
4B3
U
V
W
OE4
NC
(Top Thru View)
Pin Descriptions
Pin Name
OE3
Truth Tables
Description
Inputs
OE1
Inputs/Outputs
OE2
1A, 1B
2A, 2B
OE1, OE2, OE3, OE4
1A, 2A, 3A, 4A
Bus Switch Enables
Bus A
L
L
L
H
L
1A = 1B
2A = 2B
1A = 1B
Z
2A = 2B
Z
1B, 2B, 3B, 4B
Bus B
H
H
Z
Z
H
Inputs
OE3
Inputs/Outputs
OE4
3A, 3B
3A = 3B
3A = 3B
Z
4A, 4B
4A = 4B
Z
L
L
L
H
L
H
H
4A = 4B
Z
H
Z
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2
Connection Diagram
FBGA Pin Assignments
(48-Bit Routing)
1
2
3
4
5
6
A
B
C
D
E
F
1A2
1A4
1A6
1A1
1A3
1A5
NC
OE2
OE1
1B7
1B8
2B1
2B2
GND
GND
2B11
GND
GND
VCC
3B2
3B1
4B8
4B7
4B1
OE4
NC
1B1
1B3
1B5
1B9
1B11
2B3
2B5
2B7
2B9
1B2
1B4
1B6
1B10
1B12
2B4
2B6
2B8
2B10
1A7
GND
1A8
2A1
2A2
VCC
GND
2A11
1A10 1A9
1A12 1A11
2A4
2A6
2A8
2A3
2A5
2A7
G
H
J
2A10 2A9
K
L
2A12 3A12 GND
3B12 2B12
3B10 3B11
3A11
3A9
3A7
3A5
3A3
4A11
4A9
4A5
4A3
3A10 GND
M
N
P
R
T
3A8
3A6
3A4
GND
3A2
3B8
3B6
3B4
3B9
3B7
3B5
3A1
4A12 4A8
4A10 4A7
4B12 3B3
4B10 4B11
U
V
W
4A6
4A4
4A2
GND
4B6
4B4
4B2
4B9
4B5
4B3
4A1
(Top Thru View)
Pin Descriptions
Pin Name
OE3
Truth Tables
Description
Inputs
OE1
Inputs/Outputs
OE2
1A, 1B
2A, 2B
OE1, OE2, OE3, OE4
1A, 2A, 3A, 4A
Bus Switch Enables
Bus A
L
L
L
H
L
1A = 1B
2A = 2B
1A = 1B
Z
2A = 2B
Z
1B, 2B, 3B, 4B
Bus B
H
H
Z
Z
H
Inputs
OE3
Inputs/Outputs
OE4
3A, 3B
3A = 3B
3A = 3B
Z
4A, 4B
4A = 4B
Z
L
L
L
H
L
H
H
4A = 4B
Z
H
Z
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 6)
0.5V to +7.0V
Supply Voltage (VCC
)
DC Switch Voltage (VS) (Note 4)
−0.5V to +7.0V Power Supply Operating (VCC)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
DC Input Control Pin Voltage (VIN)(Note 5)
DC Input Diode Current (lIK) VIN < 0V
−0.5V to +7.0V Input Voltage (VIN
)
−50 mA
Output Voltage (VOUT
)
DC Output (IOUT
DC VCC/GND Current (ICC/IGND
Storage Temperature Range (TSTG
)
128 mA Input Rise and Fall Time (tr, tf)
)
+/− 100 mA
−65°C to +150 °C
Switch Control Input
Switch I/O
0 ns/V to 5 ns/V
0 ns/V to DC
)
Free Air Operating Temperature (TA)
-40 °C to +85 °C
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 4: VS is the voltage observed/applied at either A or B Ports across the
switch.
Note 5: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 6: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
TA = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 7)
VIK
Clamp Diode Voltage
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18 mA
VIH
VIL
II
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
2.0
0.8
1.0
10
1.0
7
V
µA
µA
µA
Ω
0 ≤ VIN ≤ 5.5V
0
VIN = 5.5V
IOZ
OFF-STATE Leakage Current
Switch On Resistance
(Note 8)
5.5
0 ≤ A, B ≤ VCC
RON
4.5
4
4
VIN = 0V, IIN = 64 mA
VIN = 0V, IIN = 30 mA
VIN = 2.4V, IIN = 15 mA
VIN = 2.4V, IIN = 15 mA
OE1 = OE2 = GND
VIN = VCC or GND, IOUT = 0
One Input at 3.4V
4.5
7
Ω
4.5
8
12
20
3
Ω
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
∆ ICC
5.5
2.5
mA
Other Inputs at VCC or GND
Note 7: Typical values are at VCC = 5.0V and TA= +25°C
Note 8: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
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4
AC Electrical Characteristics
TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω
Figure
Number
Symbol
Parameter
Units
Conditions
VCC = 4.5 – 5.5V
VCC = 4.0V
Min Max
Min
Max
t
PHL, tPLH
Propagation Delay Bus to Bus
(Note 9)
0.25
0.25
ns
ns
VI = OPEN
Figures
1, 2
tPZH, tPZL
Output Enable Time
1.5
1.5
6.0
7.0
6.5
VI = 7V for tPZL
Figures
1, 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
7.2
ns
Figures
1, 2
VI = OPEN for tPHZ
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 10)
Symbol
Parameter
Typ
Max
Units
Conditions
VCC = 5.0V
VCC, OE = 5.0V
CIN
Control Pin Input Capacitance
3
pF
CI/O
Input/Output Capacitance
6
pF
Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
5
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Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA114A
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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