FSD146MRBN [ONSEMI]
具有异常 OCP 功能的 650 V 集成电源开关，用于 26 W 离线反激式转换器;
| 型号： | FSD146MRBN |
| 厂家： | 
ONSEMI |
| 描述： | 具有异常 OCP 功能的 650 V 集成电源开关，用于 26 W 离线反激式转换器 开关 电源开关 转换器 |
| 文件： | 总18页 (文件大小：770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2011
FSD146MRBN
Green-Mode Fairchild Power Switch (FPS™)
Features
Description
The FSD146MRBN is an integrated Pulse Width
Modulation (PWM) controller and SenseFET designed
for offline Switch-Mode Power Supplies (SMPS) with
minimal external components. The PWM controller
includes an integrated fixed-frequency oscillator, Under-
Voltage Lockout (UVLO), Leading-Edge Blanking (LEB),
optimized gate driver, internal soft-start, temperature-
compensated precise current sources for loop
compensation, and self-protection circuitry. Compared
with a discrete MOSFET and PWM controller solution,
the FSD146MRBN can reduce total cost, component
count, size, and weight; while simultaneously increasing
efficiency, productivity, and system reliability. This
device provides a basic platform that is well suited for
cost-effective design of a flyback converter.
.
Advanced Soft Burst-Mode Operation for
Low Standby Power and Low Audible Noise
Random Frequency Fluctuation for Low EMI
Pulse-by-Pulse Current Limit
.
.
.
Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis, Output-Short
Protection (OSP), and Under-Voltage Lockout
(UVLO) with Hysteresis
.
.
.
.
.
Low Operating Current (0.4mA) in Burst Mode
Internal Startup Circuit
Internal High-Voltage SenseFET: 650V
Built-in Soft-Start: 15ms
Auto-Restart Mode
Applications
.
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
Output Power Table(2)
Operating
Package Junction
Temperature
Part
Number
CurrentRDS(ON) 230VAC ± 15%(3)
85-265VAC
Replaces
Device
Limit (Max.)
Open
Adapter(4)
Frame(5)
Open
Frame(5)
Adapter(4)
-40°C ~
+125°C
FSD146MRBN 8-DIP
1.50A
23W
35W
17W
26W FSFM260N
2.6
Notes:
1. Lead-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230VAC or 100/115VAC with voltage doubler.
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
Application Circuit
Figure 1. Typical Application Circuit
Internal Block Diagram
Figure 2. Internal Block Diagram
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
2
Pin Configuration
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
GND
Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, which provides the internal operating
current for both startup and steady-state operation.
2
3
VCC
FB
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
should be placed between this pin and GND. If the voltage of this pin reaches 7.0V, the
overload protection triggers, which shuts down the FPS™.
4
N.C.
No Connection
5, 6, 7, 8
Drain
SenseFET Drain. High-voltage power SenseFET drain connection.
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDS
Parameter
Min.
Max.
650
26
Unit
V
Drain Pin Voltage
VCC Pin Voltage
VCC
V
Feedback Pin Voltage
VFB
-0.3
10.0
3.4
V
IDM
Drain Current Pulsed
A
1.7
A
TC=25C
IDS
Continuous Switching Drain Current(6)
1.1
A
TC=100C
EAS
PD
Single Pulsed Avalanche Energy(7)
Total Power Dissipation (TC=25C)(8)
Maximum Junction Temperature
Operating Junction Temperature(9)
Storage Temperature
250
1.5
mJ
W
C
C
C
150
+125
+150
TJ
TSTG
-40
-55
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
5
2
Electrostatic
Discharge Capability
ESD
kV
Notes:
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX=0.73)
and junction temperature (see Figure 4).
7. L=45mH, starting TJ=25C.
8. Infinite cooling condition (refer to the SEMI G30-88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Impedance(10)
Junction-to-Lead Thermal Impedance(11)
Value
85
Unit
°C/W
°C/W
ΨJL
11
Notes:
10. JEDEC recommended environment, JESD51-2, and test board, JESD51-10, with minimum land pattern.
11. Measured on the SOURCE pin #7, close to the plastic interface.
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
TJ = 25C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
SenseFET Section
BVDSS
IDSS
RDS(ON)
CISS
COSS
tr
Drain-Source Breakdown Voltage
Zero-Gate-Voltage Drain Current
650
V
V
CC = 0V, ID = 250A
250
VDS = 650V, TA = 25C
A
Ω
Drain-Source On-State Resistance VGS=10V, ID =1A
2.1
436
65
2.6
Input Capacitance(12)
Output Capacitance(12)
Rise Time
VDS = 25V, VGS = 0V, f=1MHz
pF
pF
ns
ns
ns
VDS = 25V, VGS = 0V, f=1MHz
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID= 4A, RG=25Ω
24
tf
Fall Time
24
td(on)
td(off)
Turn-On Delay
Turn-Off Delay
13
30
ns
Control Section
fS
fS
Switching Frequency(12)
Switching Frequency Variation(12)
VCC = 14V, VFB = 4V
-25C < TJ < 125C
VCC = 14V, VFB = 4V
VCC = 14V, VFB = 0V
VFB = 0
61
61
67
±5
67
73
±10
73
kHz
%
DMAX
DMIN
IFB
Maximum Duty Ratio
%
Minimum Duty Ratio
0
%
Feedback Source Current
65
11
90
12
7.5
15
115
13
A
V
VSTART
VSTOP
tS/S
VFB = 0V, VCC Sweep
UVLO Threshold Voltage
Internal Soft-Start Time
After Turn-On, VFB = 0V
VSTR = 40V, VCC Sweep
7.0
8.0
V
ms
V
VRECOMM Recommended VCC Range
Burst-Mode Section
VBURH
13
23
0.45
0.30
0.50
0.35
150
0.55
0.40
V
V
VBURL
VHYS
Burst-Mode Voltage
VCC = 14V, VFB Sweep
mV
Protection Section
ILIM
VSD
Peak Drain Current Limit
1.35
6.45
1.2
1.50
7.00
2.0
1.65
7.55
2.8
A
V
di/dt = 300mA/s
Shutdown Feedback Voltage
Shutdown Delay Current
Leading-Edge Blanking Time(12,14)
Over-Voltage Protection
Threshold Time
VCC = 14V, VFB Sweep
VCC = 14V, VFB = 4V
IDELAY
tLEB
VOVP
tOSP
A
ns
V
300
24.5
1.0
VCC Sweep
23.0
0.7
26.0
1.3
s
V
OSP Triggered when
tON<tOSP & VFB>VOSP
(Lasts Longer than tOSP_FB
Output-Short
Threshold VFB
Protection(12)
VOSP
tOSP_FB
TSD
THYS
1.8
2.0
2.2
)
VFB Blanking Time
2.0
2.5
3.0
s
C
C
Shutdown Temperature
Hysteresis
125
135
60
145
Thermal Shutdown Temperature(12)
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
TJ = 25C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
Total Device Section
Operating Supply Current,
(Control Part in Burst Mode)
IOP
IOPS
VCC = 14V, VFB = 0V
VCC = 14V, VFB = 2V
0.3
1.1
0.4
1.5
120
0.5
1.9
mA
mA
A
Operating Switching Current,
(Control Part and SenseFET Part)
VCC=11V (Before VCC
ISTART
Start Current
85
155
1.3
Reaches VSTART
)
ICH
Startup Charging Current
VCC = VFB = 0V, VSTR = 40V
VCC = VFB = 0V, VSTR Sweep
0.7
1.0
26
mA
V
VSTR
Minimum VSTR Supply Voltage
Notes:
12. Although these parameters are guaranteed, they are not 100% tested in production.
13. Average value.
14. tLEB includes gate turn-on time.
Comparison of FSGM300N and FSD146MRBN
Function
FSGM300N
FSD146MRBN
Advantages of FSD146MRBN
Operating Current
1.5mA
0.4mA
Very low standby power
The difference of input power between the
low and high input voltage is quite small.
Power Balance
Long tCLD
Very Short TCLD
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
6
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 5. Operating Supply Current (IOP) vs. TA
Figure 6. Operating Switching Current (IOPS
vs. TA
)
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 7. Startup Charging Current (ICH) vs. TA
Figure 8. Peak Drain Current Limit (ILIM) vs. TA
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.60
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 9. Feedback Source Current (IFB) vs. TA
Figure 10. Shutdown Delay Current (IDELAY) vs. TA
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
7
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 11. UVLO Threshold Voltage (VSTART) vs. TA
Figure 12. UVLO Threshold Voltage (VSTOP) vs. TA
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 13. Shutdown Feedback Voltage (VSD
)
Figure 14. Over-Voltage Protection (VOVP) vs. TA
vs. TA
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Temperature [ °C]
Figure 15. Switching Frequency (fS) vs. TA
Figure 16. Maximum Duty Ratio (DMAX) vs. TA
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
8
Functional Description
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (CVcc) connected to the VCC pin, as
illustrated in Figure 17. When VCC reaches 12V, the
FSD146MRBN begins switching and the internal high-
voltage current source is disabled. The FSD146MRBN
continues normal switching operation and the power is
supplied from the auxiliary transformer winding unless
VCC goes below the stop voltage of 7.5V.
3. Feedback Control: This device employs current-
mode control, as shown in Figure 18. An opto-coupler
(such as the FOD817) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the RSENSE resistor makes it possible to
control the switching duty cycle. When the reference pin
voltage of the shunt regulator exceeds the internal
reference voltage of 2.5V, the opto-coupler LED current
increases, pulling down the feedback voltage and
reducing drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
3.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through
the SenseFET is limited by the inverting input of the
PWM comparator (VFB*), as shown in Figure 18.
Assuming that the 90μA current source flows only
through the internal resistor (3R + R =27kꢀ), the
cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (VFB) exceeds
2.5V, the maximum voltage of the cathode of D2 is
clamped at this voltage. Therefore, the peak value of
the current through the SenseFET is limited.
Figure 17. Startup Block
3.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the RSENSE
resistor leads to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
2. Soft-Start: The FSD146MRBN has an internal soft-
start circuit that increases PWM comparator inverting
input voltage, together with the SenseFET current,
slowly after it starts. The typical soft-start time is 15ms.
The pulse width to the power switching device is
progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors.
The voltage on the output capacitors is progressively
increased to smoothly establish the required output
voltage. This helps prevent transformer saturation and
reduces stress on the secondary diode during startup.
FSD146MRBN employs
a leading-edge blanking
(LEB) circuit. This circuit inhibits the PWM comparator
for tLEB (300ns) after the SenseFET is turned on.
Figure 18. Pulse Width Modulation Circuit
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
9
4. Protection Circuits: The FSD146MRBN has several
self-protective functions, such as Overload Protection
(OLP), Abnormal Over-Current Protection (AOCP),
Output-Short Protection (OSP), Over-Voltage Protection
(OVP), and Thermal Shutdown (TSD). All the
protections are implemented as auto-restart. Once the
fault condition is detected, switching is terminated and
the SenseFET remains off. This causes VCC to fall.
When VCC falls to the Under-Voltage Lockout (UVLO)
stop voltage of 7.5V, the protection is reset and the
startup circuit charges the VCC capacitor. When VCC
reaches the start voltage of 12.0V, the FSD146MRBN
resumes normal operation. If the fault condition is not
removed, the SenseFET remains off and VCC drops to
stop voltage again. In this manner, the auto-restart can
alternately enable and disable the switching of the
power SenseFET until the fault condition is eliminated.
Because these protection circuits are fully integrated
into the IC without external components, the reliability is
improved without increasing cost.
continues increasing until it reaches 7.0V, when the
switching operation is terminated, as shown in Figure
20. The delay for shutdown is the time required to
charge CFB from 2.5V to 7.0V with 2.0µA. A 25 ~
50ms delay is typical for most applications. This
protection is implemented in auto-restart mode.
Fault
occurs
Fault
removed
Power
on
Figure 20. Overload Protection
VDS
4.2 Abnormal Over-Current Protection (AOCP):
When the secondary rectifier diodes or the
transformer pins are shorted, a steep current with
extremely high di/dt can flow through the SenseFET
during the minimum turn-on time. Even though the
FSD146MRBN has overload protection, it is not
enough to protect the FSD146MRBN in that abnormal
case; since severe current stress is imposed on the
SenseFET until OLP is triggered. The FSD146MRBN
internal AOCP circuit is shown in Figure 21. When the
gate turn-on signal is applied to the power SenseFET,
the AOCP block is enabled and monitors the current
through the sensing resistor. The voltage across the
resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP
level, the set signal is applied to the S-R latch,
resulting in the shutdown of the SMPS.
VCC
12.0V
7.5V
t
Normal
operation
Fault
situation
Normal
operation
Figure 19. Auto-Restart Protection Waveforms
4.1 Overload Protection (OLP): Overload is defined
as the load current exceeding its normal level due to
an unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, in normal operation, the overload protection
circuit can be triggered during the load transition. To
avoid this undesired operation, the overload
protection circuit is designed to trigger only after a
specified time to determine whether it is a transient
situation or a true overload situation. Because of the
pulse-by-pulse current limit capability, the maximum
peak current through the SenseFET is limited and,
therefore, the maximum input power is restricted with
a given input voltage. If the output consumes more
than this maximum power, the output voltage (VOUT
)
decreases below the set voltage. This reduces the
current through the opto-coupler LED, which also
reduces the opto-coupler transistor current, thus
increasing the feedback voltage (VFB). If VFB exceeds
2.5V, D1 is blocked and the 2.0µA current source
starts to charge CFB slowly up. In this condition, VFB
Figure 21. Abnormal Over-Current Protection
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
10
4.3. Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can
flow through the SenseFET during the minimum turn-
on time. Such a steep current brings high-voltage
stress on the drain of the SenseFET when turned off.
OSP protects the device from this abnormal condition.
It is comprised of detecting VFB and SenseFET turn-
on time. When the VFB is higher than 2.0V and the
SenseFET turn-on time is lower than 1.0μs, this
condition is recognized as an abnormal error and
PWM switching shuts down until VCC reaches VSTART
again. An abnormal condition output short is shown in
Figure 22.
5. Soft Burst-Mode Operation: To minimize power
dissipation in Standby Mode, the FSD146MRBN enters
Burst-Mode operation. As the load decreases, the
feedback voltage decreases. As shown in Figure 23, the
device automatically enters Burst Mode when the
feedback voltage drops below VBURL (350mV). At this
point, switching stops and the output voltages start to
drop at a rate dependent on the standby current load.
This causes the feedback voltage to rise. Once it
passes VBURH (500mV), switching resumes. The
feedback voltage then falls and the process repeats.
Burst Mode alternately enables and disables switching
of the SenseFET, thereby reducing switching loss in
Standby Mode.
Figure 22. Output-Short Protection
4.4 Over-Voltage Protection (OVP): If the
secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor
becomes almost zero. Then VFB climbs up in a similar
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is triggered. Because more
energy than required is provided to the output, the
output voltage may exceed the rated voltage before
the overload protection is triggered, resulting in the
breakdown of the devices in the secondary side. To
prevent this situation, an OVP circuit is employed. In
general, the VCC is proportional to the output voltage
and the FSD146MRBN uses VCC instead of directly
monitoring the output voltage. If VCC exceeds 24.5V,
an OVP circuit is triggered, resulting in the termination
of the switching operation. To avoid undesired
activation of OVP during normal operation, VCC should
be designed to be below 24.5V.
Figure 23. Burst Mode Operation
6. Random Frequency Fluctuation (RFF): Fluctuating
switching frequency of an SMPS can reduce EMI by
spreading the energy over a wide frequency range. The
amount of EMI reduction is directly related to the
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by
external feedback voltage and internal free-running
oscillator at every switching instant. RFF effectively
scatters the EMI noise around typical switching
frequency (67kHz) and can reduce the cost of the input
filter used to meet EMI requirements (e.g. EN55022).
4.5 Thermal Shutdown (TSD): The SenseFET and
the control IC on a die in one package make it easier
for the control IC to detect the over temperature of the
SenseFET. If the temperature exceeds ~135C, the
thermal shutdown is triggered and stops operation.
The FSD146MRBN operates in auto-restart mode
until the temperature decreases to around 75C,
when normal operation resumes.
Figure 24. Random Frequency Fluctuation
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
11
Typical Application Circuit
Application
Input Voltage
Rated Output
Rated Power
5.0V(2A)
14.0V(1.2A)
LCD Monitor
Power Supply
85 ~ 265VAC
26.8W
Key Design Notes:
1. The delay for overload protection is designed to be about 30ms with C105 (8.2nF). OLP time between 39ms
(12nF) and 46ms (15nF) is recommended.
2. The SMD-type capacitor (C106) must be placed as close as possible to the VCC pin to avoid malfunction by
abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100nF and 220nF is
recommended.
Schematic
Figure 25. Schematic
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
12
Transformer
Figure 26. Schematic of Transformer
Winding Specification
Barrier Tape
Pin(S → F)
Wire
Turns
Winding Method
TOP
BOT
Ts
Np /2
3 → 2
0.25φ×1
22
Solenoid Winding
2.0mm
1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 7 → 6 0.4φ×2 (TIW)
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Na 4 → 5 0.2φ×1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 8 → 6 0.4φ×2 (TIW)
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N14V 10 → 8 0.4φ×2 (TIW)
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2 2 → 1 0.25φ×1
3
8
Solenoid Winding
Solenoid Winding
Solenoid Winding
Solenoid Winding
Solenoid Winding
3.0mm
1
1
1
1
1
4.0mm
3.0mm
3.0mm
2.0mm
2.0mm
3
5
22
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Electrical Characteristics
Pin
Specification
Remark
Inductance
Leakage
1－3
1－3
67kHz, 1V
826H ±6%
Short all other pins
15H Maximum
Core & Bobbin
.
.
Core: EER3016 (Ae=109.7mm2)
Bobbin: EER3016
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
13
Bill of Materials
Part #
Value
Note
Part #
Value
Note
Fuse
250V 2A
NTC
Capacitor
220nF/275V
150nF/275V
100F/400V
3.3nF/630V
F101
C101
C102
C103
C104
Box (Pilkor)
Box (Pilkor)
NTC101
5D-9
DSC
Electrolytic (SamYoung)
Film (Sehwa)
Resistor
1.5Mꢀ, J
43kꢀ, J
1.5kꢀ, F
1.0kꢀ, F
18kꢀ, F
8kꢀ, F
R101
R103
R201
R202
R203
R204
R205
1W
C105
C106
C107
C201
C202
C203
C204
C205
C301
15nF/100V
100nF
Film (Sehwa)
SMD (2012)
1W
1/4W, 1%
1/4W, 1%
1/4W, 1%
1/4W, 1%
1/4W, 1%
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Film (Sehwa)
47F/50V
820F/25V
820F/25V
2200F/10V
1000F/16V
47nF/100V
2.2nF/Y2
8kꢀ, F
Y-cap (Samhwa)
IC
Inductor
FPS
FSD146MRBN
KA431LZ
Fairchild
Fairchild
Fairchild
LF101
L201
L202
20mH
5H
Line filter 0.5Ø
5A Rating
IC201
IC301
FOD817B
5A Rating
5H
Diode
1N4007
UF4007
Transformer
D101
D102
Vishay
Vishay
T101
826H
ZD101
D201
1N4750
MBRF10H100
MBRF1060
G2SBA60
Vishay
Fairchild
Fairchild
Vishay
D202
BD101
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
14
Physical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 27. 8-Lead, MDIP, JEDEC MS-001, .300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any
manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
15
© 2011 Fairchild Semiconductor Corporation
FSD146MRBN • Rev. 1.0.0
www.fairchildsemi.com
16
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