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January 2014

FSD176MRT

Green-Mode Fairchild Power Switch (FPS™)

Features

Description

The FSD176MRT is an integrated Pulse Width

Modulation (PWM) controller and SenseFET specifically

designed for offline Switch-Mode Power Supplies

(SMPS) with minimal external components. The PWM

controller includes an integrated fixed-frequency

oscillator, Under-Voltage Lockout (UVLO), Leading-

Edge Blanking (LEB), optimized gate driver, internal

soft-start, temperature-compensated precise current

sources for loop compensation, and self-protection

circuitry. Compared with a discrete MOSFET and PWM

controller solution, the FSD176MRT can reduce total

cost, component count, size, and weight; while

simultaneously increasing efficiency, productivity, and

system reliability. This device provides a basic platform

for cost-effective design of a flyback converter.

. Advanced Soft Burst-Mode Operation for

Low Standby Power and Low Audible Noise

. Random Frequency Fluctuation for Low EMI

. Pulse-by-Pulse Current Limit

. Various Protection Functions: Overload Protection

(OLP), Over-Voltage Protection (OVP), Abnormal

Over-Current Protection (AOCP), Internal Thermal

Shutdown (TSD) with Hysteresis, Output-Short

Protection (OSP), and Under-Voltage Lockout (UVLO)

with Hysteresis

. Low Operating Current (0.4 mA) in Burst Mode

. Internal Startup Circuit

. Internal High-Voltage SenseFET: 650 V

. Built-in Soft-Start: 15 ms

. Auto-Restart Mode

Applications

. Power Supply for LCD Monitor, STB, and

DVD Combination

Ordering Information

Output Power Table⁽²⁾

Operating

Junction

Temperature

Current R_DS(ON)230 V_AC±15%⁽³⁾

85~265 V_AC

Replaces

Device

Part Number Package

Limit (Max.)

Open

Adapter⁽⁴⁾

Frame⁽⁵⁾

Open

Adapter⁽⁴⁾

Frame⁽⁵⁾

TO-220

FSD176MRTUDT 6-Lead⁽¹⁾

FSGM0765

R

-40°C ~ +125°C

3.50 A 1.6 Ω

80 W

80W

90 W

90W

48 W

70 W

U

U-

Forming

TO-220

6-Lead⁽¹⁾

L-

FSGM0765

R

FSD176MRTLDTU

-40°C ~ +125°C 3.50A

1.6Ω

48W

70 W

Forming

Notes:

1. Pb-free package per JEDEC J-STD-020B.

2. The junction temperature can limit the maximum output power.

3. 230 V_ACor 100 / 115 V_ACwith voltage doubler.

4. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.

5. Maximum practical continuous power in an open-frame design at 50°C ambient temperature.

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

Application Circuit

V_O

AC

IN

V_STR

Drain

GND

V_CC

FB

Figure 1. Typical Application Circuit

Internal Block Diagram

V_STR

V_CC

Drain

6

3

1

I_CH

V_burst

0.30V / 0.45V

V_ref

Soft Burst

V_CCGood

7.5V / 12V

Random

OSC

V_CC

V_ref

2.0µA

I_DELAY

90µA

I_FB

Soft Start

S

R

Q

PWM

Gate

Driver

FB

4

5

3R

R

LEB (300ns)

N.C.

t_ON<t_OSP(1.0μs)

LPF

2

GND

V_AOCP

V_OSP

S

R

Q

TSD

V_SD

7.0V

V_CCGood

Q

V_CC

V_OVP

24.5V

Figure 2. Internal Block Diagram

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

2

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Drain

GND

Description

1

2

SenseFET Drain. High-voltage power SenseFET drain connection.

Ground. This pin is the control ground and the SenseFET source.

Power Supply. This pin is the positive supply input, which provides the internal operating

current for both startup and steady-state operation.

3

V_CC

Feedback. This pin is internally connected to the inverting input of the PWM comparator.

The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor

should be placed between this pin and GND. If the voltage of this pin reaches 7 V, the

overload protection triggers, which shuts down the FPS.

4

5

6

FB

NC

No Connection

Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.

At startup, the internal high-voltage current source supplies internal bias and charges the

external capacitor connected to the V_CCpin. Once V_CCreaches 12 V, the internal current

source (I_CH) is disabled.

V_STR

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_STR

V_DS

Parameter

Min.

Max.

650

26

Unit

V

V_STRPin Voltage

Drain Pin Voltage

V_CCPin Voltage

V

V_CC

V

V_FB

Feedback Pin Voltage

Drain Current Pulsed

-0.3

12.0

12.8

6.4

V

I_DM

A

T_C=25°C

I_DS

Continuous Switching Drain Current⁽⁶⁾

4.0

A

T_C=100°C

E_AS

P_D

Single Pulsed Avalanche Energy⁽⁷⁾

Total Power Dissipation (T_C=25°C)⁽⁸⁾

Maximum Junction Temperature

Operating Junction Temperature⁽⁹⁾

Storage Temperature

390

50

mJ

W

°C

150

+125

T_J

-40

-55

T_STG

ESD

+150

4.5

°C

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

Electrostatic

Discharge Capability

kV

2.0

Notes:

6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D_MAX=0.74)

and junction temperature (see Figure 4. ).

7. L=45 mH, starting T_J=25°C.

8. Infinite cooling condition (refer to the SEMI G30-88).

9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.

Figure 4. Repetitive Peak Switching Current

Thermal Impedance

T_A=25°C unless otherwise specified.

Symbol

θ_JA

Parameter

Junction-to-Ambient Thermal Impedance⁽¹⁰⁾

Junction-to-Case Thermal Impedance⁽¹¹⁾

Value

63.5

2.5

Unit

°C/W

θ_JC

Notes:

10. Free standing without heat sink under natural convection condition, per JEDEC 51-2 and 1-10.

11. Infinite cooling condition per Mil Std. 883C method 1012.1.

www.fairchildsemi.com

FSD176MRT • Rev. 1.0.1

4

Electrical Characteristics

T_J= 25°C unless otherwise specified.

Symbol

Parameter

Conditions

Min. Typ. Max.

Unit

SenseFET Section

BV_DSS

I_DSS

Drain-Source Breakdown Voltage

Zero-Gate-Voltage Drain Current

Drain-Source On-State Resistance

650

V

μA

Ω

V_CC= 0 V, I_D= 250 μA

V_DS= 650 V, T_A= 25°C

V_GS=10 V, I_D=1A

250

R_DS(ON)

1.3

1.6

V_DS= 25 V, V_GS= 0 V,

f=1 MHz

C_ISS

C_OSS

t_r

Input Capacitance⁽¹²⁾

Output Capacitance⁽¹²⁾

Rise Time

674

pF

ns

V_DS= 25 V, V_GS= 0 V,

f=1 MHz

93

30

26

16

39

V_DS= 325 V, I_D= 4 A,

R_G=25 Ω

V_DS= 325 V, I_D= 4 A,

R_G=25 Ω

t_f

Fall Time

V_DS= 325 V, I_D= 4 A,

R_G=25 Ω

t_d(on)

t_d(off)

Turn-On Delay

Turn-Off Delay

V_DS= 325 V, I_D= 4 A,

R_G=25 Ω

Control Section

f_S

Δf_S

Switching Frequency⁽¹²⁾

Switching Frequency Variation⁽¹²⁾

V_CC= 14 V, V_FB= 4 V

-25°C < T_J< 125°C

V_CC= 14 V, V_FB= 4 V

V_CC= 14 V, V_FB= 0 V

V_FB=0 V

61

67

±5

67

73

±10

73

kHz

%

D_MAX

D_MIN

I_FB

Maximum Duty Ratio

%

Minimum Duty Ratio

%

Feedback Source Current

65

11

90

12

7.5

15

115

13

μA

V

V_START

V_STOP

t_S/S

V_FB= 0 V, V_CCSweep

After Turn-on, V_FB= 0 V

V_STR= 40 V, V_CCSweep

UVLO Threshold Voltage

Internal Soft-Start Time

7.0

8.0

V

ms

Burst-Mode Section

V_BURH

0.39

0.26

0.45

0.30

150

0.51

0.34

V

V_BURL

Burst-Mode Voltage

V_CC= 14 V, V_FBSweep

V_Hys

mV

Protection Section

I_LIM

V_SD

Peak Drain Current Limit

3.15

6.45

1.2

3.50

7.00

2.0

3.85

7.55

2.8

A

V

di/dt = 300 mA/μs

Shutdown Feedback Voltage

Shutdown Delay Current

Leading-Edge Blanking Time^(12)(14)

Over-Voltage Protection

Threshold Time

V_CC= 14 V, V_FBSweep

V_CC= 14 V, V_FB= 4 V

I_DELAY

t_LEB

V_OVP

t_OSP

μA

ns

V

300

24.5

1.0

V_CCSweep

23.0

0.7

26.0

1.3

μs

V

OSP Triggered when

Output-Short

Threshold V_FB

Protection⁽¹²⁾

V_OSP

t_{OSP_FB}

TSD

T_Hys

t

_ON<t_OSP& V_FB>V_OSP

1.8

2.0

2.2

(Lasts Longer than t_{OSP_FB}

)

V_FBBlanking Time

2.0

2.5

3.0

μs

°C

Shutdown Temperature

Hysteresis

130

140

60

150

Thermal Shutdown Temperature⁽¹²⁾

Continued on the following page…

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

5

Electrical Characteristics (Continued)

T_J= 25°C unless otherwise specified.

Symbol

Parameter

Conditions

Min. Typ. Max.

Unit

Total Device Section

Operating Supply Current,

(Control Part in Burst Mode)

I_OP

V

_CC= 14 V, V_FB= 0 V

0.3

1.1

0.4

1.5

0.5

1.9

mA

Operating Switching Current,

(Control Part and SenseFET Part)

I_OPS

V_CC= 14 V, V_FB= 2 V

V_CC=11 V (Before V_CC

I_START

I_CH

Start Current

85

120

1.0

26

155

1.3

μA

mA

V

Reaches V_START

)

Startup Charging Current

Minimum V_STRSupply Voltage

V_CC= V_FB= 0 V, V_STR= 40 V

0.7

V_CC= V_FB= 0 V, V_STR

Sweep

V_STR

Notes:

12. Although these parameters are guaranteed, they are not 100% tested in production.

13. Average value.

14. t_LEBincludes gate turn-on time.

Comparison of FSGM0765R and FSD176MRT

Function

FSGM0765R

FSD176MRT

Built-in

Advantages of FSD176MRT

Random Frequency Fluctuation

Operating Current

Low EMI

Very low standby power

1.6 mA

0.4 mA

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

6

Typical Performance Characteristics

Characteristic graphs are normalized at T_A=25°C.

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 5. Operating Supply Current (I_OP) vs. T_A

Figure 6. Operating Switching Current (I_OPS) vs. T_A

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 7. Startup Charging Current (I_CH) vs. T_A

Figure 8. Peak Drain Current Limit (I_LIM) vs. T_A

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.60

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 9. Feedback Source Current (I_FB) vs. T_A

Figure 10. Shutdown Delay Current (I_DELAY) vs. T_A

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

7

Typical Performance Characteristics

Characteristic graphs are normalized at T_A=25°C.

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 11. UVLO Threshold Voltage (V_START) vs. T_A

Figure 12. UVLO Threshold Voltage (V_STOP) vs. T_A

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 13. Shutdown Feedback Voltage (V_SD) vs. T_A

Figure 14. Over-Voltage Protection (V_OVP) vs. T_A

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 15. Switching Frequency (f_S) vs. T_A

Figure 16. Maximum Duty Ratio (D_MAX) vs. T_A

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

8

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (C_Vcc) connected to the V_CCpin, as

illustrated in Figure 17. When V_CCreaches 12 V, the

FSD176MRT begins switching and the internal high-

voltage current source is disabled. The FSD176MRT

continues normal switching operation and the power is

supplied from the auxiliary transformer winding unless

3. Feedback Control: This device employs current-

mode control, as shown in Figure 18. An opto-coupler

(such as the FOD817) and shunt regulator (such as the

KA431) are typically used to implement the feedback

network. Comparing the feedback voltage with the

voltage across the R_SENSEresistor makes it possible to

control the switching duty cycle. When the reference pin

voltage of the shunt regulator exceeds the internal

reference voltage of 2.5 V, the opto-coupler LED current

increases, pulling down the feedback voltage and

reducing drain current. This typically occurs when the

input voltage is increased or the output load is decreased.

V_CCgoes below the stop voltage of 7.5 V.

3.1 Pulse-by-Pulse Current Limit: Because current-

mode control is employed, the peak current through

the SenseFET is limited by the inverting input of the

PWM comparator (V_FB*), as shown in Figure 18.

Assuming that the 90 μA current source flows only

through the internal resistor (3R + R = 27 kꢀ), the

cathode voltage of diode D2 is about 2.5 V. Since D1

is blocked when the feedback voltage (V_FB) exceeds

2.5 V, the maximum voltage of the cathode of D2 is

clamped at this voltage. Therefore, the peak value of

the current through the SenseFET is limited.

Figure 17. Startup Block

3.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the R_SENSE

resistor leads to incorrect feedback operation in the

current-mode PWM control. To counter this effect, the

leading-edge blanking (LEB) circuit inhibits the PWM

comparator for t_LEB(300 ns) after the SenseFET is

turned on.

2. Soft-Start: The internal soft-start circuit increases the

PWM comparator inverting input voltage, together with

the SenseFET current, slowly after startup. The typical

soft-start time is 15ms. The pulse width to the power

switching device is progressively increased to establish

the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased to smoothly

establish the required output voltage. This helps prevent

transformer saturation and reduces stress on the

secondary diode during startup.

Figure 18. Pulse Width Modulation Circuit

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

9

charge C_FBslowly up_.In this condition, V_FBcontinues

increasing until it reaches 7.0 V, when the switching

operation is terminated, as shown in Figure 20. The

delay for shutdown is the time required to charge C_FB

from 2.5 V to 7.0 V with 2.0 µA. A 25 ~ 50 ms delay is

typical for most applications. This protection is

implemented in auto-restart mode.

4. Protection Circuits: The FSD176MRT has several

self-protective functions, such as Overload Protection

(OLP), Abnormal Over-Current Protection (AOCP),

Output-Short Protection (OSP), Over-Voltage Protection

(OVP), and Thermal Shutdown (TSD). All the

protections are implemented as auto-restart. Once a

fault condition is detected, switching is terminated and

the SenseFET remains off. This causes V_CCto fall.

When V_CCfalls to the Under-Voltage Lockout (UVLO)

stop voltage of 7.5 V, the protection is reset and the

startup circuit charges the V_CCcapacitor. When V_CC

reaches the start voltage of 12.0 V, the FSD176MRT

resumes normal operation. If the fault condition is not

removed, the SenseFET remains off and V_CCdrops to

stop voltage again. In this manner, the auto-restart can

alternately enable and disable the switching of the

power SenseFET until the fault condition is eliminated.

Because these protection circuits are fully integrated

into the IC without external components, the reliability is

improved without increasing cost.

Figure 20. Overload Protection

4.2 Abnormal Over-Current Protection (AOCP):

When the secondary rectifier diodes or the

transformer pins are shorted, a steep current with

extremely high di/dt can flow through the SenseFET

during the minimum turn-on time. Overload protection

is not enough to protect the FSD176MRT in that

abnormal case; since severe current stress is

imposed on the SenseFET until OLP is triggered. The

FSD176MRT internal AOCP circuit is shown in Figure

21. When the gate turn-on signal is applied to the

power SenseFET, the AOCP block is enabled and

monitors the current through the sensing resistor. The

voltage across the resistor is compared with a preset

AOCP level. If the sensing resistor voltage is greater

than the AOCP level, the set signal is applied to the

S-R latch, resulting in the shutdown of the SMPS.

Figure 19. Auto-Restart Protection Waveforms

4.1 Overload Protection (OLP): Overload is defined

as the load current exceeding its normal level due to

an unexpected abnormal event. In this situation, the

protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in normal

operation, the overload protection circuit can be

triggered during load transition. To avoid this

undesired operation, the overload protection circuit is

designed to trigger only after a specified time to

determine whether it is a transient situation or a true

overload situation. Because of the pulse-by-pulse

current limit capability, the maximum peak current

through the SenseFET is limited and, therefore, the

maximum input power is restricted with a given input

voltage. If the output consumes more than this

maximum power, the output voltage (V_OUT) decreases

below the set voltage. This reduces the current

through the opto-coupler LED, which also reduces the

opto-coupler transistor current, thus increasing the

feedback voltage (V_FB). If V_FBexceeds 2.5 V, D1 is

blocked and the 2.0 µA current source starts to

Figure 21. Abnormal Over-Current Protection

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

10

4.3. Output-Short Protection (OSP): If the output is

shorted, steep current with extremely high di/dt can

flow through the SenseFET during the minimum turn-

on time. Such a steep current brings high-voltage

stress on the drain of the SenseFET when turned off.

To protect the device from this abnormal condition,

OSP is included. It is comprised of detecting V_FBand

SenseFET turn-on time. When the V_FBis higher than

2.0 V and the SenseFET turn-on time is lower than

1.0 μs, the FSD176MRT recognizes this condition as

an abnormal error and shuts down PWM switching

until V_CCreaches V_STARTagain. An abnormal condition

output short is shown in Figure 22.

5. Soft Burst-Mode Operation: To minimize power

dissipation in Standby Mode, the FSD176MRT enters

Burst-Mode operation. As the load decreases, the

feedback voltage decreases. The device automatically

enters Burst Mode when the feedback voltage drops

below V_BURL(300 mV), as shown in Figure 23. At this

point, switching stops and the output voltages start to

drop at a rate dependent on standby current load. This

causes the feedback voltage to rise. Once it passes

V_BURH(450 mV), switching resumes. The feedback

voltage then falls and the process repeats. Burst Mode

alternately enables and disables switching of the

SenseFET, reducing switching loss in Standby Mode.

Figure 22. Output-Short Protection

4.4 Over-Voltage Protection (OVP): If the

secondary-side feedback circuit malfunctions or a

solder defect causes an opening in the feedback path,

the current through the opto-coupler transistor

becomes almost zero. Then V_FBclimbs up in a similar

manner to the overload situation, forcing the preset

maximum current to be supplied to the SMPS until the

overload protection is triggered. Because more energy

than required is provided to the output, the output

voltage may exceed the rated voltage before the

overload protection is triggered, resulting in the

breakdown of the devices in the secondary side. To

prevent this situation, an OVP circuit is employed. In

general, the V_CCis proportional to the output voltage

and the FSD176MRT uses V_CCinstead of directly

monitoring the output voltage. If V_CCexceeds 24.5 V,

an OVP circuit is triggered, resulting in the termination

of the switching operation. To avoid undesired

activation of OVP during normal operation, V_CCshould

be designed to be below 24.5 V.

Figure 23. Burst-Mode Operation

6. Random Frequency Fluctuation (RFF): Fluctuating

switching frequency of an SMPS can reduce EMI by

spreading the energy over a wide frequency range. The

amount of EMI reduction is directly related to the

switching frequency variation, which is limited internally.

The switching frequency is determined randomly by

external feedback voltage and an internal free-running

oscillator at every switching instant. This random

frequency fluctuation scatters the EMI noise around

typical switching frequency (67 kHz) effectively and can

reduce the cost of the input filter included to meet the

EMI requirements (e.g. EN55022).

4.5 Thermal Shutdown (TSD): The SenseFET and

the control IC on a die in one package makes it easier

for the control IC to detect the over temperature of the

SenseFET. If the temperature exceeds ~140°C, the

thermal shutdown is triggered and stops operation.

The FSD176MRT operates in auto-restart mode until

the temperature decreases to around 75°C, when

normal operation resumes.

Figure 24. Random Frequency Fluctuation

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

11

Typical Application Circuit

Application

LCD Monitor

Power Supply

Input Voltage

Rated Output

5.0 V (3 A)

Rated Power

85 ~ 265 V_AC

64 W

14.0 V (3.5 A)

Key Design Notes:

1. The delay for overload protection is designed to be about 30 ms with C105 (8.2 nF). OLP time between 39 ms

(12 nF) and 46 ms (15 nF) is recommended.

2. The SMD-type capacitor (C106) must be placed as close as possible to the V_CCpin to avoid malfunction by

abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100 nF and 220 nF

is recommended.

Figure 25. Schematic

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

12

Transformer Specification

.

Core: EER3019 (A_e=134 mm²)

.

Bobbin: EER3019

Figure 26. Transformer Specification

Table 1. Winding specification

Barrier Tape

Pin(S → F)

Wire

Turns Winding Method

TOP

BOT

Ts

N_p/2(BOT)

3 → 2

0.4φ×1

18

3

Solenoid Winding

2.0 mm

1

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

N_5V7 → 6 0.4φ×3 (TIW)

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

N_a4 → 5 0.20φ×1

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

N_5V8 → 6 0.4φ×3 (TIW)

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

N_14V10 → 8 0.4φ×3 (TIW)

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

N_p/2(TOP) 2 → 1 0.4φ×1

3.0 mm

1

8

4.0 mm 3.0 mm

3.0 mm

3

5

18

2.0 mm

Insulation: Polyester Tape t = 0.025 mm, 2 Layers

Table 2. Electrical Characteristics

Specification

465 μH ±6%

Remark

Inductance

Leakage

1－3

67 kHz, 1 V

Short all other pins

10 μH Maximum

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

13

Table 3. Bill of Materials

Part #

Value

250 V 3.15 A

5D-11

Note

Part #

Value

Capacitor

Note

Fuse

NTC

F101

C101

C102

C103

C104

220 nF / 275 V

150 nF / 275 V

Box (Pilkor)

NTC101

DSC

120 µF / 400 V Electrolytic (SamYoung)

3.3 nF / 630 V

Film (Sehwa)

Resistor

R101

R103

R201

R202

R203

R204

R205

1.5 Mꢀ, J

43 kꢀ, J

1 kꢀ, F

1 W

C105

C106

C107

C201

C202

C203

C204

C205

C206

C207

C208

C301

12 nF / 100 V

220 nF

Film (Sehwa)

SMD (2012)

1 W

1/4 W, 1%

47 µF / 50 V

Electrolytic (SamYoung)

1.2 kꢀ, F

18 kꢀ, F

8 kꢀ, F

1000 µF / 25 V Electrolytic (SamYoung)

2200 µF / 10 V Electrolytic (SamYoung)

1000 µF / 16 V Electrolytic (SamYoung)

8 kꢀ, F

100 nF

SMD (2012)

IC

SMPS

IC201

IC301

FSD176MRT

KA431LZ

Fairchild Semiconductor

4.7 nF / Y2

Y-Cap (Samhwa)

Inductor

FOD817B

LF101

L201

L202

20 mH

5 µH

Line Filter 0.5Ø

5 A Rating

Diode

D101

D102

1N4007

UF4004

Vishay

5 µH

5 A Rating

Transformer

ZD101

D201

1N4750

Vishay

T101

465 µH

MBR20150CT

FYPF2006DN

G3SBA60

Fairchild Semiconductor

Vishay

D202

BD101

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

14

Physical Dimensions

2.74

2.34

(0.70)

10.36

9.96

B

A

6.88

6.48

C

5.18

4.98

3.40

3.20

3.28

Ø

3.08

16.08

15.68

(17.83)

(21.01)

(1.13)

R1.00

#2,4,6

R1.00

0.85

1.30

1.05

5PLCS

6PLCS

0.75

0.65

0.55

#1

2.19

#6

4.90

4.70

#1,3,5

6PLCS

0.61

0.46

3.18

A B

1.75

0.05 C

1.27

0.20

3.81

5°

NOTES:

A) NO PACKAGE STANDARD APPLIES.

B) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

C) DIMENSIONS ARE IN MILLIMETERS.

D) DRAWING FILENAME : MKT-TO220E06REV2

4.80

4.40

Figure 27. 6-Lead, TO220, Fullpack, Formed

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/TO/TO220E06.pdf.

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

15

Physical Dimensions

10.36

9.96

B

2.74

2.34

(7.00)

(0.70)

A

3.28

Ø

5.18

4.98

3.40

3.20

3.08

(5.40)

6.88

6.48

16.07

15.67

19.97 18.94

18.97 17.94

13.05

(0.48)

24.00

23.00

R0.55

(0.88)

8.13

1.40

0.80

0.70

7.15

5PLCS

3.06

2.46

7.13

1.20

#1

#6

#1,6

#2,4

#3,5

0.70

0.50

5PLCS

0.20

0.60

0.45

2.19

1.75

3.48

2.88

1.27

A B

(3.81)

3.81

7.29

6.69

NOTES:

A) NO PACKAGE STANDARD APPLIES.

B) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

C) DIMENSIONS ARE IN MILLIMETERS.

4.80

4.40

5°

D) DRAWING FILENAME : MKT-TO220F06REV2

Figure 28. 6-Lead, TO220, Fullpack, U-Forming, 2 DAP

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/TO/TO220F06.pdf.

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

16

FSD176MRT • Rev. 1.0.1

www.fairchildsemi.com

17

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1


型号：	FSD176MRTUDTU
厂家：	ONSEMI
描述：	650V 集成电源开关，带异常 OCP，用于 70W 离线反激转换器开关电源开关转换器
文件：	总19页 (文件大小：828K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FSD176MRTUDTU [ONSEMI]

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