FODM611 [ONSEMI]

高抗噪能力、5V、10Mbit/sec逻辑门输出(开路集电极)光电耦合器;
FODM611
型号: FODM611
厂家: ONSEMI    ONSEMI
描述:

高抗噪能力、5V、10Mbit/sec逻辑门输出(开路集电极)光电耦合器

光电
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May 2010  
FODM611  
High Noise Immunity, 5V, 10Mbit/sec Logic Gate Output  
(Open Collector) Optocoupler  
Features  
Description  
High Noise Immunity characterized by common mode  
The FODM611 is a 5V high-speed logic gate output  
(open collector) optocoupler, which supports isolated  
communications allowing digital signals to communicate  
between systems without conducting ground loops or  
hazardous voltages. It utilizes Fairchild’s proprietary  
transient immunity (CMTi)  
– 20kV/µs Minimum CMTi  
High Speed  
– 10Mbit/sec Date Rate (NRZ)  
– 100ns max. Propagation Delay  
– 35ns max. Pulse Width Distortion  
– 40ns max. Propagation Delay Skew  
-40 to +85°C temperature range  
Safety and regulatory approvals  
®
coplanar packaging technology, Optoplanar , and  
optimized IC design to achieve high noise immunity,  
characterized by high common mode transient immunity  
specifications.  
This optocoupler consists of an AlGaAS LED at the  
input, optically coupled to a high speed integrated photo-  
detector logic gate. The output of the detector IC is an  
open collector schottky-clamped transistor. The coupled  
parameters are guaranteed over the wide temperature  
range of -40°C to +85°C. A maximum input signal of  
5mA will provide a minimum output sink current of 13mA  
(fan out of 8).  
– UL1577, 3750 VAC  
for 1 min.  
RMS  
– IEC60747-5-2 (pending approval)  
Applications  
Microprocessor system interface  
2
– SPI, I C  
Related Resources  
www.fairchildsemi.com/products/opto/  
Industrial fieldbus communications  
– DeviceNet, CAN, RS485  
Programmable logic control  
Isolated data acquisition system  
Voltage level translator  
www.fairchildsemi.com/pf/FO/FODM8061.html  
www.fairchildsemi.com/pf/FO/FODM8071.html  
Isolating MOSFET/IGBT gate drivers  
Functional Schematic  
Truth Table  
V
V
ANODE 1  
6
5
CC  
O
LED  
Off  
Output  
High  
On  
Low  
CATHODE  
GND  
3
4
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
Pin Definitions  
Number  
Name  
ANODE  
CATHODE  
GND  
Function Description  
1
3
4
5
6
Anode  
Cathode  
Output Ground  
Output Voltage  
Output Supply Voltage  
V
O
V
CC  
Safety and Insulation Ratings for Mini-Flat Package (SO5 Pin)  
As per IEC60747-5-2 (Pending Certification). This optocoupler is suitable for “safe electrical insulation” only within the  
safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.  
Symbol  
Parameter  
Installation Classifications per DIN VDE 0110/1.89 Table 1  
For rated main voltage < 150Vrms  
For rated main voltage < 300Vrms  
Climatic Classification  
Min.  
Typ.  
Max.  
Unit  
I-IV  
I-III  
40/85/21  
2
Pollution Degree (DIN VDE 0110/1.89)  
Comparative Tracking Index  
CTI  
175  
V
Input to Output Test Voltage, Method b,  
1060  
PR  
VIORM x 1.875 = V , 100% Production Test with  
PR  
t
= 1 sec, Partial Discharge < 5 pC  
m
V
Input to Output Test Voltage, Method a,  
VIORM x 1.5 = V , Type and Sample Test with  
848  
PR  
PR  
t
= 60 sec, Partial Discharge < 5 pC  
m
V
Max Working Insulation Voltage  
Highest Allowable Over Voltage  
External Creepage  
565  
4000  
5.0  
V
V
IORM  
peak  
V
IOTM  
peak  
mm  
mm  
mm  
°C  
External Clearance  
5.0  
Insulation thickness  
0.5  
T
Safety Limit Values, Maximum Values allowed in the event  
of a failure, Case Temperature  
150  
Case  
9
R
Insulation Resistance at T , V = 500V  
10  
IO  
S
IO  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
2
Absolute Maximum Ratings (T =25ºC unless otherwise specified)  
A
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In  
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Value  
Units  
T
Storage Temperature  
-40 to +125  
-40 to +85  
ºC  
ºC  
ºC  
ºC  
STG  
T
Operating Temperature  
Junction Temperature  
OPR  
T
-40 to +125  
260 for 10sec  
J
T
Lead Solder Temperature  
SOL  
(Refer to Reflow Temperature Profile)  
I
Forward Current  
Reverse Voltage  
Supply Voltage  
50  
5.0  
mA  
V
F
V
R
V
0 to 7.0  
V
CC  
V
Output Voltage  
-0.5 to V +0.5  
V
O
CC  
I
Average Output Current  
50  
100  
85  
mA  
mW  
mW  
O
(1)(2)  
PD  
Input Power Dissipation  
I
(1)(2)  
PD  
Output Power Dissipation  
O
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
Parameter  
Ambient Operating Temperature  
Min.  
-40  
4.5  
0
Max.  
+85  
5.5  
0.8  
15  
Unit  
ºC  
T
A
(3)  
V
Supply Voltages  
V
CC  
V
Logic Low Input Voltage  
Logic High Input Current  
Logic Low Input Current  
V
FL  
I
6.3  
mA  
µA  
FH  
I
250  
5
FL  
N
Fan Out (at R = 1k)  
TTL Loads  
L
R
Output Pull-up Resistor  
330  
4k  
L
Isolation Characteristics (T =25ºC)  
A
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max. Units  
V
Input-Output Isolation Voltage  
freq= 60Hz, t = 1.0min,  
3750  
Vac  
RMS  
ISO  
(4)(5)  
I
10µA  
I-O  
(4)  
12  
R
C
Isolation Resistance  
Isolation Capacitance  
V
V
= 500V  
10  
ISO  
I-O  
I-O  
(4)  
= 0V, freq=1.0MHz  
0.6  
pF  
ISO  
Notes:  
1. No derate required to 85ºC.  
2. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected  
to conditions outside these ratings.  
3. 0.1µF bypass capacitor must be connected between pins 4 and 6.  
4. Device is considered a two terminal device: Pins 1 and 3 are shorted, and Pins 4, 5, and 6 are shorted together.  
5. 3,750 VAC  
for 1 minute duration is equivalent to 4,500 VAC  
for 1 second duration.  
RMS  
RMS  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
3
Electrical Characteristics (Apply over all recommended conditions)  
(T = -40ºC to +85ºC, 4.5V V 5.5V), unless otherwise specified.  
A
CC  
Typical value is measured at T = 25ºC and V = 5.0V.  
A
CC  
Symbol  
Parameter  
Test Conditions  
Min. Typ. Max. Units  
INPUT CHARACTERISTICS  
V
Forward Voltage  
I = 10mA, Fig. 1  
1.05  
5.0  
1.45  
3.4  
1.8  
5.0  
V
V
F
F
BV  
Input Reverse Breakdown Voltage  
Threshold Input Current  
I = 10µA  
R
R
I
V = 0.6V, I (sinking) = 13mA,  
mA  
FHL  
O
OL  
T < 85ºC, Fig. 2  
A
OUTPUT CHARACTERISTICS  
V
Logic LOW Output Voltage  
I = rated I ,  
FHL  
0.4  
0.6  
V
OL  
F
I
(sinking) = 13mA, Fig. 3  
OL  
I
Logic HIGH Output Current  
I = 250µA, V = 5.0V, Fig. 4  
2.1  
7.5  
30.0  
10.0  
µA  
OH  
F
O
I
Logic LOW Output Supply Current I = 10mA, V = 5.0V, Fig. 5, 7  
mA  
CCL  
CCH  
F
CC  
I
Logic HIGH Output Supply Current I = 0mA, V = 5.0V, Fig. 6, 7  
6.0  
9.0  
mA  
F
CC  
Switching Characteristics (Apply over all recommended conditions)  
(T = -40ºC to +85ºC, 4.5V V 5.5V, I = 7.5mA), unless otherwise specified.  
A
CC  
F
Typical value is measured at T = 25ºC and V = 5.0V  
A
CC  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
Mbps  
ns  
Date Rate  
R = 350Ω  
10  
L
t
Propagation Delay Time to Logic R = 350, C = 15pF,  
Low Output  
43  
50  
7
100  
PHL  
PLH  
L
L
Fig. 8 and 11  
t
Propagation Delay Time to Logic R = 350, C = 15pF,  
High Output  
100  
35  
ns  
ns  
L
L
Fig. 8 and 11  
PWD  
Pulse Width Distortion,  
R = 350, C = 15pF,  
L
L
| t  
– t  
|
Fig. 9  
PHL  
PLH  
(6)  
t
Propagation Delay Skew  
R = 350, C = 15pF  
40  
ns  
ns  
PSK  
L
L
t
Output Rise Time, (10% to 90%) R = 350, C = 15pF,  
20  
10  
40  
40  
R
L
L
Fig. 10 and 11  
t
Output Fall Time, (90% to 10%) R = 350, C = 15pF,  
ns  
F
L
L
Fig. 10 and 11  
|CM |  
Common Mode Transient  
Immunity at Output High  
V = 5.0V, V > 0.8 x V  
,
20  
20  
kV/µs  
kV/µs  
H
I
O
CC  
(7)  
V
= 1000V , Fig. 12  
CM  
|CM |  
Common Mode Transient  
Immunity at Output Low  
V = 0V, V < 0.8V,  
L
I
O
(7)  
V
= 1000V , Fig. 12  
CM  
Notes  
6. t  
is equal to the magnitude of the worst case difference in t  
and/or t  
that will be seen between any two units  
PSK  
PHL  
PLH  
from the same manufacturing date code that are operated at same case temperature ( 5°C), at same operating  
conditions, with equal loads (R = 350and C = 15pF), and with an input rise time less than 5ns.  
L
L
7. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of  
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity  
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to  
assure that the output will remain low.  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
4
Typical Performance Curves  
Fig. 2 Threshold Input Current vs Ambient Temperature  
Fig. 1 Input LED Current vs Forward Voltage  
6
5
4
3
2
1
100  
V
= 5.0V  
CC  
I
= 13mA  
OL  
10  
T
= 85°C  
A
1
0.1  
T
A
= -40°C  
T
A
= 25°C  
0.01  
0.001  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
2.0  
-40  
-20  
0
20  
40  
60  
80  
V
F
– FORWARD VOLTAGE (V)  
T
A
– AMBIENT TEMPERATURE (°C)  
Fig. 3 Low Level Output Voltage vs. Ambient Temperature  
Fig. 4 Logic High Output Current vs Ambient Temperature  
0.60  
2.0  
I
V
I
= 5mA  
= 5.0V  
I
= 250µA  
= 5.0V  
CC  
O
F
F
CC  
V
V
= 13mA  
= 3.3V  
OL  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.55  
0.50  
0.45  
0.40  
0.35  
-20  
0
20  
40  
60  
80  
-20  
0
20  
T – AMBIENT TEMPERATURE (°C)  
A
40  
60  
80  
-40  
-40  
T
A
– AMBIENT TEMPERATURE (°C)  
Fig. 5 Typical Logic Low Output Supply Current  
vs. Ambient Temperature  
Fig. 6 Typical Logic High Output Supply Current  
vs. Ambient Temperature  
10  
9
10  
8
I
V
= 10mA  
= 5.0V  
I
V
= 0mA  
= 5.0V  
F
F
CC  
CC  
8
6
7
4
6
2
5
4
-40  
0
-40  
-20  
0
20  
40  
60  
80  
-20  
0
20  
T – AMBIENT TEMPERATURE (°C)  
A
40  
60  
80  
T
A
– AMBIENT TEMPERATURE (°C)  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
5
Typical Performance Curves (Continued)  
Fig. 7 Typical Logic Output Supply Current  
Fig. 8 Typical Propagation Delay vs. Ambient Temperature  
vs. Output Supply Voltage  
10  
55  
I
T
= 0mA (for I  
CCH  
), 10mA (for I  
)
Frequency = 5MHz  
Duty Cycle = 50%  
F
A
CCL  
= 25°C  
I
V
R
= 7.5mA  
= 5.0V  
F
CC  
8
6
4
2
0
50  
45  
40  
35  
30  
= 350Ω  
L
I
I
CCL  
CCH  
t
PHL  
t
PLH  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
-40  
-20  
0
20  
T – AMBIENT TEMPERATURE (°C)  
A
40  
60  
80  
V
CC  
– OUTPUT SUPPLY VOLTAGE (V)  
Fig. 9 Pulse Width Distortion vs. Ambient Temperature  
Fig. 10 Rise and Fall Time vs. Ambient Temperature  
8
40  
35  
30  
25  
20  
15  
10  
5
Frequency = 5MHz  
Duty Cycle = 50%  
Frequency = 5MHz  
Duty Cycle = 50%  
I
F
= 7.5mA  
I = 7.5mA  
F
V
CC  
= 5V  
V
CC  
= 5V  
R
= 350Ω  
R
= 350Ω  
L
6
4
2
0
L
t
R
t
F
0
-40  
-20  
0
20  
40  
60  
80  
-20  
0
20  
40  
60  
80  
-40  
T
A
– AMBIENT TEMPERATURE (°C)  
T – AMBIENT TEMPERATURE (°C)  
A
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
6
Schematics  
I
F
Pulse Gen.  
5MHz  
t = tr = 5ns  
f
DC = 50%  
0.1µF  
Bypass  
350Ω  
V
Monitoring  
O
Node  
C
L
Input  
Monitoring  
Mode  
R
M
(I = 7.5mA)  
F
Input  
50%  
t
f
t
r
90%  
1.5V  
10%  
Output  
V
OL  
t
t
PLH  
PHL  
Figure 11.Test Circuit for Propagation Delay Time, Rise Time and Fall Time  
I
F
V
V
CC  
0.1µF  
Bypass  
350Ω  
Monitoring  
O
Node  
SW  
C
L
R
M
V
CM  
Pulse Gen  
1kV  
0V  
V
CM  
90%  
10%  
t
r
t
f
V
OH  
V
V
(I = 0mA)  
F
O
O
0.8 V  
CC  
0.8V  
(I = 7.5mA)  
F
V
OL  
Figure 12.Test Circuit for Instantaneous Common Mode Rejection Voltage  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
7
Package Dimensions  
LAND PATTERN RECOMMENDATION  
Notes:  
1. No standard applies to this package.  
2. All dimensions are in millimeters.  
3. Dimensions are exclusive of burrs, mold flash, and tie bar extrusion.  
4. Drawings filesname and revision: MKT-MFP05A.  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
8
Ordering Information  
Order Entry Identifier  
Option  
No Suffix  
R2  
(Example)  
Description  
FODM611  
Mini-Flat 5-pin, shipped in tubes (100 units per tube)  
Mini-Flat 5-pin, tape and reel (2,500 units per reel)  
FODM611R2  
All packages are lead free per JEDEC: J-STD-020B standard.  
Marking Information  
1
2
6
M611  
V X YY M  
5
3
4
Definitions  
1
2
3
4
5
6
Fairchild logo  
Device number  
IEC60747-5-2 (VDE marking)  
One digit year code, e.g., ‘9’  
Two digit work week ranging from ‘01’ to ‘53’  
Assembly package code  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
9
Tape and Reel Dimensions  
P
2
D0  
P
0
t
K0  
E
A0  
W
W1  
B0  
F
d
D1  
P
2.54 Pitch  
Description  
Symbol  
Dimensions (mm)  
12.00 +0.30/-0.10  
0.30 ±0.05  
Tape Width  
W
t
Tape Thickness  
Sprocket Hole Pitch  
Sprocket Hole Diameter  
Sprocket Hole Location  
Pocket Location  
P0  
D0  
E
4.00 ±0.10  
1.50 +0.10/-0.0  
1.75 ±0.10  
F
5.50 ±0.10  
P2  
P
2.00 ±0.10  
Pocket Pitch  
8.00 ±0.10  
Pocket Dimension  
A0  
B0  
K0  
D1  
W1  
d
4.40 ±0.10  
7.30 ±0.10  
2.30 ±0.10  
Pocket Hole Diameter  
Cover Tape Width  
1.50 Min.  
9.20  
Cover Tape Thickness  
0.065 ±0.010  
Max. Component Rotation or Tilt  
Devices Per Reel  
10° Max.  
2500  
Reel Diameter  
330mm (13")  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
10  
Reflow Profile  
Max. Ramp-up Rate = 3°C/S  
Max. Ramp-down Rate = 6°C/S  
T
P
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
t
P
T
L
Tsmax  
t
L
Preheat Area  
Tsmin  
t
s
60  
40  
20  
0
120  
Time 25°C to Peak  
240  
360  
Time (seconds)  
Profile Feature  
Pb-Free Assembly Profile  
150°C  
Temperature Min. (Tsmin)  
Temperature Max. (Tsmax)  
200°C  
Time (t ) from (Tsmin to Tsmax)  
60–120 seconds  
3°C/second max.  
217°C  
S
Ramp-up Rate (t to t )  
L
P
Liquidous Temperature (T )  
L
Time (t ) Maintained Above (T )  
60–150 seconds  
260°C +0°C / –5°C  
30 seconds  
L
L
Peak Body Package Temperature  
Time (t ) within 5°C of 260°C  
P
Ramp-down Rate (T to T )  
6°C/second max.  
8 minutes max.  
P
L
Time 25°C to Peak Temperature  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
11  
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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.  
The datasheet is for reference information only.  
Rev. I76  
©2009 Fairchild Semiconductor Corporation  
FODM611 Rev. 1.0.3  
www.fairchildsemi.com  
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