FDWS9509L-F085 [ONSEMI]
P 沟道,逻辑电平,Power Trench® MOSFET,-40V,-65A,8mΩ;型号: | FDWS9509L-F085 |
厂家: | ONSEMI |
描述: | P 沟道,逻辑电平,Power Trench® MOSFET,-40V,-65A,8mΩ |
文件: | 总7页 (文件大小:361K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – P-Channel,
Logic Level, POWERTRENCH)
V
R
MAX
I MAX
D
DSS
DS(ON)
−40 V
8.0 mW @ −10 V
−65 A
-40 V, -65 A, 8.0 mW
D
FDWS9509L-F085
Features
G
• Typ R
• Typ Q
= 6.3 mW at V = −10 V; I = −65 A
GS D
DS(on)
= 48 nC at V = −10 V; I = −65 A
g(tot)
GS
D
S
• UIS Capability
P−Channel MOSFET
• Wettable Flanks for Automatic Optical Inspection (AOI)
• AEC−Q101 Qualified and PPAP Capable
Bottom
Top
D
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
D
D
D
Compliant
G
Applications
S
S
S
Pin 1
• Automotive Engine Control
• PowerTrain Management
• Solenoid and Motor Drivers
• Electronic Steering
• Integrated Starter/Alternator
• Distributed Power Architectures and VRM
• Primary Switch for 12 V Systems
DFNW8
CASE 507AU
MARKING DIAGRAM
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
ON
AYWWWL
FDWS
9509L
Parameter
Drain−to−Source Voltage
Symbol
Value
−40
16
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain Current
GS
T
T
= 25°C
= 25°C
I
D
−65
A
C
(V = 10 V) (Note 1)
A
Y
= Assembly Location
= Year
Pulsed Drain Current
See
Figure 4
C
WW
WL
= Work Week
= Assembly Lot
Single Pulse Avalanche Energy (Note 2)
Power Dissipation
E
84
mJ
W
AS
FDWS9509L = Specific Device Code
P
107
0.71
D
Derate above 25°C
W/°C
°C
ORDERING INFORMATION
Operating and Storage Temperature
T , T
−55 to
+175
J
STG
†
Device
Package
Shipping
Thermal Resistance (Junction−to−Case)
R
1.4
50
°C/W
°C/W
DFNW8
(Power 56)
(Pb−Free)
q
JC
JA
FDWS9509L−F085
3000 /
Tape & Reel
Maximum Thermal Resistance
(Junction−to−Ambient) (Note 3)
R
q
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Current is limited by wirebond configuration.
2. Starting Tj = 25°C, L = 50 mH, I = 56 A, V = −40 V during inductor charging
AS
DD
and V = 0 V during time in avalanche.
DD
3. R
is the sum of the junction−to−case and case−to−ambient thermal
q
JA
resistance where the case thermal reference is defined as the solder
mounting surface of the drain pins. R
is guaranteed by design while R
q
JA
q
JC
is determined by the user’s board design. The maximum rating presented
2
here is based on mounting on a 1 in pad of 2 oz copper.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
October, 2021 − Rev. 2
FDWS9509L−F085/D
FDWS9509L−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
B
Drain−to−Source Breakdown Voltage
Drain−to−Source Leakage Current
I
= −250 mA, V = 0 V
−40
−
−
−
−
−
−
1
V
VDSS
D
GS
I
V
V
= −40 V,
= 0 V
T = 25°C
J
mA
mA
nA
DSS
DS
GS
T = 175°C (Note 4)
J
−
1
I
Gate−to−Source Leakage Current
V
=
16 V
−
100
GSS
GS
ON CHARACTERISTICS
V
R
Gate−to−Source Threshold Voltage
Drain−to−Source On−Resistance
V
I
= V , I = −250 mA
−1
−
−1.7
10.7
6.3
−3
V
GS(th)
GS
DS
D
= −65 A, V = −4.5 V
15.3
8.0
mW
mW
DS(on)
D
GS
I
= −65 A
= −10 V
T = 25°C
−
D
J
V
GS
T = 175°C (Note 4)
J
−
10.6
13.0
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= −20 V, V = 0 V, f = 1 MHz
−
−
−
−
−
−
−
−
3360
1230
38
−
−
pF
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Gate Resistance
−
rss
R
V
GS
V
GS
V
GS
= 0.5 V, f = 1 MHz
21
−
W
g
Q
Total Gate Charge
= 0 to −10 V
= 0 to −2 V
V
= −20 V,
= −65 A
48
67
−
nC
g(tot)
DD
I
D
Q
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
7
g(th)
Q
12
−
gs
Q
6
−
gd
SWITCHING CHARACTERISTICS
t
Turn−On Time
Turn−On Delay
Rise Time
V
DD
V
GS
= −20 V, I = −65 A,
−
−
−
−
−
−
−
10
5
22
−
ns
on
D
= −10 V, R
= 6 W
GEN
t
d(on)
t
r
−
t
Turn−Off Delay
Fall Time
198
71
−
−
d(off)
t
f
−
t
Turn−Off Time
405
off
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
I
I
= −65 A, V = 0 V
−
−
−
−
1.0
0.9
57
−1.25
−1.2
80
V
SD
SD
GS
= −32.5 A, V = 0 V
SD
GS
t
Reverse Recovery Time
I = −65 A, dI /dt = 100 A/ms
F
ns
rr
SD
Q
Reverse Recovery Charge
45
67
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The maximum value is specified by design at T = 175°C. Product is not tested to this condition in production
J
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2
FDWS9509L−F085
TYPICAL CHARACTERISTICS
1.2
1.0
100
90
80
70
60
50
V
= −10 V
GS
0.8
0.6
0.4
Current Limited
by Package
40
30
20
10
0
0.2
0
0
25
50
75
100
125
150
175
125
T , CASE TEMPERATURE (°C)
25
50
75
100
150
175
T , CASE TEMPERATURE (°C)
C
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
1
D = 0.50
0.20
P
DM
0.10
0.05
0.02
0.01
t
1
t
2
0.1
DUTY CYCLE, D = t /t
1
2
x R
Single Pulse
Peak T = P
x Z
+ T
JC C
q
q
J
DM
JC
0.01
−5
−4
−3
−2
−1
10
10
10
10
10
1
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
V
GS
= −10 V
T
C
= 25°C
For temperatures above 25°C
derate peak current as follows:
175 * T
C
Ǹ
I + I
ƪ ƫ
25
150
100
10
Single Pulse
−5
−4
−3
−2
−1
10
10
10
10
10
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 4. Peak Current Capability
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3
FDWS9509L−F085
TYPICAL CHARACTERISTICS (continued)
1000
100
10
100
Starting T = 25°C
J
100 ms
10
Starting T = 150°C
J
Operation in this area may
be limited by R
1 ms
DS(on)
1
T
= 25°C
If R = 0
= (L)(I )/(1.3*Rated BV
C
10 ms
100 ms
T = Max Rated
J
t
− V
)
AV
AS
DSS
DD
Single Pulse
If R ≠ 0
= (L/R)In[(I *R)/(1.3*Rated BV
t
AV
− V ) +1]
AS
DSS
DD
0.1
1
100 200
0.1
1
10
0.001
0.01
0.1
1
10
100
1000
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
t , TIME IN AVALANCHE (ms)
AV
Figure 6. Unclamped Inductive Switching Capability
Figure 5. Forward Bias Safe Operating Area
(Note: Refer to onsemi Applications Notes AN7514 and
AN7515)
300
250
200
150
100
50
300
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
100
V
GS
= 0 V
V
DS
= −5 V
10
T = 175°C
J
T = 175°C
J
1
T = 25°C
J
T = 25°C
J
0.1
0.01
0.001
T = −55°C
J
T = −55°C
J
0
2
3
4
5
6
7
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
250
200
150
100
50
300
250
200
150
100
50
V
GS
= −10 V
250 ms Pulse Width
T = 175°C
J
250 ms Pulse Width
T = 25°C
−7 V
−7 V
−5 V
J
V
GS
= −10 V
−5 V
−4.5 V
−4.5 V
−4 V
−4 V
−3.5 V
−3.5 V
0
0
0
1
2
3
4
5
1
0
2
3
4
5
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 9. Saturation Characteristics
Figure 10. Saturation Characteristics
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4
FDWS9509L−F085
TYPICAL CHARACTERISTICS (continued)
60
50
40
30
20
10
0
1.7
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
I
D
= −65 A
I
D
= −65 A
V
GS
= −10 V
T = 175°C
J
T = 25°C
J
3
4
5
6
7
8
9
10
−75 −50 −25
0
25 50 75 100 125 150 175
−V , GATE TO SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. RDS(on) vs. Gate Voltage
Figure 12. Normalized RDS(on) vs. Junction
Temperature
1.8
1.5
1.2
0.9
0.6
1.25
1.00
0.75
0.50
0.25
I
= −5 mA
D
V
= V
DS
= −250 mA
GS
I
D
−80
−40
0
40
80
120
160
200
−80 −40
0
40
80
120
160 200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 14. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
10000
1000
100
10
8
I
D
= −65 A
C
iss
V
DD
= −16 V
V
DD
= −20 V
C
oss
6
V
DD
= −24 V
4
C
rss
2
0
f = 1 MHz
= 0 V
V
GS
10
0.1
0
10
20
30
50
40
1
10
150
Q , GATE CHARGE (nC)
g
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 16. Gate Charge vs. Gate to Source
Voltage
Figure 15. Capacitance vs. Drain to Source
Voltage
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5
FDWS9509L−F085
PACKAGE DIMENSIONS
DFNW8 5.2x6.3, 1.27P
CASE 507AU
ISSUE A
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6
FDWS9509L−F085
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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