FDS3992 [ONSEMI]
分立式商用N沟道PowerTrench MOSFET，100V，4.5A，0.062 Ohms @ VGS = 10V，SO-8封装;
| 型号： | FDS3992 |
| 厂家： | 
ONSEMI |
| 描述： | 分立式商用N沟道PowerTrench MOSFET，100V，4.5A，0.062 Ohms @ VGS = 10V，SO-8封装 PC 开关 光电二极管 晶体管 |
| 文件： | 总13页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2013
FDS3992
Dual N-Channel PowerTrench® MOSFET
100V, 4.5A, 62mΩ
Features
Applications
•
•
•
•
•
•
r
= 54mΩ (Typ.), V = 10V, I = 4.5A
D
• DC/DC converters and Off-Line UPS
DS(ON)
GS
Q (tot) = 11nC (Typ.), V = 10V
GS
g
•
•
•
•
•
•
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Direct Injection / Diesel Injection Systems
42V Automotive Load Control
Low Miller Charge
Low Q Body Diode
RR
Optimized efficiency at high frequencies
UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82745
Electronic Valve Train Systems
(1)
(2)
(8)
(7)
Branding Dash
5
1
(3)
(4)
(6)
(5)
2
3
4
SO-8
MOSFET Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Ratings
100
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
20
Drain Current
o
o
4.5
2.8
A
A
Continuous (T = 25 C, V = 10V, R
GS
= 50 C/W)
o
A
θJA
I
D
o
Continuous (T = 100 C, V = 10V, R
GS
= 50 C/W)
A
θJA
Pulsed
Figure 4
167
A
E
P
Single Pulse Avalanche Energy (Note 1)
Total Package Power Dissipation
mJ
W
AS
2.5
D
o
o
Derate above 25 C
20
mW/ C
o
T , T
J
Operating and Storage Temperature
-55 to 150
C
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)
Thermal Resistance, Junction to Case (Note 2)
50
85
25
C/W
θJA
θJA
θJC
o
C/W
o
C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
12mm
Quantity
FDS3992
FDS3992
SO-8
13’’
2500 units
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
GS
100
-
-
-
-
-
V
VDSS
D
V
V
V
= 80V
-
-
-
1
DS
GS
GS
I
µA
nA
DSS
GSS
o
= 0V
T
= 150 C
250
100
C
I
= 20V
On Characteristics
V
Gate to Source Threshold Voltage
V
I
= V , I = 250µA
DS
2
-
-
4
V
GS(TH)
GS
D
= 4.5A, V = 10V
GS
0.054 0.062
0.072 0.108
D
I
I
= 2A, V = 6V
GS
-
D
r
Drain to Source On Resistance
Ω
DS(ON)
= 4.5A, V = 10V,
GS
D
-
0.107 0.123
o
T
= 150 C
C
Dynamic Characteristics
C
C
C
Input Capacitance
-
-
-
-
-
-
-
-
750
118
27
-
-
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 25V, V = 0V,
GS
DS
f = 1MHz
Output Capacitance
OSS
RSS
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
-
Q
Q
Q
Q
Q
V
V
= 0V to 10V
11
15
1.9
-
g(TOT)
g(TH)
gs
GS
= 0V to 2V
1.4
3.5
2.1
2.8
GS
V
I
= 50V
DD
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
= 4.5A
D
I = 1.0mA
g
-
gs2
-
gd
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
47
-
ns
ns
ns
ns
ns
ns
ON
8
d(ON)
23
28
26
-
-
V
V
= 50V, I = 4.5A
D
= 10V, R = 27Ω
r
DD
Turn-Off Delay Time
Fall Time
-
GS
GS
d(OFF)
-
f
Turn-Off Time
81
OFF
Drain-Source Diode Characteristics
I
= 4.5A
= 2A
-
-
-
-
-
-
-
-
1.25
1.0
48
V
V
SD
V
Source to Drain Diode Voltage
SD
I
I
I
SD
SD
SD
t
Reverse Recovery Time
Reverse Recovery Charge
= 4.5A, dI /dt= 100A/µs
SD
ns
nC
rr
Q
= 4.5A, dI /dt= 100A/µs
SD
65
RR
Notes:
1:
2:
starting T = 25°C, L = 37mH, I = 3A. 100% test at L = 1mH, I = 10.3A.
AS
J AS
E
of 167mJ is based on
AS
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
θJA
drain pins.
R
is guaranteed by design while R
2
is determined by the user’s board design.
θCA
θJC
is measured with 1.0 in copper on FR-4 board
3:
R
θJA
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
V
= 10V
GS
0
25
50
75
100
125
150
25
50
75
, AMBIENT TEMPERATURE ( C)
A
100
125
150
o
o
T
T , AMBIENT TEMPERATURE ( C)
A
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
o
R
=50 C/W
0.2
0.1
θJA
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
x R
PEAK T = P
J
x Z
+ T
A
DM
θJA
θJA
0.001
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
200
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T = 25 C
A
FOR TEMPERATURES
o
100
10
1
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
C
I = I
25
V
= 10V
GS
125
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
Figure 4. Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Typical Characteristics T = 25°C unless otherwise noted
A
200
100
7
10µs
o
STARTING T = 25 C
J
10
1
o
STARTING T = 150 C
J
100µs
1
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10ms
100ms
0.1
0.01
SINGLE PULSE
= MAX RATED
If R = 0
= (L)(I )/(1.3*RATED BV
t
AV
- V
DD
)
T
AS
DSS
J
o
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
T
= 25 C
1s
C
t
- V ) +1]
DD
AV
AS
DSS
0.1
0.1
1
10
100
300
0.01
0.1
t
1
10
100
V
, DRAIN TO SOURCE VOLTAGE (V)
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
30
30
PULSE DURATION = 80µs
o
T
= 25 C
A
V
= 10V
DUTY CYCLE = 0.5% MAX
= 15V
GS
V
DD
25
20
15
10
5
25
20
15
10
5
V
= 7V
GS
o
V
= 6V
T
= 150 C
GS
J
o
T
= 25 C
J
V
= 5V
GS
o
T
= -55 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
0.5
1.0
1.5
, DRAIN TO SOURCE VOLTAGE (V)
2.0
V
, GATE TO SOURCE VOLTAGE (V)
V
GS
DS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
80
75
70
65
60
55
50
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 10V
GS
V
= 10V, I = 4.5A
D
GS
-80
-40
0
40
80
120
160
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
o
I , DRAIN CURRENT (A)
D
T , JUNCTION TEMPERATURE ( C)
J
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.0
0.8
0.6
1.2
1.1
1.0
0.9
V
= V , I = 250µA
DS D
I
= 250µA
GS
D
-80
-40
0
40
80
120
160
-80
-40
0
40
80
T , JUNCTION TEMPERATURE ( C)
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2000
10
C
= C + C
GS
V
= 50V
DD
ISS
GD
1000
100
10
8
6
4
2
0
C
≅ C + C
GD
OSS
DS
C
= C
RSS
GD
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 4.5A
= 2A
D
D
V
= 0V, f = 1MHz
1
GS
0.1
10
100
0
2
4
6
8
Q , GATE CHARGE (nC)
10
12
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
g
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
V
DD
V
GS
-
V
= 2V
DUT
GS
Q
gs2
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
maximum transient thermal impedance curve.
JM
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P , in an
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
DM
Therefore the application’s ambient
application.
temperature, T ( C), and thermal resistance R
o
o
( C/W)
θJA
is never exceeded.
A
must be reviewed to ensure that T
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
26
0.23 + Area
R
= 64 + -------------------------------
(EQ. 2)
θJA
(T – T )
= ------------------------------
JM
A
(EQ. 1)
P
DM
RθJA
The transient thermal impedance (Z ) is also effected by
θJA
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 64 + 26/(0.23+Area)
θJA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
100
50
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
0.001
0.01
0.1
1
10
2
AREA, TOP COPPER AREA (in )
Figure 21. Thermal Resistance vs Mounting
Pad Area
150
COPPER BOARD AREA - DESCENDING ORDER
0.04 in
2
2
0.28 in
120
2
0.52 in
2
0.76 in
2
90
60
30
0
1.00 in
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 22. Thermal Impedance vs Mounting Pad Area
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
PSPICE Electrical Model
rev Aug 2002
.SUBCKT FDS3992 2 1 3 ;
Ca 12 8 2.3e-10
Cb 15 14 3.5e-10
LDRAIN
Cin 6 8 7.47e-10
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
11
Ebreak 11 7 17 18 108
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
+
50
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
MWEAK
ESG
EVTHRES
+
+
16
21
-
19
8
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
18
22
It 8 17 1
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 5.61e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 25.e-3
Rgate 9 20 3.7
22
RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 20e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))}
.MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7
+ CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6)
.MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5)
.MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54)
.MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7)
.MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8)
.MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5)
.MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
SABER Electrical Model
REV Aug 2002
template FDS3992 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)
dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)
dp..model dplcapmod = (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0)
LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5)
c.ca n12 n8 = 2.3e-10
c.cb n15 n14 = 3.5e-10
c.cin n6 n8 = 7.47e-10
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DBREAK
11
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
+
16
21
-
spe.ebreak n11 n7 n17 n18 = 108
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1e-8
res.rdrain n50 n16 = 25e-3, tc1=1.15e-2,tc2=2.8e-5
res.rgate n9 n20 = 3.7
res.rslc1 n5 n51 = 1e-6, tc1=3.3e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 20e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5))
}
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
SPICE Thermal Model
REV Aug 2002
JUNCTION
th
FDS3992
Copper Area =1.0 in2
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
6
5
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
4
3
2
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
}
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in
3.2e-1
8.5e-1
0.3
0.28 in
0.52 in
0.76 in
1.0 in
3.5e-1
9.0e-1
1.8
4.0e-1
9.0e-1
2.0
4.0e-1
9.0e-1
2.0
4.0e-1
9.0e-1
2.0
24
18
12
10
9
36
21
18
16
15
53
37
30
28
23
©2004 Fairchild Semiconductor Corporation
FDS3992 Rev. C
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