FDMS2D5N08C [ONSEMI]

N 沟道,屏蔽门极,PowerTrench® MOSFET,80V,166A,2.7mΩ;
FDMS2D5N08C
型号: FDMS2D5N08C
厂家: ONSEMI    ONSEMI
描述:

N 沟道,屏蔽门极,PowerTrench® MOSFET,80V,166A,2.7mΩ

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www.onsemi.com  
FDMS2D5N08C  
N-Channel Shielded Gate PowerTrench® MOSFET  
80 V, 166 A, 2.7 mΩ  
Features  
General Description  
„ Shielded Gate MOSFET Technology  
This N-Channel MV MOSFET is produced using ON  
Semiconductor’s advanced PowerTrench® process that  
incorporates Shielded Gate technology. This process has been  
optimized to minimise on-state resistance and yet maintain  
superior switching performance with best in class soft body  
diode.  
„ Max rDS(on) = 2.7 mΩ at VGS = 10 V, ID = 68 A  
„ Max rDS(on) = 6.7 mΩ at VGS = 6 V, ID = 34 A  
„ 50% lower Qrr than other MOSFET suppliers  
„ Lowers switching noise/EMI  
Applications  
„ MSL1 robust package design  
„ Primary DC-DC MOSFET  
„ Synchronous Rectifier in DC-DC and AC-DC  
„ Motor Drive  
„ 100% UIL tested  
„ RoHS Compliant  
„ Solar  
Bottom  
Top  
Pin 1  
S
S
S
D
D
D
D
S
Pin 1  
S
G
S
D
D
D
G
D
Power 56  
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted  
Symbol  
VDS  
VGS  
Parameter  
Ratings  
80  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current -Continuous  
-Continuous  
V
V
±20  
TC = 25 °C  
C = 100 °C  
(Note 5)  
(Note 5)  
(Note 1a)  
(Note 4)  
(Note 3)  
166  
T
105  
ID  
A
-Continuous  
TA = 25 °C  
24  
-Pulsed  
823  
EAS  
Single Pulse Avalanche Energy  
Power Dissipation  
Power Dissipation  
600  
mJ  
W
TC = 25 °C  
TA = 25 °C  
138  
PD  
(Note 1a)  
2.7  
TJ, TSTG  
Operating and Storage Junction Temperature Range  
-55 to +150  
°C  
Thermal Characteristics  
RθJC  
RθJA  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
0.9  
45  
°C/W  
(Note 1a)  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
Reel Size  
13 ’’  
Tape Width  
12 mm  
Quantity  
FDMS2D5N08C  
FDMS2D5N08C  
Power 56  
3000 units  
Semiconductor Components Industries, LLC, 2017  
May, 2017, Rev. 1.1  
Publication Order Number:  
FDMS2D5N08C/D  
1
Electrical Characteristics TJ = 25 °C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
ID = 250 μA, VGS = 0 V  
80  
V
ΔBVDSS  
ΔTJ  
Breakdown Voltage Temperature  
Coefficient  
I
D = 250 μA, referenced to 25 °C  
62  
mV/°C  
IDSS  
IGSS  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
VDS = 64 V, VGS = 0 V  
VGS = ±20 V, VDS = 0 V  
1
μA  
100  
nA  
On Characteristics  
VGS(th)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 380 μA  
2.0  
2.9  
4.0  
V
ΔVGS(th)  
ΔTJ  
Gate to Source Threshold Voltage  
Temperature Coefficient  
I
D = 380 μA, referenced to 25 °C  
-8.3  
mV/°C  
V
GS = 10 V, ID = 68 A  
2.2  
3.3  
3.7  
148  
2.7  
6.7  
4.5  
rDS(on)  
gFS  
Static Drain to Source On Resistance  
Forward Transconductance  
VGS = 6 V, ID = 34 A  
mΩ  
VGS = 10 V, ID = 68 A, TJ = 125 °C  
VDS = 5 V, ID = 68 A  
S
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
4455  
1480  
59  
6240  
2070  
85  
pF  
pF  
pF  
Ω
VDS = 40 V, VGS = 0 V,  
f = 1 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
0.8  
1.6  
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
21  
11  
29  
7
34  
20  
47  
13  
84  
54  
ns  
ns  
VDD = 40 V, ID = 68 A,  
V
GS = 10 V, RGEN = 6 Ω  
Turn-Off Delay Time  
Fall Time  
ns  
ns  
Qg  
Total Gate Charge  
Total Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
Output Charge  
VGS = 0 V to 10 V  
VGS = 0 V to 6 V  
60  
38  
19  
12  
84  
51  
nC  
nC  
nC  
nC  
nC  
nC  
Qg  
VDD = 40 V,  
D = 68 A  
I
Qgs  
Qgd  
Qoss  
Qsync  
VDD = 40 V, VGS = 0 V  
VDS = 0 V, ID = 68 A  
Total Gate Charge Sync  
Drain-Source Diode Characteristics  
V
GS = 0 V, IS = 2.2 A  
(Note 2)  
(Note 2)  
0.7  
0.8  
30  
1.2  
1.3  
48  
VSD  
Source to Drain Diode Forward Voltage  
V
VGS = 0 V, IS = 68 A  
trr  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Time  
Reverse Recovery Charge  
ns  
nC  
ns  
IF = 34 A, di/dt = 300 A/μs  
Qrr  
trr  
55  
88  
24  
39  
IF = 34 A, di/dt = 1000 A/μs  
Qrr  
139  
222  
nC  
Notes:  
2
1. R  
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R  
is determined by the user's board design.  
θCA  
θJA  
a. 45 °C/W when mounted on a  
b. 115 °C/W when mounted on a  
minimum pad of 2 oz copper.  
2
1 in pad of 2 oz copper.  
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.  
3. E of 600 mJ is based on starting T = 25 °C; N-ch: L = 3 mH, I = 20 A, V = 80 V, V =10 V. 100% test at L = 0.1 mH, I = 63 A.  
AS  
J
AS  
DD  
GS  
AS  
4. Pulsed Id please refer to Fig 11 SOA graph for more details.  
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.  
www.onsemi.com  
2
Typical Characteristics TJ = 25 °C unless otherwise noted.  
300  
6
5
4
3
2
1
0
VGS = 10 V  
VGS = 7 V  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
VGS = 4.5 V  
250  
VGS = 6 V  
VGS = 5 V  
200  
VGS = 5.5 V  
VGS = 5.5 V  
150  
100  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
VGS = 6 V  
VGS = 5 V  
50  
0
VGS = 10 V  
VGS = 7 V  
VGS = 4.5 V  
2
0
1
3
4
5
0
50  
100  
150  
200  
250  
300  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
ID, DRAIN CURRENT (A)  
Figure 1. On Region Characteristics  
Figure2. N o r m a l i z e d O n - R e s i s ta n c e  
vs. Drain Current and Gate Voltage  
2.0  
20  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
ID = 68 A  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
VGS = 10 V  
ID = 68 A  
15  
10  
5
TJ = 125 o  
C
TJ = 25 o  
C
0
-75 -50 -25  
0
25 50 75 100 125 150  
4
5
6
7
8
9
10  
TJ, JUNCTION TEMPERATURE (oC)  
VGS, GATE TO SOURCE VOLTAGE (V)  
Figure 3. Normalized On Resistance  
vs. Junction Temperature  
Figure4. On-Resistance vs. Gate to  
Source Voltage  
300  
300  
VGS = 0 V  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
100  
250  
200  
150  
100  
50  
VDS = 5 V  
10  
TJ = 150 o  
C
1
TJ = 150 o  
C
TJ = 25 o  
C
0.1  
TJ = 25 o  
C
0.01  
0.001  
TJ = -55 o  
C
TJ = -55 o  
C
0
2
3
4
5
6
7
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
VGS, GATE TO SOURCE VOLTAGE (V)  
VSD, BODY DIODE FORWARD VOLTAGE (V)  
Figure 5. Transfer Characteristics  
Figure6. Source to Drain Diode  
Forward Voltage vs. Source Current  
www.onsemi.com  
3
Typical Characteristics TJ = 25 °C unless otherwise noted.  
10  
10000  
1000  
100  
10  
ID = 68 A  
Ciss  
VDD = 30 V  
8
Coss  
VDD = 40 V  
6
VDD = 50 V  
4
2
0
Crss  
f = 1 MHz  
GS = 0 V  
V
1
0
10  
20  
30  
40  
50  
60  
70  
0.1  
1
10  
80  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
Qg, GATE CHARGE (nC)  
Figure 7. Gate Charge Characteristics  
Figure8. C a p a c i t a n c e v s . D r a i n  
to Source Voltage  
100  
10  
1
180  
150  
120  
90  
RθJC = 0.9 oC/W  
VGS = 10 V  
TJ = 25 o  
C
TJ = 100 o  
C
60  
VGS = 6 V  
TJ = 125 o  
C
30  
0
0.001  
0.01  
0.1  
1
10  
100  
1000  
25  
50  
75  
100  
125  
150  
TC, CASE TEMPERATURE (oC)  
tAV, TIME IN AVALANCHE (ms)  
Figure9. U n c l a m p e d I n d u c t i v e  
Switching Capability  
Figure10. Maximum Continuous Drain  
Current vs. Case Temperature  
1000  
100000  
10000  
1000  
100  
SINGLE PULSE  
RθJC = 0.9 oC/W  
C = 25 oC  
10 μs  
T
100  
10  
1
100 μs  
THIS AREA IS  
LIMITED BY rDS(on)  
1 ms  
SINGLE PULSE  
TJ = MAX RATED  
RθJC = 0.9 oC/W  
10 ms  
CURVE BENT TO  
MEASURED DATA  
100 ms/DC  
T
C = 25 oC  
0.1  
0.1  
10  
10-5  
10-4  
10-3  
t, PULSE WIDTH (sec)  
10-2  
10-1  
1
1
10  
100 500  
VDS, DRAIN to SOURCE VOLTAGE (V)  
Figure 11. Forward Bias Safe  
Operating Area  
Figure 12. Single Pulse Maximum  
Power Dissipation  
www.onsemi.com  
4
Typical Characteristics TJ = 25 °C unless otherwise noted.  
2
DUTY CYCLE-DESCENDING ORDER  
1
D = 0.5  
0.2  
P
DM  
0.1  
0.1  
0.05  
0.02  
0.01  
t
1
t
2
NOTES:  
(t) = r(t) x R  
0.01  
SINGLE PULSE  
Z
θJC  
θJC  
o
R
= 0.9 C/W  
θJC  
Peak T = P  
x Z (t) + T  
J
DM  
θJC C  
Duty Cycle, D = t / t  
1
2
0.001  
10-5  
10-4  
10-3  
10-2  
10-1  
1
t, RECTANGULAR PULSE DURATION (sec)  
Figure 13. Junction-to-Case Transient Thermal Response Curve  
www.onsemi.com  
5
(4.42)  
3.81  
0.10 C  
5.00  
PKG  
A
2X  
8
7
6
5
C
L
B
8
5
(1.14)  
(3.49)  
KEEP OUT  
AREA  
(4.63)  
(6.61)  
C
PKG  
6.00  
L
(1.27)  
4X  
0.10 C  
1
3
2
4
1
4
PIN #1  
IDICATOR  
(0.61)  
TOP VIEW  
SIDE VIEW  
8X  
1.27  
2X  
(5.10)  
SEE  
DETAIL A  
LAND PATTERN  
RECOMMENDATION  
0.10 C  
1.10  
0.90  
0.08 C  
C
3.81  
1.27  
0.05  
0.00  
0.10  
0.05  
0.42±0.05 8X  
C A B  
(0.20)  
SEATING  
PLANE  
C
4X  
(0.38)  
SCALE: 2:1  
1
4
0.57±0.05  
4X  
NOTES: UNLESS OTHERWISE SPECIFIED  
A) PACKAGE STANDARD REFERENCE:  
JEDEC MO-240, ISSUE A, VAR. AA,  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE BURRS  
OR MOLD FLASH. MOLD FLASH OR  
BURRS DOES NOT EXCEED 0.10MM.  
D) DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M-2009.  
(0.35)  
2X  
6.00±0.10  
4.33±0.10  
0.65±0.10  
3X  
E) IT IS RECOMMENDED TO HAVE NO TRACES  
OR VIAS WITHIN THE KEEP OUT AREA.  
F) DRAWING FILE NAME: PQFN08TREV1.  
8
5
4.23±0.10  
5.00±0.10  
BOTTOM VIEW  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer  
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not  
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification  
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized  
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and  
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such  
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This  
literature is subject to all applicable copyright laws and is not for resale in any manner.  
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