FDMA507PZ [ONSEMI]
P 沟道，PowerTrench® MOSFET，-20V，-7.8A，24mΩ;
| 型号： | FDMA507PZ |
| 厂家： | 
ONSEMI |
| 描述： | P 沟道，PowerTrench® MOSFET，-20V，-7.8A，24mΩ 开关 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Single, P-Channel,
POWERTRENCH)
V
r
MAX
I
MAX
S1S2
S1S2(on)
S1S2
−20 V
24 mW @ −5 V
25 mW @ −4.5 V
35 mW @ −2.5 V
45 mW @ −1.8 V
−7.8 A
-20 V, -7.8 A, 24 mW
FDMA507PZ
General Description
This device is designed specifically for battery charge or load
switching in cellular handset and other ultraportable applications. It
features a MOSFET with low on−stade resistance.
The MicroFET t 2x2 package offers exceptional thermal
perfomance for its physical size and is well suited to linear mode
applications.
Pin 1
D
D
G
Source
Drain
Features
• Max r
• Max r
• Max r
• Max r
= 24 mW at V = −5 V, I = −7.8 A
GS D
DS(on)
DS(on)
D
D
S
= 25 mW at V = −4.5 V, I = −7 A
GS
D
Bottom View
) = 35 mW at V = −2.5 V, I = −5.5 A
DS(on
GS
D
WDFN6 2x2, 0.65P
(MicroFET 2x2)
CASE 511DB
= 45 mW at V = −1.8 V, I = −4 A
DS(on)
GS
D
• Low Profile − 0.8 mm Maximum − in the Package MicroFETt
2x2 mm
• HBM ESD Protection Level > 3.2 kV Typical (Note 3)
• Free from Halogenated Compounds and Antimony Oxides
• This Device is Pb−Free, Halide Free and is RoHS Compliant
MARKING DIAGRAM
&Z&2&K
507
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Ratings
Unit
V
V
−20
8
DS
GS
&Z = Assembly Plant Code
&2 = 2−Digit Date Code
V
V
I
D
A
&K = 2−Digits Lot Run Traceability Code
507 = Specific Device Code
−Continuous T = 25°C (Note 1a)
−7.8
−24
A
−Pulsed
P
D
Power Dissipation
W
T = 25°C (Note 1a)
2.4
0.9
A
PIN ASSIGNMENT
T = 25°C (Note 1b)
A
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
Bottom Drain Contact
J
STG
D
D
G
1
2
3
6
5
4
D
D
S
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Ratings
Unit
R
q
JA
Thermal Resistance, Junction to Ambient
(Note 1a)
52
°C/W
R
q
JA
Thermal Resistance, Junction to Ambient
(Note 1b)
145
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
April, 2023 − Rev. 3
FDMA507PZ/D
FDMA507PZ
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= −250 mA, V = 0 V
−20
−
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= −250 mA, referenced to 25°C
−12
mV/°C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= −16 V, V = 0 V
−
−
−
−
−1
10
mA
mA
DSS
GSS
DS
GS
I
= 8 V, V = 0 V
DS
GS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = −250 mA
−0.4
−
−0.5
3
−1.5
−
V
GS(th)
GS
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
= −250 mA, referenced to 25°C
mV/°C
DVGS(th)
DTJ
D
r
Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
GS
V
GS
V
DS
= −5 V, I = −7.8 A
−
−
−
−
−
−
19
20
24
29
26
33
24
25
35
45
34
−
mW
DS(on)
D
= −4.5 V, I = −7 A
D
= −2.5 V, I = −5.5 A
D
= −1.8 V, I = −4 A
D
= −5 V, I = −7.8 A, T = 125°C
D
J
g
FS
= −5 V, I = −7.8 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −10 V, V = 0 V, f = 1 MHz
−
−
−
1515
265
2015
355
pF
pF
pF
iss
GS
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
240
360
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
R
= −10 V, I = −7.8 A V = −5 V,
−
−
−
−
−
−
−
6.4
14
192
96
30
2
13
25
307
154
42
−
ns
ns
d(on)
DD
D
GS
= 6 W
GEN
t
r
t
Turn−Off Delay Time
Fall Time
ns
d(off)
t
f
ns
Q
g(TOT)
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
= −10 V, I = −7.8 A V = −5 V
nC
nC
nC
DD
GS
D
GS
Q
Q
gs
gd
7.5
−
DRAIN−SOURCE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = −2.0 A (Note 2)
−
−
−
−0.6
66
−1.2
106
70
V
SD
S
t
rr
I = −7.8 A, di/dt = 100 A/ms
F
ns
nC
Q
rr
Reverse Recovery Charge
44
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
JC
q
q
JA
by design while R
is determined by the user’s board design.
q
CA
a. 52°C/W when mounted on a
b. 145°C/W when mounted on a
minimum pad of 2 oz copper
2
1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
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2
FDMA507PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
J
24
20
16
12
8
2.5
V
= −5 V
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
V
= −4.5 V
GS
V
GS
= −3 V
2.0
1.5
1.0
0.5
= −2.5 V
GS
V
= −1.8 V
GS
V
= −1.8 V
GS
V
GS
= −2.5 V
V
GS
= −5 V
4
V
= −3 V
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= −4.5 V
16
0
0
0.2
0.4
0.6
0.8
1.0
0
4
8
12
20
24
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
−I , DRAIN CURRENT (A)
D
Figure 1. On Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
1.6
1.4
1.2
1.0
0.8
0.6
160
120
80
40
0
I
V
= −7.8 A
= −5 V
I
= −7.8 A
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
D
D
GS
T = 125°C
J
T = 25°C
J
−75 −50 −25
0
25
50
75 100 125 150
1
2
3
4
5
T , JUNCTION TEMPERATURE (°C)
J
−V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 3. Normalized On Resistance vs.
Junction Temperature
Figure 4. On−Resistance vs. Gate to Source Voltage
24
20
16
12
8
20
10
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
V
DS
= −5 V
1
T = 150°C
J
T = 25°C
J
0.1
T = −55°C
J
T = 150°C
J
T = 25°C
J
0.01
4
T = −55°C
J
0
0.001
0
0.5
1.0
1.5
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage vs.
Source Current
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3
FDMA507PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
J
5
4
3
2
1
0
10000
I
D
= −7.8 A
V
DD
= −8 V
C
C
iss
V
= −10 V
DD
1000
V
DD
= −12 V
oss
C
rss
f = 1 MHz
= 0 V
V
GS
100
0
10
20
30
40
0.1
1
10
20
Q , GATE CHARGE (nC)
g
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain to Source Voltage
10−1
10−2
10−3
10−4
10−5
10−6
10−7
10−8
10−9
10−10
50
V
GS
= 0 V
100 ms
10
1 ms
10 ms
1
0.1
T = 125°C
J
THIS AREA IS
LIMITEDBY r
100 ms
DS(on)
1 s
10 s
DC
SINGLE PULSE
T = MAX RATED
J
T = 25°C
J
R
= 145°C/W
q
JA
T = 25°C
A
0.01
0
3
6
9
12
15
0.1
1
10
80
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 9. Gate Leakage Current vs.
Gate to Source Voltage
Figure 10. Forward Bias Safe Operating Area
1000
100
10
SINGLE PULSE
R
= 145°C/W
q
JA
T = 25°C
A
1
0.5
10−4
10−3
10−2
10−1
t, PULSE WIDTH (s)
1
10
100
1000
Figure 11. Single Pulse Maximum Power Dissipation
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4
FDMA507PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
P
DM
t
1
t
2
SINGLE PULSE
= 145°C/W
NOTES:
DUTY FACTOR: D = t / t
R
q
JA
1
2
PEAK T = P
x Z
x R
+ T
JA A
q
q
J
DM
JA
0.001
10−4
10−3
10−2
10−1
t, RECTANGULAR PULSE DURATION (s)
1
10
100
1000
Figure 12. Junction−to−Ambient Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package
Reel Size
Tape Width
Shipping
FDMA507PZ
507
WDFN6 2x2, 0.65P
(MicroFET 2x2)
7”
12 mm
3000 / Tape & Reel
(Pb−Free, Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
MicroFET is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511DB
ISSUE O
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13617G
WDFN6 2X2, 0.65P
PAGE 1 OF 1
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