FAN53745UC00X [ONSEMI]
Buck Regulator, Synchronous, 3.33 MHz, 1 A;
| 型号： | FAN53745UC00X |
| 厂家： | 
ONSEMI |
| 描述： | Buck Regulator, Synchronous, 3.33 MHz, 1 A |
| 文件： | 总37页 (文件大小：1609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Buck Regulator,
Synchronous, 3.33 MHz, 1 A
WLCSP6
CASE 567UH
FAN53745
Description
MARKING DIAGRAM
The FAN53745 is a low quiescent current step−down DC/DC
converter that delivers a regulated output voltage from an input supply
of 2.3 V to 5.5 V. The combination of built−in power transistors,
synchronous rectification, and a tiny solution size make the device
ideal for portable applications.
The converter normally operates in PWM Mode at a typical
fixed−frequency of 3.33 MHz. At moderate and light loads, the device
will transition into PFM Mode to maintain high efficiency and
excellent transient response. Additionally, a low power Shutdown
Mode reduces power consumption when the device is disabled.
The FAN53745 is available in 6−bump, 0.4 mm pitch, Wafer−Level
Chip−Scale Package (WLCSP).
12KK
XYZ
12
= Alphanumeric Device Code
(see Ordering Information for
specific device marking)
= Lot Run Number
= Alphanumeric Year Code
= 2−Weeks Date Code
= Assembly Plant Code
KK
X
Y
Z
FAN53745
L1
V
Features
OUT
VIN
SW
C
Proprietary Current Mode Architecture
Wide Input Voltage Range: 2.3 V to 5.5 V
1 A Load Capability
IN
0.47ꢀ H
C
OUT
4.7ꢀ F
2x10ꢀ F
SCL
SDA
FB
PFM / PWM Modes for High Efficiency
2
I C−compatible Interface
GND
Programmable Output Voltage: 1.5 V to 3.3 V
Programmable Current Limit: 440 mA to 2090 mA
Internal Soft−Start
Figure 1. Typical Application
Protection Faults
(OT, Input UVLO, Output Short and Reverse Current)
Automatic Pass−Through Operation
Hardware Reset when Holding SCL Low
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Pb−Free and RoHS Compliant
Applications
Smart Phones
Smart Watch
Health Monitoring
Sensor Drive
Energy Harvesting
Utility and Safety Modules
RF Modules
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2023 − Rev. 2
FAN53745/D
FAN53745
ORDERING INFORMATION
Device
Marking
Output
Voltage
Temperature
Slave
Address
†
Range
Part Number
Package
Shipping
MJ
2.60 V
2.6 V
−25C to +85C
6−bump WLCSP,
S/B 1.50 x 0.94
Tape & Reel
FAN53745UC00X
7h’20
7h’30
FAN53745UC01X
(In Development)
TBD
FAN53745UC02X
(In Development)
TBD
2.6 V
7h’32
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
A2
VIN
bck_ipk
Buck Control
bck_ilim
Fsw
Core Analog
Block
REF
B2
SW
GND
FB
C2
C1
Digital Control
bk_ipk
Thermal
Protection
therm_sd
vin_uvlo_ref
VIN
I2C
A1
B1
SDA
SCL
Figure 2. Block Diagram
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2
FAN53745
PRODUCT PIN ASSIGNMENTS
VIN
A2
SDA
A1
SDA
A1
VIN
A2
SCL
B1
SW
B2
SW
B2
SCL
B1
GND
C2
FB
C1
FB
C1
GND
C2
TOP VIEW
BOTTOM VIEW
Figure 3. Pin Arrangement
PIN DESCRIPTION
Pin No.
A1
Name
SDA
VIN
Description
2
Serial Interface Data. I C input/output data line pin. Do not leave this pin floating.
Input Voltage. Power input to converter. Place input decoupling capacitor as close to the this pin as possible.
A2
2
B1
SCL
Serial Interface Clock. I C Clock input pin. Holding this pin low for 100 ms will generate a hardware reset.
Do not leave this pin floating.
B2
C1
C2
SW
FB
Switching Node. Connect to one side of the inductor.
Feedback. Connect to positive side of output capacitor.
Ground. Power and IC ground. All signals are referenced to this pin.
GND
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3
FAN53745
MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.3
−0.3
−0.3
−0.3
−
Typ
−
Max
6.0
Unit
V
V
IN
Input Voltage
V
SW
−
Voltage on SW Pin
6.0
V
V
CTRL
SDA and SCL Pins
−
(Note 1)
(Note 1)
−
V
FB Pin
−
V
ESD
ESD
Electrostatic Discharge Protection Level
Electrostatic Discharge Protection Level
Junction Temperature
Storage Temp
Human Body Model
2.0
500
−
kV
V
Charged Device Model
−
−
T
J
−40
−40
+150
+150
C
C
T
STG
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 6 V or VIN + 0.3 V.
THERMAL CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Q
Junction−to−Ambient Thermal Resistance
−
65
−
°C/W
JA
2. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with two−layer 2s2p with VIAs
boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given
ambient temperature TA.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage Range
Conditions
Min
2.3
−
Typ
−
Max
5.5
−
Unit
V
V
IN
L
Inductor
0.47
4.7
2x10
−
ꢀ H
ꢀ F
ꢀ F
mA
°C
C
−
−
Input Capacitor
IN
C
I
−
−
Output Capacitor
Output Current
OUT
−
1000
+85
OUT
T
A
−
Operating Ambient Temperature
Junction Temperature
−25
−40
T
J
−
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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FAN53745
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V = 3.8 V, V
= 1.5 to 3.3 V, T = −25C to +125C
J
IN
OUT
unless otherwise noted. Typical values are at T = 25C, V = 3.8 V, V = 2.6 V)
A
IN
OUT
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OPERATING CURRENT
I
−
−
−
−
−
−
Shutdown Supply Current
Standby Supply Current
PFM Quiescent Current
ENABLE bit = 0, No Load, SCL pulled low
ENABLE bit = 0, No Load
0.25
15.4
43
ꢀ A
ꢀ A
ꢀ A
RESET
I
IDLE
IQ
ENABLE bit = 1, PFM Mode, Non
Switching, No Load
PFM
IQ
−
−
−
−
PWM Quiescent Current (Note 4) ENABLE bit = 1, FPWM Mode, No Load
8.5
80
mA
PWM
IQ
PASS−THRU from PFM Current
ENABLE = 1, V
> V > V
UVLO
ꢀ
A
PT_PFM
OUT_TARGET
IN
Consumption (Note 4)
IQ
PASS−THRU from PWM Current
Consumption (Note 4)
ENABLE bit = 1, V
UVLO
> V >
IN
−
80
−
ꢀ
A
PT_PWM
OUT_TARGET
V
OUTPUT VOLTAGE
VO
VO
−
−
−
−
−
−
Minimum Programmable Voltage
2.3 V V 4.9 V
1.500
3.30
V
V
MIN
IN
Maximum Programmable Voltage 3.8 V V 4.9 V
MAX
DVS
IN
VO
Programmable Voltage Slew Rate 1.5 V V
3.3 V
0.5, 1.0,
1.25,
mV/ꢀ s
OUT
2.0, 2.5,
3.75, 5,
10
VO
Programmable Voltage Slew Rate
for 0.5 to 3.75 mV/ꢀ s
Scaling Settings
V
IN
= 2.3 to 4.9 V & V > V
+ 500 mV
−10
−
+10
%
DVS_ACC
IN
OUT
Programmable Voltage Slew Rate
V
V
= 2.3 to 4.9 V & V > V
+ 500 mV
+ 500 mV
−20
−
−
+20
40
%
IN
IN
OUT
for 5 mV/ꢀ s and 10 mV/ꢀ s
2
T
DVS
Period from I C command to
= 2.3 to 4.9 V & V > V
−
ꢀ
s
IN
IN
OUT
ramp start
PWM VOLTAGE ACCURACY
VOUT Output Voltage Accuracy
V
V
OUT
= 2.3 to 4.9 V & V > V
+ 500 mV,
−40
−2
−
−
+40
+3
mV
%
ACC
IN
IN
OUT
= 1.5 V to 3.3 V, Forced PWM Mode,
OUT
I
= 0 A; −40C to 85C
PFM VOLTAGE ACCURACY
VOUT
Output Voltage Accuracy
V
V
OUT
= 2.3 to 4.9 V & V > V
+ 500 mV,
ACC
IN
OUT
IN
OUT
= 1.5 V to 3.3 V, PFM Mode,
I
= 0 A; −40C to 85C
CURRENT LIMIT
ILIM
Peak Inductor Current Limit
Accuracy
Peak current accuracy for 1.0 A pk
−25
−12
−30
−20
−700
−
+25
+12
%
%
PWM_ACC
setting, open loop
Peak current accuracy for > 1.0 A pk
setting, open loop
−
−
ILIM
PFM peak current accuracy for < 1.0 A pk
setting, open loop
+30
%
PFM_ACC
PFM peak current accuracy for > 1.0 A pk
setting, open loop
−
+20
%
ILIM
Negative Current
−1000
−1300
mA
NEG
PFM <−> PWM THRESHOLDS
I
I
where part transitions into
V
V
= 3.8 V, V
= 3.8 V, V
= 1.5 V − 3.3 V
= 1.5 V − 3.3 V
−
−
103
135
−
−
mA
mA
PFM
OUT
IN
OUT
PFM
I
I
OUT
PWM
where part transitions into
PWM
IN
OUT
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FAN53745
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V = 3.8 V, V
= 1.5 to 3.3 V, T = −25C to +125C
J
IN
OUT
unless otherwise noted. Typical values are at T = 25C, V = 3.8 V, V = 2.6 V) (continued)
A
IN
OUT
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
UVLO DETECTION
V
Under−Voltage Lockout Threshold Rising V
2.10
2.00
−
2.15
2.05
100
2.20
2.10
−
V
V
UVLO_RISE
UVLO_FALL
IN
V
Under−Voltage Lockout Threshold Falling V
IN
V
UVLO Hystersis
mV
UVLO_HYS
POWER MOSFETs RDSON
RDS
RD
VIN = VGS = 3.8 V
VIN = VGS = 3.8 V
−
−
−
−
NMOS Resistance (Ball−to−Ball)
PMOS Resistance (Ball−to−Ball)
92
m
ꢁ
ꢁ
ON_NMOS
125
m
ON_PMOS
GENERAL
F
Switching Frequency
PWM, I
= 0 A
3.00
80
3.33
100
3.67
120
MHz
SW
OUT
R
Output Discharge Resistance
ꢁ
BK_DIS
2
I C TIMING AND PERFORMANCE
V
−
−
SDA and SCL Logic Low threshold
−
0.4
5.5
V
V
IL
V
IH
SDA and SCL Logic High
threshold
1.2
V
I
−
−
−
−
−
SDA Logic Low Output
SDA Sink Current
3 mA Sink
0.4
−
V
OL
2.0
mA
kHz
ꢀ s
OL
f
SCL Clock Frequency
Fast Mode Plus
Fast Mode Plus
1000
−
SCL
t
Bus−Free Time Between STOP
and START Conditions (Note 4)
0.5
BUF
t
t
; STA
START or Repeated START Hold Fast Mode Plus
Time
260
−
−
ns
HD
t
SCL LOW Period
Fast Mode Plus
Fast Mode−Plus
Fast Mode−Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
0.5
260
260
50
−
−
−
−
−
−
−
−
−
−
−
−
−
ꢀ s
ns
ns
ns
ns
ns
ns
ns
ns
pF
LOW
t
SCL HIGH Period
HIGH
; STA
; DAT
; DAT
Repeated START Setup Time
Data Setup Time
−
SU
SU
VD
t
t
−
Data Valid Time
450
450
120
120
−
t
; ACK
Data Valid Acknowledge Time
−
VD
t
R
SDA and SCL Rise Time (Note 4) Fast Mode Plus
−
t
F
SDA and SCL Fall Time (Note 4)
Stop Condition Setup Time
Fast Mode Plus, V = 1.8 V
6.55
260
−
DD
t
; STO
Fast Mode Plus
SU
C
SDA and SCL Input Capacitance
(Note 5)
10
i
C
Capacitive Load for SDA and
SCL (Note 5)
−
−
−
550
50
pF
ns
b
t
SP
Spike pulse width that input filter
must be suppress
SCL, SDA only
0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Refer to Typical Characteristics waveforms/graphs for closed loop data and variation with input supply and temperature. Electrical
specifications reflects both steady state and dynamic close loop data associated with the recommended external components.
4. Guaranteed by Design. Characterized on the ATE or Bench
5. Guaranteed by Design Only. Not Characterized or Production Tested
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FAN53745
SYSTEM SPECIFICATIONS (The following system specifications are guaranteed by designed and verified during bench evaluation,
but are not performed in production testing. Recommended operating conditions, unless otherwise noted are, V = 2.3 V to 4.9 V & V
>
IN
IN
V
+ 500 mV, T = −25C to 85C, V
= 2.6 V. Typical values are based on V = 3.8 V, V
= 2.6 V and T = 25C. System
OUT
A
OUT
IN
OUT A
Specifications area based on circuit per Figure 1. L = 0.47 ꢀ H, C = 4.7 ꢀ F, C
= 2 x 10 ꢀ F) (Note 6)
IN
OUT
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VOUT REGULATION
LOAD
Load Regulation
Load Transient
Line Transient
1 mA I
OUT
1000 mA, V = 2.3 to 4.9 V & V
IN
−5
−
−
−
+5
mV
mV
mV
REG
OUT
IN
V
+ 500 mV, V
= 1.5, 2.6, 3.2 V FPWM
OUT
V
TRRP
I
= 0 mA <−> 1 A, T = T = 500 mA/ms, Auto
−30
−35
+45
+35
OUT
R
OUT
F
Mode, V = 3.8 V, V
= 1.5, 2.6 and 3.2 V
IN
LINE
V
= 3.0 V <−> 3.6 V, 100 mV/ꢀ s, I
= 300 mA,
TRAN
IN
OUT
PWM, V
= 2.6 V
OUT
RIPPLE
V
Output Ripple
Output Ripple
V
= 2.3 to 4.9 V, I = 1 mA and 10 mA, PFM
OUT
−
−
31
5
50
15
mV
mV
RIPPLE
IN
Mode, V
= 1.5, 2.6 and 3.2 V
OUT
V
V
V
= 2.3 to 4.9 V, I
= 500 mA and 1.0 A,
RIPPLE
IN
OUT
OUT
= 1.5, 2.6 and 3.2 V, PWM Mode
6. System Specification are tested closed loop while using the recommended external components table.
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FAN53745
TYPICAL CHARACTERISTICS
UNLESS OTHERWISE SPECIFIED, V = 3.8 V, V
= 2.6 V, AUTO MODE, T = 25C, CIRCUIT AND COMPONENTS ACCORDING
A
IN
OUT
TO THE RECOMMENDED EXTERNAL COMPONENTS AND LAYOUT.
Figure 4. Efficiency vs. Load Current and Input
Figure 5. Efficiency vs. Load Current and
Temperature
Voltage
Figure 6. Efficiency vs. Load Current and Input
Voltage, FPWM Mode
Figure 7. Efficiency vs. Load Current and
Temperature, FPWM Mode
Figure 8. Shutdown Current vs. Input Voltage
and Temperature
Figure 9. Standby Current vs. Input Voltage
and Temperature
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FAN53745
TYPICAL CHARACTERISTICS
UNLESS OTHERWISE SPECIFIED, V = 3.8 V, V
= 2.6 V, AUTO MODE, T = 25C, CIRCUIT AND COMPONENTS ACCORDING
A
IN
OUT
TO THE RECOMMENDED EXTERNAL COMPONENTS AND LAYOUT.
Figure 10. PFM Quiescent Current vs. Input
Figure 11. PWM Quiescent Current vs. Input
Voltage and Temperature
Voltage and Temperature
Figure 12. Frequency vs. Load Current and
Input Voltage
Figure 13. Output Ripple vs. Load Current and
Input Voltage
Figure 14. Output Voltage Accuracy (%) and
Input Voltage
Figure 15. Output Voltage Accuracy (%) and
Temperature
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FAN53745
TYPICAL CHARACTERISTICS
UNLESS OTHERWISE SPECIFIED, V = 3.8 V, V
= 2.6 V, AUTO MODE, T = 25C, CIRCUIT AND COMPONENTS ACCORDING
A
IN
OUT
TO THE RECOMMENDED EXTERNAL COMPONENTS AND LAYOUT.
Figure 16. FPWM Output Voltage Accuracy
Figure 17. FPWM Output Voltage Accuracy
(mV) and Temperature
(mV) and Input Voltage
Figure 18. Load Regulation and Input Voltage
Figure 19. Load Regulation and Temperature
Figure 20. Line Regulation and Load Current
Figure 21. Line Regulation and Temperature,
OUT = 200 mA
I
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FAN53745
TYPICAL CHARACTERISTICS
UNLESS OTHERWISE SPECIFIED, V = 3.8 V, V
= 2.6 V, AUTO MODE, T = 25C, CIRCUIT AND COMPONENTS ACCORDING
A
IN
OUT
TO THE RECOMMENDED EXTERNAL COMPONENTS AND LAYOUT.
IL (500mA/div)
SW (2V/div)
VIN (200mV/div), 3V offset
VOUT (20mV/div)
200us/div
Figure 22. PFM−PWM Entry, VOUT = 2.6 V
Figure 23. Line Transient, VOUT = 2.6 V,
3 V u" 3.6 V, 6 ms Edge, 300 mA Load
IL (500mA/div)
SW (5V/div)
VIN (500mV/div), 3.8V offset
SW (2V/div)
IOUT (100mA/div)
IL (500mA/div)
VOUT (20mV/div)
VOUT (20mV/div)
100us/div
200us/div
Figure 24. Line Transient, VOUT = 3.3 V,
Figure 25. Load Transient
3.8 V u" 4.4 V, 6 ms Edge, 300 mA Load
10 mA u" 200 mA, 1 ms Edge
IOUT (100mA/div)
IL (500mA/div)
IL (500mA/div)
SW (5V/div)
IOUT (500mA/div)
VOUT (20mV/div)
SW (2V/div)
VOUT (20mV/div)
100us/div
2ms/div
Figure 26. Load Transient
Figure 27. Load Transient
10 mA u" 200 mA, 1 ms Edge, FPWM Mode
0 A u" 1 A, 2 ms Edge
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FAN53745
TYPICAL CHARACTERISTICS
UNLESS OTHERWISE SPECIFIED, V = 3.8 V, V
= 2.6 V, AUTO MODE, T = 25C, CIRCUIT AND COMPONENTS ACCORDING
A
IN
OUT
TO THE RECOMMENDED EXTERNAL COMPONENTS AND LAYOUT.
SW (2V/div)
IL (200mA/div)
VIN (500mV/div)
VIN (1V/div)
VOUT (500mV/div)
IL (200mA/div)
VOUT (500mV/div)
SW (2V/div)
400us/div
400us/div
Figure 28. Pass Thru Operation, IOUT = 10 mA,
Figure 29. Pass Thru Operation, IOUT = 1 A,
V
IN = 3 u" 2.4 V, VOUT = 2.6 V
V
IN = 3.8 u" 2.4 V, VOUT = 2.6 V
SCL (2V/div)
IL (500mA/div)
SW (5V/div)
SW (2V/div)
SDA (2V/div)
IL (500mA/div)
VOUT (500mV/div)
VOUT (1V/div)
100us/div
80us/div
Figure 30. Startup into 100 mA Load
Figure 31. Startup into 500 mA Load
IL (500mA/div)
SW (5V/div)
VOUT with pulldown disabled (2V/div)
VOUT with pulldown = 100 ohm (2V/div)
VOUT with pulldown = 50 ohm (2V/div)
4ms/div
Figure 32. VOUT Discharge with Different Pulldown Settings
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FAN53745
FUNCTIONAL SPECIFICATIONS
Device Operation
During medium to heavy loading of the output, the
FAN53745 operates in PWM operation to ensure excellent
regulation. During light loading, the device automatically
switches to PFM operation for high efficiency. To avoid
potential noise interference by PFM switching frequencies
with the load or other circuitry, the device can be
programmed into Forced PWM operation. More details on
PFM and PWM operation can be found under the Modes of
Operation heading.
Operation Description
The FAN53745 uses a proprietary current mode
architecture with synchronous rectification to convert input
voltages down to a regulated output voltage while limiting
the peak inductor current.
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FAN53745
From any state POR = 1 or
(SCL = 0 for > 100 ms) or SW Reset
2
I C will NAK
Buck is Disabled
SCL = 0 or
POR = 1
RESET
SCL = 0 for SCL = 1 and SW Reset
100 ms
POR = 0
SCL = 0 for
100 ms
SW Reset
UVLO or
OTP Fault
2
IDLE
I C will ACK
Buck is Disabled
2
I C enabled
uvlo/otp detect ON
Buck Disabled
CRASH
Enable bit set to 1
Ready = 1
Enable bit set to 0
Buck Disable
En bit reset to 0
Uvlo or otp event
ACTIVE
2
I C enabled
uvlo/otp detect ON
Buck Enabled
active_state = 1
2
I C will ACK
Buck is Enabled
Ready status = ((idle_state or active_state) and pwr_ok and (over_temp_fault or uvlo_fault)
Figure 33. State Diagram
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FAN53745
Device States
Idle State
2
In Idle State the I C registers are read/write accessable
and the UVLO comparator is activated. The READY bit in
the Status Register 0x02h will be ”1” while in the Idle State,
providing there isn’t a UVLO or OT fault. If the input
voltage is less than UVLO rising threshold upon entering the
Idle State from the Reset State, a UVLO fault will be
generated and the device will stay in this state as long as POR
< VIN < UVLO rising.
When the device enters Idle State due to either a UVLO
or OT condition, the device waits 20 ms for the fault to clear.
If the fault still exists after the 20 ms, the device will remain
in the Idle State and READY = 0 until the fault clears. If the
ENABLE bit is set to a ”1” while either a UVLO or OT fault
condition exists, the bit will be immediately cleared and the
device will not advance to the Active State. Only after the
fault has cleared and ENABLE is then set to ”1” will the
device move to the Active State.
Reset State
When power is applied to the FAN53745, the device will
go through a Power On Reset (POR) and then the FAN53745
checks the state of the I C SCL pin. If the SCL pin is low, the
device will stay in the Reset State. If the SCL is high or if it
at anytime goes high, the device moves to the Idle State.
During Reset State, all I C registers are cleared to their
default values and cannot be written to or read. If at anytime
the input voltage were to fall below the POR threshold, the
device will completely power off.
2
2
Software Reset
If the correct Reset code is written to the RESET register
or the SCL pin is pulled low for more than 100 ms, the device
will exit the present state (Active or Idle) and enter the Reset
State. For a SW reset, by setting the Reset register, the device
will only enter the Reset State momentarily to clear the
registers and then the device will enter Idle State.
Active State
SCL Low Reset
In Active State, the buck converter is enabled and
provides a regulated output voltage to the load. If during
Active State the input voltage falls between POR and
UVLO_Falling, the device will exit Active State, the Enable
bit will be cleared and the device will return to an Idle State.
If the device temperature exceeds the OTP threshold
while in the Active State, the Enable bit will be cleared and
the device will return to the Idle State. The device will
remain in the idle state until it cools below the hysteresis
level and the ENABLE bit is set again to ”1”.
When a UVLO or OTP fault occurs, the associated
STATUS and FAULT register bits are set. The Status bit will
be cleared when the input voltage recovers or the die
temperature returns below the hysteresis level. The Fault
bits will remain set to ”1” until they are read.
If the device entered Reset because the SCL was held low
for more than 100 ms, house keeping circuitry will be
powered down to reduce power consumption and all
registers will be reset to their default values. The device will
remain in the Reset State as long as the SCL is held low.
Once the SCL is released high, a wait time of ~20 ꢀ s or more
should be allowed for the I C to properly read any I C
commands. After the housekeeping circuitry is stable, the
READY bit will be set and the ENABLE bit can be set for
the device to move from the Idle State to Active State.
2
2
2
Note: Care should be used when sharing the I C with
another slave which may stretch the clock for more than
100 ms. If the application requires for the FAN53745 to
ignore the SCL being held low, please consult your local On
Semiconductor representative.
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15
FAN53745
Startup Behavior
Protection Features
Startup Description
SHORT FAULT
To enable the FAN53745, the ENABLE Register bit must
be set to “1”. The FAN53745 has internal soft−start which
limits the input current from the battery by incrementing the
voltage up to the target output voltage. This limits the current
drawn and prevents brown out conditions. The device starts
up within 520 ꢀ s typical using the recommended external
components table.
If the output voltage falls below one−half the programmed
voltage during normal operation, the device will declare a
Short fault immediately without a debounce period and the
SHORT FAULT bit will be set.
PFM Current Limit
During PFM operation, the peak current is limited to
control the ripple and prevent the inductor from saturating.
The open loop PFM current limit can be programmed
between 500 mA and 1325 mA in 55 mA steps. Due to
inherent delays, the closed loop PFM current limit is
expected to be 10 to 15% higher than the open loop PFM
ILIMIT threshold of the device. Once the current limit is set,
it can be locked by setting the locking bit
V_I_LIMIT_LOCK.
Shutdown Behavior
Disable
To disable the FAN53745, the ENABLE reg bit should be
configured to code 0. When the part is disabled, the output
will tristate. If the DISCHARGE SEL bits are set to
something other than ”00”, the output will be discharged
through the selected resistance. Otherwise, if DISCHARGE
SEL = ”00”, the output will only be discharged by the load.
PWM Current Limit
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from damaging the device. After 500 ꢀ s of current
limit, the regulator triggers an over−current fault, causing
the regulator to shut down for about 20 ms before attempting
a restart. If the fault is caused by a short circuit, the soft−start
circuit attempts to restart after about 20 ms and produces a
SHORT FAULT if the fault persisted.
Active Pull Down
The FAN53745 has an active pull down to discharge the
output capacitance. Once the ENABLE reg bit is set to 0,
within ~2 ꢀ s, the active pull down is enabled and discharges
the VOUT via an internal resistor. The strength of the pull
down can be selected between 50 ꢁ, 100 ꢁ (Default), 200ꢂ ꢁ
2
and open by setting the DISCHARGE SEL I C bit. If the
2
DISCHARGE I C bit is set to 1, the resistor selected by
DISCHARGE SEL will be used to discharge the output
during voltage programming transitions from a higher to
lower voltage.
The open Loop Peak Inductor Current Limit can be
2
programmed via I C and range from 440 mA to 2090 mA
max in 110 mA steps. Due to inherent delays, the closed loop
current limit is expected to be 10 to 15% higher than the open
loop ILIMIT threshold of the device.
Modes of Operation
PFM
Pulsed Frequency Modulation (PFM) operation adjusts
the switching frequency relative to the load. By reducing the
switching frequency at lighter load conditions, higher
efficiency is realized at these light loads. In Automode
operation, the device enters PFM mode when the load falls
below IPFM threshold.
UVLO
Rising
While in Idle or Active State, the UVLO detection is
enabled. The FAN53745 is designed to check the input
voltage before enabling the converter. For Idle State, the
input voltage must be above the UVLO rising threshold
when the ENABLE bit is set to enable the buck converter.
Otherwise, once loaded by the buck converter, the input
voltage may fall below the UVLO falling threshold,
resulting in start−up hiccup behavior. If the voltage is below
the UVLO rising threshold when the ENABLE bit is set, the
UVLO fault and status bits will be set and the ENABLE bit
cleared.
PWM
During Pulse Width Modulation (PWM) mode, the device
switches at a nominal fixed frequency of 3.3 MHz, which
reduces the values of the external components. During Auto
Mode, the part enters PWM when load currents exceed
IPWM typ. In PWM mode the device has excellent load
regulation, ideal for powering loads which are sensitive to
deviations in supply voltage. The FAN53745 can be forced
into PWM (FPWM) regardless of the load current by setting
FORCE_PWM to a “1”.
Falling
If the input voltage falls below the UVLO_falling
threshold during Active State, the buck ENABLE bit will be
cleared, the device will go to the Idle State and the
PASS−THRU and PFM−PWM bits in the Status Reg are set
to their default values of ”0” and ”1” respectively.
Pass Thru
To ensure there is not sub−harmonic behavior when Vin
is close to the Vout_Target, the device enters Pass−Thru
automatically. Using a proprietary method, the device
maintains excellent regulation when transitioning into and
out of Pass−Thru mode.
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16
FAN53745
Thermal Shutdown
by the period of time between each step can be controlled by
setting the DVS register bits.
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the ENABLE
bit is cleared and the device returns to Idle State and the
OVER TEMP Status and Fault bits are set. The
PASS−THRU and PFM−PWM bits in the Status Reg are set
to their default values of ”0” and ”1” respectively.
By monitoring the OVER TEMP bit in the FAULT
STATUS register, when the die temperature falls below the
hysteresis temperature and OVER_TEMP falls to ”0”, the
buck can be re−enabled.
Limiting the Programmable Range
If a new voltage value is written into the VSEL register
which is either higher than VMAX or lower than VMIN, the
DAC will scale to the limit(VMAX or VMIN), preventing
the voltage from going beyond the limit.
If a new value for VMAX or VMIN is written to the
registers and is either lower than or higher than respectively
of the present voltage in the VSEL register, the output
voltage will remain at it’s present voltage until commanded
to change when a new VSEL value is written.
Negative Current Limit
The FAN53745 has a negative current limit protection
which limits the current through the NFET in PWM Mode.
If a voltage is applied to the buck output and is higher than
VOUT target while in PWM, a negative current will be
detected. Once the inductor current hits −1 A for one cycle,
the output begins to tristate until the applied voltage is
released and the output voltage falls below the regulated
voltage.
In PFM mode, the Zero Crossing Detection does not allow
any negative current to flow within inductor, any voltage
higher than vout target applied to output will cause the
regulator to enter tri−state and block current back through
inductor.
Dynamic Voltage Scaling
The FAN53745 DVS operation for programming the
voltage to a new level can be controlled by setting the DVS
register bits for rates of 0.5 to 10 mV/ꢀ s. If the DVS EN bit
in the MODE Register, 0x03 is set to a ”1” when the output
voltage is commanded to a lower voltage, the DAC
decrements through the programmable output voltage steps
until the reference value for target voltage is reached. The
output voltage will fall at a rate dependent on the amount of
distributed capacitance and load. The speed of the reduction
in voltage can be accelerated by setting the DISCHARGE
register bit in the SHUTDOWN register. The discharge
resistance will be disabled when the DAC reference value is
reached. The drawings below provide an example of the
behavior during rising and falling DVS control.
NOTE: If a voltage applied to VOUT is greater than VIN,
the body diode of high side FET will conduct.
Note:
Output Voltage
If there is little or no load on the output during the ramp,
some non−linear ramping of the output voltage may be
observed during DVS ramping.
Simply setting the DVS bit to a ”1” does not initiate
voltage change. Voltage change is only initiated when the
VSEL register value is changed.
Programmable Output Voltage
The FAN53745 output voltage can be programmed in
10 mV steps from 1.5 to 3.3 V using the VESL register. The
voltage transition is implemented by stepping through the
voltage programming DAC up−to/down−to the new target
voltage. The FAN53745 provides DVS functionality where
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17
FAN53745
I2C Interface
IC supports single register read and write transactions as
well as multiple register read transactions.
Introduction
The FAN53745 serial interface is compatible with the
Standard−mode, Fast−mode and Fast−mode Plus I C bus
specifications. The SCL pin is an input and the SDA pin is
bi−directional with an open−drain output configuration. The
Slave Address
2
2
The default I C address for one of the device options is
shown below. See Ordering Information for the other
released device options and their default values. Contact
onsemi to request configuration options.
Table 1. DEVICE ADDRESS VALUES
Device
Hex
Binary
FAN53745UC00X
7h20
0100000X
Table 2. 7−BIT BINARY ADDRESS
7
6
5
4
3
2
1
X
0
1
0
0
0
0
0
R/W
READ = 1
WRITE = 0
2
I C Timing Diagrams
tF
tSU;STA
tBUF
SDA
tSU;DAT
tR
tHIGH
tSU;STO
SCL
tLOW
tHD;DAT
tHD;STA
tHD;STA
STOP
START
START
REPEATED
START
Figure 34. I2C Interface Timing for Fast−Mode Plus, Fast−Mode and Standard−Mode
Normally, data transfer occurs when the SCL is LOW.
Data is clocked in on the rising edge of SCL. Typically data
transitions at or after the subsequent falling edge of SCL to
provide ample setup time for the next data bit to be ready
before the subsequent rising edge of the SCL.
Data Change Allowed
SDA
TH
TSU
SCL
Figure 35. Data Transfer Timing
2
The idle state of I C bus is with both SCL and SDA HIGH.
is defined as SDA transitioning from High to LOW with
SCL HIGH.
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
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18
FAN53745
Slave Address
THD:STA
MS Bit
SDA
SCL
Figure 36. Start Bit Timing
A valid transaction ends with a STOP condition which
occurs when SDA transaction from LOW to HIGH while
SCL remains HIGH.
Slave Release
Master Drives
TSU
;STO
ACK (0) or
SDA
NACK (1)
SCL
Figure 37. Stop Bit Timing
A
REPEATED START condition is functionally
before re−sending the slave address. The REPEATED
START is a HIGH to LOW transition on SDA while SCL is
HIGH.
equivalent to a STOP condition followed by a START
condition. During a read from the IC, the master issues a
REPEATED START after sending the register address and
TSU;STA
Slave Release
THD;STA
ACK(0) or
NACK(1)
SLAVE ADDR
MS Bit
SDA
TVD;DAT
SCL
Figure 38. Repeated Start Timing
Read and Write Transactions
Figure 39. Single Register Write Transaction
Figure 40. Single Register Read Transaction
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19
FAN53745
Figure 41. Multiple Register Write Transaction
2
I C Hardware Reset
2
The FAN53745 can be reset and the I C registers cleared
to their default values by pulling SCL low for more than
100 ms.
Figure 42. I2C Timing
FUNCTIONAL BEHAVIOR
Defined Behavior
PFM <−> PWM Thresholds
Device will transition into PWM when IOUT reaches
IPWM and transition back to PFM when load current falls
below IPFM.
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20
FAN53745
REGISTER MAPPING TABLE
Table 3. REGISTER MAPPING
Read Only Write Only Read / Write Read / Clear Write / Clear
Address
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
0x00
Product
ID_REV
Product ID
Silicon Revision
0x01
FAULT
FLAGS
0
STARTUP
TIMEOUT
FAULT
UVLO
FAULT
OVER
TEMP
FAULT
SHORT
FAULT
ILIM FAULT
0x02
0x03
STATUS
MODE
0
READY
PASS-THRU PFM_PWM
OPERATION
UVLO
OVER
TEMP
VOUT
SHORT
CURRENT
LIMIT
ENABLE
FORCE_P V_I_LIMIT_
WM LOCK
SS
TIMEOUT
DVS EN
DVS
0x04
0x05
0x06
0x07
VSEL
VMIN
VMAX
BUCK_VOUT
VOUT_MIN
VOUT_MAX
SHUT
DOWN
0
DISCHARGE SEL
PWM ILIM
DISCHARGE
0x08
0x09
ILIMIT
PFM ILIM
RESET
SOFT_RESET
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21
FAN53745
REGISTER DETAILS
Table 4. REGISTER DETAILS − 0X00 PRODUCT ID_REV
0x00 Product ID_REV
Default = 00000001
Description
Bit
Name
Default
Type
7:4
Product ID
0000
Read
Code represents part number
Code
<<Effect>>
−
0000
0001
FAN53745
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3:0
Silicon Revision
0001
Read
Represents silicon revision
Code
0000
0001
….
Revision
Initial Silicon
Increment register with each iteration
….
1111
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22
FAN53745
Table 5. REGISTER DETAILS − 0X01 FAULT FLAGS
0x01 FAULT FLAGS
Default = 00000000
Description
Bit
7:5
4
Name
UNUSED
Default
Type
STARTUP TIMEOUT FAULT
0
R/CLR Displays startup timeout fault status. This indicator is latched when
startup timeout occurs and causes a fault. The flag is cleared upon
read.
Code
Start Up Time−Out Fault
No startup timeout fault occurred
A startup timeout fault occurred
0
1
3
2
1
0
UVLO FAULT
OVER TEMP FAULT
SHORT FAULT
ILIM FAULT
0
0
0
0
R/CLR Displays UVLO fault status. This indicator is latched when UVLO
occurs and causes a fault. The flag is cleared upon read.
Code
Under Voltage Fault Occurance
No UVLO fault occurred
0
1
A UVLO fault occurred
R/CLR Displays over temp fault status. This indicator is latched when over
temp occurs and causes a fault. The flag is cleared upon read.
Code
Start Up Time−Out Fault
No over temp fault
0
1
An over temp fault occurred
R/CLR Displays Vout short fault status. This indicator is latched when Vout
short occurs and causes a fault. The flag is cleared upon read.
Code
Vout Short Fault
The output has not shorted
The output was shorted
0
1
R/CLR During PWM operation, if the peak current limit is hit continuously for
500 ꢀ s, a fault is generated. The flag is cleared upon read.
Code
Vout Short Fault
The output has not shorted
The output was shorted
0
1
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23
FAN53745
Table 6. REGISTER DETAILS − 0X02 STATUS
0x02 STATUS
Default = 00010000
Description
Bit
7
Name
UNUSED
READY
Default
Type
6
0
Read
Reset condition: 0
Code
DEVICE READY
0
Indicates that either the device is not in Idle
mode or that there is a UVLO or over
temperature fault.
1
Indicates that the device is in IDLE mode; that
the input voltage is good and the die
temperature is within safe operating range.
5
PASS−THRU OPERATION
0
Read
Reset condition: 0
The Pass−Thru Operation bit gives the status of the converter.
Code
State of Operation
0
Converter functioning in PFM or PWM
operation.
1
Converter is in pass−thru mode
4
3
PFM_PWM
1
0
Read
Read
Reset condition: 0
This bit indicates the device is operating in PFM mode or PWM mode.
Code
PFM or PWM Switching
PFM operation
0
1
Device is operating in fixed frequency PWM
UVLO
Displays UVLO comparator status.
Code
UVLO Status
0
Input voltage is good
1
The input voltage is presently below the
UVLO threshold
2
1
OVER TEMP
0
0
Read
Read
Displays over temp comparator status.
Code
Die Temperature Status
0
1
The die temperature is safe for operation
The die is too hot to operate
VOUT SHORT
Displays Vout short comparator status.
Code
Output Shorted
0
1
No Vout short fault
The output is presently shorted or is in a state
of recovery after a short
This bit will be cleared when the buck is disabled.
Displays over current comparator status.
0
CURRENT LIMIT
0
Read
Code
Current Limit Detect
0
1
No over current fault
The buck converter is presently hitting peak
current limit
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24
FAN53745
Table 7. REGISTER DETAILS − 0X03 MODE
0x03 MODE
Default = 00001111
Description
Bit
Name
Default
Type
7
ENABLE2
0
R/W
This register enables/disables the buck regulator. Setting a code 0
shutdowns the device, where as code 1 enables the device.
Code
Effect
0
1
Buck Converter disabled
Buck Converter enabled
6
5
FORCE_PWM
0
0
R/W
R/W
Forces the part to operate in PWM mode regardless of the load cur-
rent.
Code
Mode
Auto (PFM/PWM depending on load current)
Force PWM
0
1
V_I_LIMIT_LOCK
Reset condition: 0
Code
LOCK
0
VMIN, VMAX, PFM and PWM Ilimit levels are
not locked.
1
Locks the minimum (VMIN),
Maximum(VMAX) voltages and PFM and
PWM current limits that the device can be
programmed to.
4
SS TIMEOUT
DVS EN
DVS
0
R/W
R/W
R/W
This register activates/deactivates the soft start time−out timer.
Code
Status of Soft Start Timer
0
The converter will continuous attempt to
reach output regulation.
1
A timer is activated when the converter is
enabled. If the converter output fails to reach
regulation in 2ms, a fault will be declared.
3
1
Reset condition: 0
This register bit enables/disables the DVS functionality
Code
DVS Enable
0
1
DVS operation is disabled
DVS will be performed per Mode Control
register bits 2:0
2:0
111
Reset condition: 0
DVS rate control register bits
Code
000
001
010
011
100
101
110
111
Voltage Scaling Rate
0.5 mV/ꢀ s
1.0 mV/ꢀ s
1.5 mV/ꢀ s
2.0 mV/ꢀ s
2.5 mV/ꢀ s
3.5 mV/ꢀ s
5.0 mV/ꢀ s
10 mV/ꢀ s
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25
FAN53745
Table 8. REGISTER DETAILS − 0X04 VSEL
0x04 SEL
Default = 10111001
Description
Bit
Name
Default
Type
7:0
BUCK_VOUT
10111001
R/W
Sets the buck regulation target voltage.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
1.510 V
1.520 V
1.530 V
1.540 V
1.550 V
1.560 V
1.570 V
1.580 V
1.590 V
1.600 V
1.610 V
1.620 V
1.630 V
1.640 V
1.650 V
1.660 V
1.670 V
1.680 V
1.690 V
1.700 V
1.710 V
1.720 V
1.730 V
1.740 V
1.750 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
2.030
2.040
2.050
2.060
2.070
2.080
2.090
2.100
2.110
2.120
2.130
2.140
2.150
2.160
2.170
2.180
2.190
2.200
2.210
2.220
2.230
2.240
2.250
2.260
2.270
2.280
2.290
2.300
2.310
2.320
2.330
2.340
2.350
2.360
2.370
2.380
2.390
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
2.670
2.680
2.690
2.700
2.710
2.720
2.730
2.740
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
2.860
2.870
2.880
2.890
2.900
2.910
2.920
2.930
2.940
2.950
2.960
2.970
2.980
2.990
3.000
3.010
3.020
3.030
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
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26
FAN53745
Table 8. REGISTER DETAILS − 0X04 VSEL (continued)
0x04 SEL
Default = 10111001
Description
Bit
Name
Default
Type
Hex
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
2.400
2.410
2.420
2.430
2.440
2.450
2.460
2.470
2.480
2.490
2.500
2.510
2.520
2.530
2.540
2.550
2.560
2.570
2.580
2.590
2.600
2.610
2.620
2.630
2.640
2.650
2.660
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
3.040
3.050
3.060
3.070
3.080
3.090
3.100
3.110
3.120
3.130
3.140
3.150
3.160
3.170
3.180
3.190
3.200
3.210
3.220
3.230
3.240
3.250
3.260
3.270
3.280
3.290
3.300
7:0
BUCK_VOUT
10111001
R/W
25
26
27
28
29
2A
2B
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.760 V
1.770 V
1.780 V
1.790 V
1.800 V
1.810 V
1.820 V
1.830 V
1.840 V
1.850 V
1.860 V
1.870 V
1.880 V
1.890 V
1.900 V
1.910 V
1.920 V
1.930 V
1.940 V
1.950 V
1.960 V
1.970 V
1.980 V
1.990 V
2.000 V
2.010 V
2.020 V
2
2
2
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
www.onsemi.com
27
FAN53745
Table 9. REGISTER DETAILS − 0X05 VMIN
0x05 VMIN
Default = 01001011
Description
Bit
Name
Default
Type
7:0
VOUT_MIN
01001011
R/W
Sets the minimum voltage the buck can be programmed to.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
1.510 V
1.520 V
1.530 V
1.540 V
1.550 V
1.560 V
1.570 V
1.580 V
1.590 V
1.600 V
1.610 V
1.620 V
1.630 V
1.640 V
1.650 V
1.660 V
1.670 V
1.680 V
1.690 V
1.700 V
1.710 V
1.720 V
1.730 V
1.740 V
1.750 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
2.030
2.040
2.050
2.060
2.070
2.080
2.090
2.100
2.110
2.120
2.130
2.140
2.150
2.160
2.170
2.180
2.190
2.200
2.210
2.220
2.230
2.240
2.250
2.260
2.270
2.280
2.290
2.300
2.310
2.320
2.330
2.340
2.350
2.360
2.370
2.380
2.390
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
2.670
2.680
2.690
2.700
2.710
2.720
2.730
2.740
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
2.860
2.870
2.880
2.890
2.900
2.910
2.920
2.930
2.940
2.950
2.960
2.970
2.980
2.990
3.000
3.010
3.020
3.030
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
www.onsemi.com
28
FAN53745
Table 9. REGISTER DETAILS − 0X05 VMIN (continued)
0x05 VMIN
Default = 01001011
Description
Bit
Name
Default
Type
Hex
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
2.400
2.410
2.420
2.430
2.440
2.450
2.460
2.470
2.480
2.490
2.500
2.510
2.520
2.530
2.540
2.550
2.560
2.570
2.580
2.590
2.600
2.610
2.620
2.630
2.640
2.650
2.660
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
3.040
3.050
3.060
3.070
3.080
3.090
3.100
3.110
3.120
3.130
3.140
3.150
3.160
3.170
3.180
3.190
3.200
3.210
3.220
3.230
3.240
3.250
3.260
3.270
3.280
3.290
3.300
7:0
VOUT_MIN
01001011
R/W
25
26
27
28
29
2A
2B
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.760 V
1.770 V
1.780 V
1.790 V
1.800 V
1.810 V
1.820 V
1.830 V
1.840 V
1.850 V
1.860 V
1.870 V
1.880 V
1.890 V
1.900 V
1.910 V
1.920 V
1.930 V
1.940 V
1.950 V
1.960 V
1.970 V
1.980 V
1.990 V
2.000 V
2.010 V
2.020 V
2
2
2
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
www.onsemi.com
29
FAN53745
Table 10. REGISTER DETAILS − 0X06 MAX
0x06 MAX
Default = 11111111
Description
Bit
Name
Default
Type
7:0
VOUT_MAX
11111111
R/W
Sets the maximum voltage the buck can be programmed to.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
1.510 V
1.520 V
1.530 V
1.540 V
1.550 V
1.560 V
1.570 V
1.580 V
1.590 V
1.600 V
1.610 V
1.620 V
1.630 V
1.640 V
1.650 V
1.660 V
1.670 V
1.680 V
1.690 V
1.700 V
1.710 V
1.720 V
1.730 V
1.740 V
1.750 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
2.030
2.040
2.050
2.060
2.070
2.080
2.090
2.100
2.110
2.120
2.130
2.140
2.150
2.160
2.170
2.180
2.190
2.200
2.210
2.220
2.230
2.240
2.250
2.260
2.270
2.280
2.290
2.300
2.310
2.320
2.330
2.340
2.350
2.360
2.370
2.380
2.390
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
2.670
2.680
2.690
2.700
2.710
2.720
2.730
2.740
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
2.860
2.870
2.880
2.890
2.900
2.910
2.920
2.930
2.940
2.950
2.960
2.970
2.980
2.990
3.000
3.010
3.020
3.030
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
www.onsemi.com
30
FAN53745
Table 10. REGISTER DETAILS − 0X06 MAX (continued)
0x06 MAX
Default = 11111111
Description
Bit
Name
Default
Type
Hex
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
2.400
2.410
2.420
2.430
2.440
2.450
2.460
2.470
2.480
2.490
2.500
2.510
2.520
2.530
2.540
2.550
2.560
2.570
2.580
2.590
2.600
2.610
2.620
2.630
2.640
2.650
2.660
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
3.040
3.050
3.060
3.070
3.080
3.090
3.100
3.110
3.120
3.130
3.140
3.150
3.160
3.170
3.180
3.190
3.200
3.210
3.220
3.230
3.240
3.250
3.260
3.270
3.280
3.290
3.300
7:0
VOUT_MAX
11111111
R/W
25
26
27
28
29
2A
2B
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.760 V
1.770 V
1.780 V
1.790 V
1.800 V
1.810 V
1.820 V
1.830 V
1.840 V
1.850 V
1.860 V
1.870 V
1.880 V
1.890 V
1.900 V
1.910 V
1.920 V
1.930 V
1.940 V
1.950 V
1.960 V
1.970 V
1.980 V
1.990 V
2.000 V
2.010 V
2.020 V
2
2
2
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
www.onsemi.com
31
FAN53745
Table 11. REGISTER DETAILS − 0X07 SHUTOWN
0x07 SHUTDOWN
Default = 0000100
Description
Bit
7:3
2:1
Name
UNUSED
Default
Type
DISCHARGE SEL
10
R/W
This register sets the strength of the pulldown resistor.
Code
00
Strength of Pulldown
OPEN
01
200
100
50
ꢁ
ꢁ
10
11
ꢁ
0
DISCHARGE
0
R/W
This register activates/deactivates the internal pulldown resistor. Set-
ting to Code 1, the pulldown is active when ENABLE goes from 1 to 0
and on any negative V
transitions.
OUT
Code
Status of Pulldown
0
1
Pulldown not used (OFF)
Pulldown active during transition
Table 12. REGISTER DETAILS − 0X08 ILIMIT
0x08 ILIMIT
Default = 10101101
Description
Bit
Name
Default
Type
Reset condition: 0
7:4
PFM ILIM
1010
R/W
Sets the open loop peak PFM current limit
PFM Peak Current Limit
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
500 mA
555 mA
610 mA
665 mA
720 mA
775 mA
830 mA
885 mA
940 mA
995 mA
1050 mA
1105 mA
1160 mA
1215 mA
1270 mA
1325 mA
www.onsemi.com
32
FAN53745
Table 12. REGISTER DETAILS − 0X08 ILIMIT (continued)
0x08 ILIMIT
Name
PWM ILIM
Default = 10101101
Description
Bit
Default
Type
Sets the open loop peak inductor current limit thresholds. The Range
is from 440 mA to 2090 mA in 110 mA steps.
3:0
1101
R/W
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PWM Peak Current Limit
440 mA
550 mA
660 mA
770 mA
880 mA
990 mA
1100 mA
1210 mA
1320 mA
1430 mA
1540 mA
1650 mA
1760 mA
1870 mA
1980 mA
2090 mA
Table 13. REGISTER DETAILS − 0X09 RESET
0x09 RESET
Default = 00000000
Bit
Name
Default
Type
Description
2
7:0
SOFT_RESET
00000000
Write
The software reset register allows all I C settings to be reverted to
POR defaults when 0x45h code is written to it.
www.onsemi.com
33
FAN53745
APPLICATION GUIDELINES
Table 14. PRIMARY COMPONENTS
Component
Manufacturer
Murata
Part Number
Description
Case Size
Voltage Rating
CIN
L
GRM035R60J475ME15D
CIGT201208EHR47MNE
4.7 ꢀ F
0201/0603 (0.6 mm x 0.3 mm)
0805/2012 (2 mm x 1.2 mm)
6.3 V
Samsung
0.47 ꢀ H
−
ISAT = 4.3 A
IRAT = 3.9 A
RDC = 31
ꢁ
COUT
Murata
GRM155R60J106ME47D
2x 10 ꢀ F
0402/1005 (1.0 mm x 0.5 mm)
6.3 V
Input Capacitor Considerations
least 80% of its value at I
. It is recommended to
LIM(PK)
The 2.2 ꢀ F ceramic 0402 (1005 metric) input capacitor
should be placed as close as possible between the VIN pin
and GND to minimize the parasitic inductance. If a long wire
is used to bring power to the IC, additional “bulk”
capacitance (electrolytic or tantalum) should be placed
select an inductor where its saturation current is above the
value.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but because ꢃI increases,
I
LIM(PK)
between C and the power source lead to reduce the ringing
the RMS current increases, as do the core and skin effect
losses.
IN
that can occur between the inductance of the power source
leads and C .
2
IRMS + SQRT (IOUT(DC)
)
ꢃ I2ń12)
IN
(eq. 3)
The effective capacitance value decreases as V
increases due to DC bias effects.
IN
The increased RMS current produces higher losses
through the R of the IC MOSFETs, as well as the
DS(ON)
Inductor Considerations
inductor DCR. Increasing the inductor value produces lower
RMS currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current and higher DCR.
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects average current limit,
the PWM−to−PFM transition point, output voltage ripple,
and efficiency.
Output Capacitor Considerations
The ripple current (ꢃI) of the regulator is:
FAN53745 uses two 10 ꢀ F 0402 (1005 metric) for an
output capacitor. The effective capacitor of ceramic
capacitors decrease as the bias voltage increases. To
overcome this increasing the output capacitor has no effect
on loop stability and therefore the COUT can be increased
to reduce the output voltage ripple or to improve transient
response. Output voltage ripple is defined as:
ꢃ
I
(
V
ń
V
)
@
(
(
V
*
V
)
ń
(
L
@
f
s
w
)
)
O
U
T
I
N
I
N
O
U
T
(eq. 1)
The maximum average load current, I
, is
MAX(LOAD)
related to the peak current limit, I
, by the ripple
LIM(PK)
current, given by:
IMAX(LOAD) + ILIM(PK)
* ꢃ Iń2
(eq. 2)
The FAN53745 is optimized for operation with
L = 0.47ꢂ ꢀH. The inductor should be rated to maintain at
2
ꢃ V
+ ꢃ I @ [(f
@ C
@ ESR ń(2 @ D @ (1 * D))) ) (1ń(8 @ f
@ C
))]
OUT
L
SW
OUT
SW
OUT
(eq. 4)
www.onsemi.com
34
FAN53745
Recommended Layout
Figure 43. Recommended Placement
Layout Considerations
To minimize spikes at V
PACKAGE INFORMATION
, C
OUT
must be placed as
OUT
close as possible to PGND and VOUT, as shown in
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground pour
should be set to fill all available PCB surface area and tied
to internal layers with a cluster of thermal via.
Table 15. PACKAGE DIMENSIONS
Product
D
E
FAN53745
1.50 mm +/− 30 ꢀ m 0.94 mm +/− 30 ꢀ m
1. Typical height to be 0.55 mm.
2. Dimensions shown in the table below are approximations.
www.onsemi.com
35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6, 0.94x1.50x0.581
CASE 567WU
ISSUE O
DATE 17 JUL 2018
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON93753G
WLCSP6, 0.94x1.50x0.581
PAGE 1 OF 1
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