FAN53880UC002X_技术文档

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FAN53880

One Buck, One Boost and

Four LDO PMIC

General Description

The FAN53880 is a low quiescent current PMIC for mobile power

applications. The PMIC contains one buck, one boost, and four low

noise LDOs.

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The buck and boost converters can operate within a wide supply

range of 2.5 V to 5.5 V. At moderate and light loads, Pulse Frequency

Modulation (PFM) reduces current consumption while maintaining

excellent transient response during load swings. At higher loads, the

converters automatically switch to Pulse Width Modulation (PWM)

control.

WLCSP25

CASE 567QT

The FAN53880 is available in a 25−bump, 0.4 mm pitch,

Wafer−Level Chip−Scale Package (WLCSP).

Features

MARKING DIAGRAM

• Programmable Start−Up/Down Sequencing

• Programmable Output Voltages

• Soft−Start (SS) Inrush Current Limiting

• Fault Protection with Interrupt Reporting

♦ UVLO, OCP, OVP, UVP and OTP

12KK

XYZ

1

• Low Current Standby and Shutdown Modes

12

KK

X

Y

Z

= Alphanumeric Device Marking

= Lot Run Code

= Alphabetical Year Code

= 2−weeks Date Code

= Assembly Plant Code

• Buck Converter:

♦ Input Voltage Range: 2.5 V to 5.5 V

♦ Digitally Programmable Voltage Range: 0.6 V to 3.3 V

♦ 1200 mA Output Current Capability

♦ 95% Efficiency

• Boost Converter:

♦ Input Voltage Range: 2.5 V to 5.5 V

♦ Digitally Programmable Voltage Range: 3.0 V to 5.7 V

♦ 1000 mA Output Current Capability

♦ 95% Efficiency

• Four LDOs:

♦ Input Voltage Range: 1.9 V to 5.5 V

♦ Digitally Programmable Voltage Range: 0.8 V to 3.3 V

♦ 300 mA Output Current Capability

Applications

• Smartphones and Tablets

• Compact Camera Modules

• USB On−The−Go

1

Publication Order Number:

May, 2019 − Rev. 2

FAN53880/D

FAN53880

Application Diagram

PVIN

AVIN

SW1

L1

CPVIN

CBUCK

PGND1

FB1

CAVIN

CVIN12

CVIN3

LDO1

AGND

VIN12

CLDO1

CLDO3

LDO2

CLDO2

LDO3

LDO4

VIN3

VIN4

FAN53880

CVIN4

CLDO4

VBST

SW2

CBST

L2

PGND2

CBSTIN

HWEN

SCL

BSTEN

N/C

SDA

N/C

INTB

DGND

Figure 1. Application Diagram

PART NUMBERING

Table 1. ORDERING INFORMATION

Buck

LDO1,2

LDO3,4

Boost

I2C

Address

Temperature

Range

Packing

Method

Device

Marking

V

OUT

V

OUT

V

OUT

V

OUT

Part Number

Package

FAN53880UC001X*

1.1 V

2.8 V

1.8 V

5.0 V

7’h35

−40°C to 85°C 25−Bump Tape and

LT

†

WLCSP

Reel

FAN53880UC002X

1.1 V

2.8 V

1.8 V

5.0 V

7’h35

−40°C to 85°C 25−Bump Tape and

LW

†

WLCSP

Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

*Not recommended for new designs.

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2

FAN53880

PRODUCT PIN ASSIGNMENTS

Pin Configuration

SW1

PVIN

VBST

SW2

VBST

PVIN

SW1

A5

A1

A2

A3

A4

A3

A2

A1

INTB

PGND1

FB1

BSTEN

PGND2

BSTEN

FB1

PGND1

INTB

B5

B1

B2

B3

B4

B3

B2

B1

N/C

HWEN

DGND

SDA

SCL

SDA

DGND

HWEN

N/C

C5

C1

C2

C3

C4

C3

C2

C1

VIN4

AVIN

VIN12

N/C

AVIN

VIN3

N/C

VIN3

D1

D5

D1

D2

D3

D4

D3

D2

LDO3

AGND

LDO2

LDO1

LDO2

AGND

LDO3

LDO4

E5

E1

E2

E3

E4

E3

E2

E1

Figure 2. Pin Configuration

Pin Descriptions

Table 2. PIN DEFINITION

A1

A2

Pin Name

SW1

Description

Switching node of the buck converter. Tie one lead of the inductor to this pin.

Input power for the buck and boost converter. Bypass this pin with C close to the device pin.

PVIN

The voltage must be kept within 25 mV of AV

.

IN

A3

A4, A5

B1

VBST

SW2

Boost output node. Locate C

close to this pin

BST

Switching node for the boost converter.

Power ground connection for the buck converter. Connect directly to ground plane.

Feedback pin for the buck converter. Connect to C and keep trace away from noisy circuitry.

PGND1

FB1

B2

BUCK

B3

BSTEN

Enables the boost and critical circuits associated with the boost operation when asserted high. The BSTEN

pin has an internal 2.8 MW pull−down and should always be connected to a logic high or low.

Note: HWEN does not need to be high for Boost operation when BSTEN is high.

B4

B5

C1

C2

INTB

PGND2

N/C

I2C interrupt pin is active low indicating that an interrupt event has occurred.

Power ground connection for the Boost converter. Connect directly to ground plane.

This pin is a no−connect within the device. It is recommended to tie this pin to ground, but is not necessary.

HWEN

HWEN pin is used to enable basic circuits necessary for controlling the power converter outputs. The HWEN

pin has an internal 5 MW pull−down and should always be connected to a logic high or low.

C3

C4

C5

D1

D2

D3

DGND

SDA

Digital/Analog ground connection. Tie to inner layer power plane through via.

I2C Data pin. Node should be tied high through a pull up resistor.

I2C Clock pin. Node should be tied high through a pull up resistor.

SCL

VIN4

VIN3

AVIN

Input power pin for LDO4. Place C

Input power pin for LDO3. Place C

as close to this pin as possible.

VIN4

VIN3

Analog power pin. Route trace from battery side of the boost inductor (L2) to the AV pin. Connect the

IN

C

capacitor as close as possible to the pin. To create a low pass filter, a series resistor may be added

AVIN

between the inductor and C

. The voltage must be kept within 25 mV of PV to ensure system stability.

AVIN

IN

D4

D5

E1

E2

E3

E4

E5

N/C

This pin is a no−connect within the device. It is recommended to tie this pin to ground, but is not necessary.

This is the input power pin for LDO1 and LDO2. Place C as close to this pin as possible.

VIN12

LDO4

LDO3

AGND

LDO2

LDO1

VIN12

This is the output pin for LDO4. Place C

This is the output pin for LDO3. Place C

as close to this pin as possible.

LDO4

LDO3

Analog ground is the analog circuitry ground. Tie this pin to the analog ground plane.

This is the output pin for LDO2. Place C

This is the output pin for LDO1. Place C

as close to this pin as possible.

LDO2

LDO1

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3

FAN53880

PRODUCT BLOCK DIAGRAM

Block Diagram

PVIN

Buck Control

Core Analog

Block

AVIN

SW1

N/C

PGND1

AGND

FB1

VIN12

LDO1

LDO2

LDO1

Control

LDO2

Control

LDO3

LDO4

VIN3

VIN4

LDO3

Control

LDO4

Control

VBST

SW2

Boost Control

Boost Enable

BSTEN

N/C

PGND2

HWEN

Thermal Protection

Digital Control

I2C

SCL

SDA

INTB

DGND

Figure 3. Block Diagram

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4

FAN53880

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Conditions

Min

−0.3

− 0.3

Typ

Max

Units

V

IN

Input Voltage

AV , PV , V

, V

IN3

and V

IN4

(Note 1)

IN

IN12

V

SW1

V

SW2

Voltage on SW1 Pin

Voltage on SW2 Pin

SDA and SCL Pins

INTB Pins

V

CTRL

V

INTB

AV

V

IN

other Pins

(Note 1)

V

ESD

Electrostatic Discharge Protection

Level

Human Body Model

Charged Device Model

2.0

kV

V

500

T

Junction Temperature

Storage Temp

−40

+150

°C

J

T

STG

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Lesser of 6 V or AV + 0.3 V.

IN

Table 4. THERMAL PROPERTIES

Symbol

Parameter

Typical

Unit

q

Junction−to−Ambient Thermal Resistance

58

°C/W

JA

NOTE: Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with two−layer 2s2p

boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T at a

J(max)

given ambient temperature T .

A

Table 5. RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Conditions

Min

2.5

1.9

Typ

Max

5.5

Units

AP

Supply Voltage Range

AV , PV

IN

V

VIN

IN

V

IN12

V

5.5

IN12

IN3

V

IN3

5.5

V

IN4

5.5

V

IN4

P

Power Dissipation

PD = (125°C − 85°C) / 58°C/W = 0.69 W

0.69

85

W

D

T

A

Operating Ambient Temperature

Junction Temperature

−40

°C

T

125

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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5

FAN53880

Table 6. ELECTRICAL CHARACTERISTICS

Minimum and maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V

+ 350 mV and PV < V

− 250 mV, V

= 2.5 V

= 3.0 V

IN

BUCK

IN

BST

IN12

to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

+ 150 mV, V

= 0.6 V to 3.3 V, V

IN

LDO1/2

IN3

IN4

IN3

IN4

LDO3/4

BUCK

BST

to 5.7 V, V

, V

LDO2

, V

LDO3

and V

= 0.8 V to 3.3 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T = 25°C,

LDO1

LDO4

A

AV , PV , V

= 3.8 V, V , V

= 1.95 V, V

= 1.1 V, V

= 5.0 V, V

and V

= 2.8 V, V

and V

= 1.8 V.

IN

IN12

IN3

IN4

BUCK

BST

LDO1

LDO2

LDO3

LDO4

Symbol

Parameter

Conditions

Min

Typ

Max

Units

POWER SUPPLIES UVLO

V

Under−Voltage Lockout

Threshold

Rising AV or V

IN12

2.30

2.15

1.80

1.70

2.35

2.25

1.85

1.75

2.45

2.30

1.95

1.80

V

VIN UVLO_RISE

VIN UVLO_FALL

IN

Falling AV or V

IN

IN12

V

Rising V and V

IN3 IN4

VIN3/4 UVLO_RISE

VIN3/4 UVLO_FALL

V

Falling V and V

IN3 IN4

BUCK EC

POWER SUPPLIES

IQ

PFM Quiescent Current

Total current on PV and AV when AV

IN

36

mA

BK_PFM

IN

= PV = VHWEN, BUCK_EN bit = 1, PFM

IN

Mode, Non Switching, No Load, all other

converters disabled.

R

Output Discharge Resistance

80

100

120

W

BK_DIS

PFM e PWM THRESHOLDS

I

where part transitions into

value where part transi-

OUT

50

mA

BK_PFM

OUT

PFM

I

120

BK_PWM

tions into PWM

BUCK V

ACCURACY

OUT

VO

PFM Output Voltage Accuracy

PWM Output Voltage Accuracy

V

= 0.6 V, AV = PV = 3.8 V, PFM

OUT

−3

−2

−3

−2

3

2

3

2

%

BK_ACC

OUT

IN

= 0 A

IN

Mode, I

AV = PV = 3.8 V, No Load, PFM Mode,

IN

V

OUT

= 1.0125 V to 3.3 V

V

= 0.6 V, AV = PV = 3.8 V, PWM

OUT

IN

= 0 A

IN

Mode, I

OUT

AV = PV = 3.8V, No Load, PWM Mode,

IN

V

OUT

= 1.0125 V to 3.3 V

CURRENT LIMIT

ILIM

Peak Inductor Current Limit

Switching Frequency

Programmed to support 1.2 A DC load

1600

2.25

1900

2.5

2200

2.75

mA

BK

REGULATOR

F

PWM, I

= 0 A, AV = PV = 3.8 V,

MHz

BK_SW

OUT

IN

V

= 1.1 V

OUT

RDS

PMOS Resistance Ball−to−Ball AP

NMOS Resistance Ball−to−Ball AP

= V = 3.8 V, Temp = 25°C

0.125

0.085

1.1

0.200

0.140

3.3

W

V

ON BK_P

ON BK_N

BK_RNG

VIN

GS

= V = 3.8 V, Temp = 25°C

GS

VO

Buck Output Voltage Range

When V

+ 300 mV < AV & PV

IN

0.6

OUT

IN

BUCK OUTPUT PROTECTION

OVP

Rising Over Voltage Output

Threshold

V

= 3.8 V, V = 1.1 V,

OUT

Vtarget Vtarget Vtarget

x 1.17 x 1.2 x 1.23

V

BK_RS

IN

= 2.85 V

V

= 0.6 V

Vtarget Vtarget Vtarget

x 1.15 x 1.2 x 1.25

OUT

OVP

UVP

Falling Over Voltage Output

Threshold

= 0.6 V to 3.300V

= 0.6 V

Vtarget Vtarget Vtarget

x 1.04 x 1.10 x 1.14

BK_FL

Falling Under Voltage Output

Threshold

Vtarget Vtarget Vtarget

x 0.83 x 0.90 x 0.97

BK_FL

= 3.8 V, V

= 1.1 V, 2.85 V

Vtarget Vtarget Vtarget

x 0.86 x 0.90 x 0.93

IN

OUT

UVP

Rising Under Voltage Output

Threshold

= 0.6 V to 3.3 V

Vtarget Vtarget Vtarget

x 0.90 x 0.95 x 0.99

BK_RS

OUT

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6

FAN53880

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V

+ 350 mV and PV < V

− 250 mV, V

= 2.5 V

= 3.0 V

IN

BUCK

IN

BST

IN12

to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

+ 150 mV, V

= 0.6 V to 3.3 V, V

IN

LDO1/2

IN3

IN4

IN3

IN4

LDO3/4

BUCK

BST

to 5.7 V, V

, V

LDO2

, V

LDO3

and V

= 0.8 V to 3.3 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T = 25°C,

LDO1

LDO4

A

AV , PV , V

= 3.8 V, V , V

= 1.95 V, V

= 1.1 V, V

= 5.0 V, V

and V

= 2.8 V, V

and V

Typ

40

= 1.8 V.

IN

IN12

IN3

IN4

BUCK

BST

LDO1

LDO2

LDO3

LDO4

Symbol

Parameter

Conditions

Min

32

Max

Units

OVP

Over Voltage Output Protection

Timer

V

= 2.85 V, V

held at 3.65 V,

held at 2.05 V,

56

ms

BK_TMR

OUT_Target

OUT

INTB going high trigger

UVP

Under Voltage Output Protec-

tion Timer

V

= 2.85 V, V

32

40

56

ms

BK_TMR

OUT_Target

OUT

Time to Output Disabled

BOOST EC

POWER SUPPLIES

IQ

Quiescent Current

Total current on PV and AV ,

IN

32

44

90

mA

BST_PFM

IN

V

= 5 V when V

= AV , VHWEN

OUT

BSTEN IN

= 0, PFM Mode, Non Switching, No Load,

all other converters disabled.

IQ

IQ in Auto Pass−Thru Mode

Total current on PV and AV when

39

18

mA

BST PT

IN

V

= AV , VHWEN = 0, No Load, all

BSTEN

IN

other converters disabled.

IQ

IQ when part is in Forced

Pass−Thru Mode

Total current on PV and AV when AV

BST_FPT

IN

= PV = V

= 3.8 V,

IN

BSTEN

VHWEN = 0, BST_MODE bit = 1,

No Load, all other converters disabled.

R

Output Discharge Resistance

80

100

120

W

BST_DCHG

PFM e PWM THRESHOLDS

PFM Mode I

I

Threshold

100

130

mA

BST_PFM

OUT

I

PWM Mode I

OUT

BST_PWM

BOOST V

ACCURACY

OUT

VO

PFM Output Voltage Accuracy

PWM Output Voltage Accuracy

V

= 3.8 V, No Load, PFM Mode

= 3.8 V, No Load, PWM Mode

−3

3

%

BST_ACC

IN

CURRENT LIMIT

I

Peak Inductor Current Limit

PWM Switching Frequency

Programmed to support 1 A DC load

3.0

3.5

4.0

A

LIMBST

REGULATOR

F

V

IN

= 3.8 V

2.25

2.5

65

2.75

120

100

5.7

MHz

mW

V

SW_BST

RDS

PMOS Resistance Ball−to−Ball Temp = 25°C

NMOS Resistance Ball−to−Ball Temp = 25°C

ON BST_P

ON BST_N

BST_RNG

50

VO

Boost Output Voltage Range

When PV < V

and 2.5 V ≤ PV /AV

3.0

5.0

IN

BST

IN

≤ 5.5 V

BOOST OUTPUT PROTECTION

OVP

UVP

Rising Over Voltage Output

Threshold

V

= 3.8 V, V

= 5.0 V

Vtarget Vtarget Vtarget

x 1.16 x 1.2 x 1.22

V

BST_RS

AVIN

OUT

Falling Over Voltage Output

Threshold

Vtarget Vtarget Vtarget

x 1.07 x 1.1 x 1.12

BST_FL

Falling Under Voltage Output

Threshold

V

AVIN

= 3.8 V, V

Vtarget Vtarget Vtarget

x 0.78 x 0.80 x 0.82

V

BST_FL

OUT

UVP

Rising Under Voltage Output

Threshold

Vtarget Vtarget Vtarget

V

BST_RS

BST_TMR

x 0.88

x 0.90

x 0.93

OVP

UVP

Over Voltage Output Protection

Timer

V

= 5.0 V, V

held at 6.25 V,

held at 4.00 V,

OUT

32

40

56

ms

OUT_Target

OUT

INTB going high trigger

Under Voltage Output Protec-

tion Timer

V

= 5.0 V, V

32

40

56

OUT_Target

Time to Output Disabled

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7

FAN53880

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V

+ 350 mV and PV < V

− 250 mV, V

= 2.5 V

= 3.0 V

IN

BUCK

IN

BST

IN12

to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

+ 150 mV, V

= 0.6 V to 3.3 V, V

IN

LDO1/2

IN3

IN4

IN3

IN4

LDO3/4

BUCK

BST

to 5.7 V, V

, V

LDO2

, V

LDO3

and V

= 0.8 V to 3.3 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T = 25°C,

LDO1

LDO4

A

AV , PV , V

= 3.8 V, V , V

= 1.95 V, V

= 1.1 V, V

= 5.0 V, V

and V

= 2.8 V, V

and V

= 1.8 V.

IN

IN12

IN3

IN4

BUCK

BST

LDO1

LDO2

LDO3

LDO4

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LDO1/2 EC SPECS

QUIESCENT CURRENT

IQ

Quiescent Current, No Load

I

= 0 A, Combined Current Measured

40

55

mA

L12

OUT

at AV and V

when LDO1 is enabled

IN

IN12

only or LDO2 is enabled only, Buck and

Boost are disabled, VHWEN = AV

IN

VO

LDO Output Voltage Range

Output Voltage Accuracy

Dropout Voltage

When V

+ 300 mV < V and

IN12

0.8

2.8

3.3

+2.0

250

V

L12_RNG

L12_ACC

L12_DO

OUT

2.5 V ≤ V

≤ 5.5 V

VO

I

= 300 mA, AV = V = 3.8 V,

IN12

OUT

−2.0

%

OUT

IN

V

= 0.8 V to 3.3 V

V

= V

− 100 mV, I

OUT_TARGET

=

mV

mA

OUT

OUT_TARGET

OUT

300 mA, V

= 2.8 V

IO

Max load current

V

OUT

V

IN12

+ 0.3 V < V and

IN12

= 2.5 V to 4.5 V

300

MAX_L12

CURRENT LIMIT

I

Current Limit

V

+ 500 mV < V and

IN12

150

360

180

420

210

480

mA

LIM_L12

OUT

2.5 V ≤ V

≤ 4.5 V

IN12

V

OUT

+ 500 mV < V

and

IN12

2.5 V ≤ V

≤ 4.5 V

IN12

OUTPUT PROTECTION

OVP

UVP

Rising Over Voltage Output

Threshold

V

= V

= 3.8 V, V

= 2.8 V

Vtarget Vtarget Vtarget

x 1.17 x 1.2 x 1.23

V

L12_RS

AVIN

IN1/2

OUT

Falling Over Voltage Output

Threshold

V

AVIN

= V

= 2.8 V

Vtarget Vtarget Vtarget

x 1.07 x 1.1 x 1.12

L12_FL

Falling Under Voltage Output

Threshold

V

AVIN

Vtarget Vtarget Vtarget

x 0.77 x 0.8 x 0.82

V

L12_FL

UVP

Rising Under Voltage Output

Threshold

V

AVIN

Vtarget Vtarget Vtarget

V

L12_HS

x 0.88

x 0.9

x 0.93

OVP

UVP

Over Voltage Output Protection

Timer

V

= 2.8 V, V

held at 3.5 V,

held at 1.8 V,

OUT

32

40

56

ms

W

L12_TMR

L12_DCHG

OUT_Target

OUT

INTB going high trigger

Under Voltage Output Protec-

tion Timer

V

= 2.8 V, V

32

80

40

56

OUT_Target

Time to Output Disabled

R

Output Discharge Resistance

100

120

LDO3/4 EC SPECS

QUIESCENT CURRENT

IQ Quiescent Current, No Load

I

= 0 A, Combined Current Measured

38

50

mA

L34

OUT

at AV and V

when LDO3 is enabled or

IN

IN3

IN4

AV and V

when LDO4 is enabled.

IN

LDO1, LDO2, Buck and Boost are dis-

abled, VHWEN = AV

IN

VO

LDO3/4 Output Voltage Range LDO3: V

+ 0.15 < V

and V = 1.95

IN3

0.8

1.8

3.3

V

L34_RNG

OUT

IN3

V to 4.5 V, LDO4: V

+ 150 mV < V

OUT

IN4

and V

= 1.95 V to 4.5 V

IN4

VO

Output Voltage Accuracy

Dropout Voltage

I

= 300 mA, AV = 3.8 V, V = 3.8

IN3/4

OUT

−2.5

+2.0

150

%

L34_ACC

OUT

IN

V, V

= 0.8 V to 3.3 V

V

= V

− 100 mV, I =

OUT

OUT_TARGET

mV

mA

L34_DO

OUT

OUT_TARGET

300 mA, V

= 1.8 V

IO

Max load current

V

+ 150 mV < V

and V = 1.95 V

IN3

300

MAX_L34

OUT

IN3

to 4.5 V, LDO4: V

+ 150 mV < V

and

OUT

IN4

V

= 1.95 V to 4.5 V

IN4

www.onsemi.com

8

FAN53880

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V

+ 350 mV and PV < V

− 250 mV, V

= 2.5 V

= 3.0 V

IN

BUCK

IN

BST

IN12

to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

+ 150 mV, V

= 0.6 V to 3.3 V, V

IN

LDO1/2

IN3

IN4

IN3

IN4

LDO3/4

BUCK

BST

to 5.7 V, V

, V

LDO2

, V

LDO3

and V

= 0.8 V to 3.3 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T = 25°C,

LDO1

LDO4

A

AV , PV , V

= 3.8 V, V , V

= 1.95 V, V

= 1.1 V, V

= 5.0 V, V

and V

= 2.8 V, V

and V

= 1.8 V.

IN

IN12

IN3

IN4

BUCK

BST

LDO1

LDO2

LDO3

LDO4

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CURRENT LIMIT

I

Current Limit

V

+ 500 mV < V

and V = 1.95 V

IN3

150

360

80

180

420

100

210

mA

LIM_L34

OUT

IN3

to 4.5 V, LDO4: V

+ 500 mV < V

and

OUT

IN4

V

IN4

= 1.95 V to 4.5 V

V

OUT

+ 500 mV < V

and V = 1.95 V

IN3

480

120

mA

IN3

to 4.5 V, LDO4: V

+ 500 mV < V

and

OUT

IN4

V

IN4

= 1.95 V to 4.5 V

R

Output Discharge Resistance

W

L34_DCHG

OUTPUT PROTECTION

OVP

UVP

Rising Over Voltage Output

Threshold

V

= 3.8 V, V

= 1.95V, V

= 1.8 V Vtarget Vtarget Vtarget

V

L34_RS

AVIN

IN3/4

OUT

x 1.17

x 1.2

x 1.23

Falling Over Voltage Output

Threshold

V

AVIN

= 1.8 V Vtarget Vtarget Vtarget

L34_FL

x 1.07 x 1.1 x 1.12

Falling Under Voltage Output

Threshold

V

AVIN

= 1.8 V Vtarget Vtarget Vtarget

x 0.77 x 0.80 x 0.82

V

L34_FL

UVP

Rising Under Voltage Output

Threshold

V

AVIN

= 1.8 V Vtarget Vtarget Vtarget

V

L34_RS

L34_TMR

OUT

x 0.88

x 0.90

x 0.93

OVP

UVP

Over Voltage Output Protection

Timer

V

= 1.8 V, V

held at 2.25 V,

32

40

56

ms

OUT_Target

OUT

INTB going high trigger

Under Voltage Output Protec-

tion Timer

V

= 1.8 V, V

held at 1.35 V,

OUT

32

40

56

OUT_Target

Time to Output Disabled

I/O LEVELS

V

HWEN Logic Low threshold

HWEN Logic High threshold

BSTEN Logic Low threshold

BSTEN Logic High threshold

0.35

V

IL

V

IH

1.2

V

IN

V

0.25

V

IL

IH

V

AV = 4.5 V;

1.05

1

V

IN

V

IN

R

HWEN and BSTEN Input

Resistance

V

IN

= High or Low

4.4

MW

PD

V

INTB

Isink = 5 mA

= 5.5 V

0.3

0.5

V

OL_INTB

I

V

mA

INTB

IQ CONDITIONS

I

Shutdown Supply Current

Total current on AV when AV = 5.0 V

5

mA

Q AVIN_SD

IN

and all xxx_EN bits = 0, xxx_SEQ bits

=000, HWEN = BSTEN = SDA = SCL =

Low

I

Total current on PV when PV = 5.0 V

1.5

Q PVIN_SD

IN

and all xxx_EN bits = 0, xxx_SEQ bits

=000, HWEN = BSTEN = SDA = SCL =

Low

I

Total current on V

when V

= 5.0 V

Q VIN12_SD

IN12

and all xxx_EN bits = 0, xxx_SEQ bits

=000, HWEN = BSTEN = SDA = SCL =

Low

I

Total current on V

when V

= 5.0 V

Q VIN3_SD

Q VIN4_SD

IN3

and all xxx_EN bits = 0, xxx_SEQ bits

=000, HWEN = BSTEN = SDA = SCL =

Low

Total current on V

when V

= 5.0 V

IN4

and all xxx_EN bits = 0, xxx_SEQ bits

=000, HWEN = BSTEN = SDA = SCL =

Low

www.onsemi.com

9

FAN53880

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V

+ 350 mV and PV < V

− 250 mV, V

= 2.5 V

= 3.0 V

IN

BUCK

IN

BST

IN12

to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

+ 150 mV, V

= 0.6 V to 3.3 V, V

IN

LDO1/2

IN3

IN4

IN3

IN4

LDO3/4

BUCK

BST

to 5.7 V, V

, V

LDO2

, V

LDO3

and V

= 0.8 V to 3.3 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T = 25°C,

LDO1

LDO4

A

AV , PV , V

= 3.8 V, V , V

= 1.95 V, V

= 1.1 V, V

= 5.0 V, V

and V

= 2.8 V, V

and V = 1.8 V.

LDO4

IN

IN12

IN3

IN4

BUCK

BST

LDO1

LDO2

LDO3

Symbol

Parameter

Conditions

Total current on PV , AV , V

Min

Typ

Max

Units

I

Standby Supply Current

, V

IN3

165

190

mA

Q_STBY

IN

IN12

and V

when = 5.0 V and all xxx_EN bits

IN4

= 1 (Except BST_EN), xxx_SEQ bits =000,

AV = PV = VHWEN = V . LDO1−4

IN

BSTEN

on, Buck on, Boost on

I

Sleep Supply Current

Total current on PV , AV , V

, V

IN3

12

20

mA

SLP

IN

IN12

and V

when = 5.0 V and all xxx_EN bits

IN4

= 0, xxx_SEQ bits =000, AV = PV

=

IN

VHWEN, BSTEN = Low. LDO1−4 off,

Buck off, Boost off, No I2C activity

{

2

I C Timing and Performance

V

SDA and SCL Logic Low

threshold

−0.5

0.4

5.5

0.4

V

IL

V

IH

SDA and SCL Logic High

threshold

1.2

V

OL

SDA Logic Low Output

SDA Sink Current

3 mA Sink

V

I

OL

20

mA

kHz

ms

fSCL

tBUF

SCL Clock Frequency

Fast Mode Plus

1000

Bus−Free Time Between STOP Fast Mode Plus

and START Conditions

0.5

tHD;STA

START or Repeated START

Hold Time

Fast Mode Plus

260

ns

tLOW

tHIGH

tSU;STA

tHD;DAT

tSU;DAT

tVD;DAT

tVD;ACK

tR

SCL LOW Period

Fast Mode Plus

Fast Mode−Plus

Fast Mode Plus

Fast Mode Plus, VDD = 1.8 V

Fast Mode Plus

0.5

260

0

ms

ns

pF

SCL HIGH Period

Repeated START Setup Time

Data Hold Time

Data Setup Time

50

Data Valid Time

450

120

Data Valid Acknowledge Time

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

tF

6.55

260

tSU;STO

Ci

SDA and SCL Input Capaci-

tance

10

550

50

Cb

Capacitive Load for SDA and

SCL

pF

ns

t

SP

Pulse width of spikes which

must be suppressed by input

filter

SCL, SDA only

0

Notes: Refer to Typical Characteristics waveforms/graphs for closed loop data and variation with input supply and temperature. Electrical

specifications reflects open loop steady state data. System specifications reflects both steady state and dynamic close loop data

associated with the recommended external components.

Guarantee Levels:

{

− Guaranteed by Design Only. Not Characterized or Production Tested.

www.onsemi.com

10

FAN53880

Table 7. SYSTEM CHARACTERISTICS

System Specifications are guaranteed by design and are not production tested. They reflect closed loop performance using the

Recommended Layout and External Components. Minimum and Maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V +

BUCK

IN

350 mV and PV < V

− 250 mV, V

= 2.5 V to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

IN4 LDO3/4

IN

BST

IN12

IN

LDO1/2

IN3

IN4

IN3

+ 150 mV, V

= 0.6 V to 3.3 V, V

= 3.0 V to 5.7 V, V

, V

LDO2

, V

LDO3

and V = 0.8 V to 3.3 V, T = −40°C to 85°C, unless

LDO4 A

BUCK

BST

LDO1

otherwise noted. Typical values are at T = 25°C, AV = PV = V

= 3.8 V, V

= V

= 1.95 V, V

= 1.1 V, V = 5.0 V,

BST

A

IN

IN12

IN3

IN4

BUCK

V

LDO1

= V

= 2.8 V, V

= V

= 1.8 V.

LDO2

LDO3

LDO4

Symbol

SOFT START

Parameter

Conditions

Min

Typ

Max

Units

T

Soft−Start

Time from enabling to 95% of V

Target of 1.1 V,

300

30

480

ms

SS BK

OUT

I

= 300 mA and 1.2 A, Auto Mode, C

=

OUT

10 uF, PV = 3.0 V to 4.4 V

IN

RIPPLE

V

Output Ripple

I

= 20 mA, PFM Mode

= 200 mA, PWM Mode

40

10

mV

BK PFM_RPL

BK PWM_RPL

OUT

V

OUT

REGULATION & TRANSIENT

REG

Load Regulation

Line Regulation

I

= 1 mA to 1200 mA, PWM Mode

−1.5

−0.5

1.5

0.5

%

BK_LOAD

OUT

REG

V

= 3.0 V to 4.4 V , I

= 50 mA, 300 mA, and

BK_LINE

IN

OUT

1200 mA, PWM Mode

V

Load Transient

I

= 240 mA <−> 960 mA, T = T = 1 us,

70

mV

BK TR_LD

OUT

R

F

V

= 1.1 V, PV = 3.8 V, Auto Mode,

OUT

IN

Trecovery < 10 us

I

MAX

OUT

IO

I

Max

1200

mA

MAX_BK

OUT

EFFICIENCY

EFF

Efficiency

I

= 10 mA, V

= 2.85 V, PV = 3.8 V

92

93

90

85

%

BK

OUT

IN

= 600 mA, V

= 2.85 V, PV = 3.8 V

IN

OUT

= 1.2 A, V

= 2.85 V, PV = 3.8 V

IN

OUT

= 200 mA to 600 mA, V

3.8 V

= 1.1 V, PV

=

OUT

IN

I

= 10 mA, V

= 1.1 V, PV = 3.8 V

84

85

77

%

OUT

IN

= 600 mA, V

= 1.1 V, PV = 3.8 V

IN

OUT

= 1.2 A, V

= 1.1 V, PV = 3.8 V

IN

OUT

SOFT START

T

Soft Start Input Linear

Current Limit

450

280

190

700

580

mA

ms

LIN_BST

T

Soft−Start

Time from enabling to 90% of V

OUT

Target,

SS_BST

OUT

I

= 100 mA

T

PV = 3.8 V, BST_MODE bit = 1, V

= PV

IN

ms

SS BST_PS

IN

OUT

(Start up into Forced Pass−Through Mode)

RIPPLE

V

Output Ripple

I

= 10 mA, V

= 5 V, PV = 3.8 V

40

20

80

40

mV

BST PFM_RPL

BST PWM_RPL

OUT

IN

V

= 500 mA, V

= 5 V, PV = 3.8 V

OUT IN

OUT

REGULATION & TRANSIENT

REG

Load Regulation

Line Regulation

Load Transient

I

= 1 mA <−> 1 A, PV = 3.8 V, V = 5.0 V

OUT

−1.5

−0.5

+1.5

+0.5

150

%

BST_LD

BST_LN

OUT

IN

PV = 3.0 V <−> 4.4 V , I

= 50 mA and 1 A

IN

OUT

V

I

= 200 mA <−> 800 mA, T = T = 2 us,

mV

BST TR_LD

OUT

R

F

V

= 5.0 V, PV = 3.8 V, Trecovery < 10 us

OUT

IN

I

MAX

OUT

I

Max

1000

mA

O_BST

OUT

www.onsemi.com

11

FAN53880

Table 7. SYSTEM CHARACTERISTICS (continued)

System Specifications are guaranteed by design and are not production tested. They reflect closed loop performance using the

Recommended Layout and External Components. Minimum and Maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V +

BUCK

IN

350 mV and PV < V

− 250 mV, V

= 2.5 V to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

IN4 LDO3/4

IN

BST

IN12

IN

LDO1/2

IN3

IN4

IN3

+ 150 mV, V

= 0.6 V to 3.3 V, V

= 3.0 V to 5.7 V, V

, V

LDO2

, V

LDO3

and V = 0.8 V to 3.3 V, T = −40°C to 85°C, unless

LDO4 A

BUCK

BST

LDO1

otherwise noted. Typical values are at T = 25°C, AV = PV = V

= 3.8 V, V

= V

= 1.95 V, V

= 1.1 V, V = 5.0 V,

BST

A

IN

IN12

IN3

IN4

BUCK

V

LDO1

= V

= 2.8 V, V

= V

= 1.8 V.

LDO2

LDO3

LDO4

Symbol

EFFICIENCY

EFF

Parameter

Conditions

Min

Typ

Max

Units

Efficiency

PV = 3.8 V, V

= 5.0 V, I

= 10 mA

= 600 mA

= 1 A

88

94

93

%

BST

IN

OUT

PV = 3.8 V, V

IN

PV = 3.8 V, V

IN

LDO1/2 SOFT START

Startup Time

T

Time from enabling to 90% of V

(2.8 V), I =

OUT

100

150

ms

SS_LDO12

OUT

10 mA, C

= 14.7 uF

OUT

PSRR & NOISE

PSRR

Power Supply Rejection

Ratio

V

= 3.4 V, I

BUCK

= 100 mA, F = 1 kHz, C =

OUT

70

45

35

dB

L12 1KHZ

L12 100KHZ

N_L12

IN12

OUT

2.2 uF, I

= 1.2 A, I

= 1 A

BST

PSRR

V

= 3.4 V, I

= 100 mA, F = 100 kHz, C

=

IN12

OUT

2.2 uF, I

= 1.2 A, I

= 1 A

BUCK

BST

LDO1/2 Output Noise

V

IN12

= 3.4 V, V

= 1.8 V and 2.8 V, F = 100 Hz

60

uVrms

OUT

to 100 kHz, I

= 100 mA, C

= 2.2 uF

OUT

REGULATION & TRANSIENT PERFORMANCE

REG

LDO Load Regulation

LDO Line Regulation

I

= 100 uA to 300 mA, AV = V = 3.8 V

IN12

−0.5

+0.5

%

L12_LD

L12_LN

OUT

IN

AV = V

V

= 3.1 V to 4.4 V and AV /V

IN IN12

>

IN

IN12

+ 300 mV, I

= 50 mA and 300 mA

OUT

V

LDO Load Transient

I

= 1 mA <−> 100 mA, 150 mA/us

50

mV

L12 TR_LD

OUT

SHORT CIRCUIT

T

Short Circuit Debounce

Timer

40

20

ms

L12 SC_DEB

T

Period from Short Circuit

Shutdown to Restart

ms

L12 SC_RST

LDO3/4 SOFT START

T

Soft Start Time

Time from enabling to 90% of V

(1.8 V), I

=

80

150

ms

SS_L34

OUT

10 mA, C

= 14.7 uF

OUT

PSRR & NOISE

PSRR

Power Supply Rejection

Ratio

I

= 100 mA, F = 1 kHz, V = 1.95 V,

IN3/4

60

45

25

dB

L34

OUT

C

= 2.2 uF, I

= 1.2 A, I

= 1 A

OUT

BUCK

BST

I

= 100 mA, F = 10 kHz, V

= 1.95 V,

= 1 A

OUT

IN3/4

C

= 2.2 uF, I

= 1.2 A, I

OUT

BUCK BST

V

N_L34

LDO3/4 Output Noise

V

= 1.95 V, V = 1.8 V, F = 100 Hz to

OUT

60

uVrms

IN3/4

100 kHz, I

= 100 mA, C

= 2.2 uF

OUT

REGULATION & TRANSIENT PERFORMANCE

REG

LDO Load Regulation

LDO Line Regulation

LDO Load Transient

I

= 100 uA to 300 mA, AV = V = 3.8 V,

IN3/4

OUT

−0.5

+0.5

50

%

L34_LD

OUT

IN

V

= 1.8 V

REG

AV = V

V

= 3.0 V to 4.4 V and AV = V

>

L34_LN

IN

IN3/4

IN

IN3/4

+ 150 mV, I

= 50 mA and 300 mA

OUT

V

I

= 1 mA <−> 100 mA, 150 mA/us

mV

L34 TR_LD

OUT

www.onsemi.com

12

FAN53880

Table 7. SYSTEM CHARACTERISTICS (continued)

System Specifications are guaranteed by design and are not production tested. They reflect closed loop performance using the

Recommended Layout and External Components. Minimum and Maximum values are at AV = PV = 2.5 V to 5.5 V & PV > V +

BUCK

IN

350 mV and PV < V

− 250 mV, V

= 2.5 V to 5.5 V & V > V

+ 300 mV, V , V

= 1.95 V to 5.5 V & V , V

> V

IN4 LDO3/4

IN

BST

IN12

IN

LDO1/2

IN3

IN4

IN3

+ 150 mV, V

= 0.6 V to 3.3 V, V

= 3.0 V to 5.7 V, V

, V

LDO2

, V

LDO3

and V = 0.8 V to 3.3 V, T = −40°C to 85°C, unless

LDO4 A

BUCK

BST

LDO1

otherwise noted. Typical values are at T = 25°C, AV = PV = V

= 3.8 V, V

= V

= 1.95 V, V

= 1.1 V, V = 5.0 V,

BST

A

IN

IN12

IN3

IN4

BUCK

V

LDO1

= V

= 2.8 V, V

= V

= 1.8 V.

LDO2

LDO3

LDO4

Symbol

SHORT CIRCUIT

Parameter

Conditions

Min

Typ

Max

Units

T

Short Circuit Debouncer

Timer

40

20

ms

L34 SC_DEB

T

Period from Short Circuit

Shutdown to Restart

ms

L34 SC_RST

THERMAL PROTECTION

T

Thermal Warning

Thermal Shutdown

115

130

125

140

135

150

°C

WRN

T

SD

www.onsemi.com

13

FAN53880

TYPICAL CHARACTERISTICS

Unless otherwise specified, T = 25°C, AV = PV = V

= 3.8 V, V = V = 1.95 V, V

= 1.8 V, Recommended Layout and External Components.

= 1.1 V,

A

IN

IN12

IN3

IN4

BUCK

V

= 5.0 V, V

= V

= 2.8 V, V

= V

BST

LDO1

LDO2

LDO3

LDO4

Figure 4. Buck Efficiency vs. Load Current and

Input Voltage, V_OUT= 1.1 V, Auto Mode

Figure 5. Buck Efficiency vs. Load Current and

Input Voltage, V_OUT= 2.85 V, Auto Mode

Figure 6. Boost Efficiency vs. Load Current and

Input Voltage, V_OUT= 5.0 V, Auto Mode

Figure 7. Buck Output Regulation vs. Load Current

and Input Voltage, V_OUT= 1.1 V, Auto Mode

Figure 9. Boost Output Regulation vs. Load Current

and Input Voltage, V_OUT= 5.0 V, Auto Mode

Figure 8. Buck Output Regulation vs. Load Current

and Input Voltage, V_OUT= 2.85 V, Auto Mode

www.onsemi.com

14

FAN53880

Figure 10. LDO1/2 Output Regulation vs. Load

Current and Input Voltage, V_OUT= 2.8 V, Auto Mode

Figure 11. LDO3/4 Output Regulation vs. Load

Current and Input Voltage, V_OUT= 1.8 V, Auto Mode

Figure 12. Buck Output Ripple in PFM Mode,

_IN= 3.8 V, V_OUT= 1.1 V, I_OUT= 10 mA

Figure 13. Buck Output Ripple in PWM Mode,

V

V_IN= 3.8 V, V_OUT= 1.1 V, I_OUT= 200 mA

Figure 14. Boost Output Ripple in PFM Mode, V_IN

3.8 V, V_OUT= 5.0 V, I_OUT= 10 mA, Auto Mode

=

Figure 15. Boost Output Ripple in PWM Mode, V_IN

3.8 V, V_OUT= 5.0 V, I_OUT= 500 mA, Auto Mode

=

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15

FAN53880

Figure 16. Buck Load Transient, V_IN= 3.8 V, V_OUT

1.1 V, 240 mA @ 960 mA, 1 ms Edge, Auto Mode

=

Figure 17. Boost Load Transient, V_IN= 3.8 V, V_OUT

5.0 V, 200 mA @ 800 mA, 2 ms Edge, Auto Mode

=

Figure 19. LDO3/4 Load Transient, V_IN= 1.95 V,

Figure 18. LDO1/2 Load Transient, V_IN= 3.8 V,

V

_OUT= 1.8 V, 1 mA @ 150 mA, 1 ms Edge

V

_OUT= 2.85 V, 1 mA @ 150 mA, 1 ms Edge

Figure 20. Buck Start−up, V_IN= 3.8 V, V_OUT= 1.1 V,

Figure 21. Boost Start−up, V_IN= 3.8 V, V_OUT= 5.0 V,

300 mA Resistive Load, Auto Mode

100 mA Resistive Load, Auto Mode

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16

FAN53880

Figure 22. LDO1/2 Start−up, V_IN= 3.8 V,

_OUT= 2.8 V, No Load

Figure 23. LDO3/4 Start−up, V_IN= 1.95 V,

_OUT= 1.8 V, No Load

V

Figure 25. LDO3/4 PSRR vs. Frequency,

100 mA Load

Figure 24. LDO1/2 PSRR vs. Frequency,

100 mA Load

Figure 26. LDO1/2 Output Noise Voltage vs.

Frequency, 100 mA Load

Figure 27. LDO3/4 Output Noise Voltage vs.

Frequency, 100 mA Load

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17

FAN53880

FUNCTIONAL SPECIFICATIONS

Device Operation

Overview

available for power−up and power−down of the Buck and

LDOs.

Many of the ICs protection mechanisms have

programmable thresholds. For fault handling, a dedicated

interrupt pin, mask−able interrupt bits, and real time status

bits are provided.

The FAN53880 is a Mini−PMIC containing:

• One 2.5 MHz, 1200 mA Buck converter

• One 2.5 MHz, 1000 mA Boost converter

• Four 300 mA low noise LDOs

The Buck and Boost allow the use of small inductors and

capacitors for a small overall solution size.

Refer to the figure below for an additional overview of the

FAN53880 operation.

Each converter can be individually enabled/disabled

through I2C communication. The Boost converter also has

an enable pin, BSTEN. A configurable sequencer is

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18

FAN53880

AVIN

Applied

Start Up/Shut Down Flow Chart

No

AVIN>VPOR

BUCK_SEQ

=000

LDO1_SEQ

= 000

LDO2_SEQ

= 000

LDO3_SEQ

= 000

LDO4_SEQ

= 000

Yes

No

Start POR

BST_EN

= 1

BUCK_EN

= 1

LDO1_EN

= 1

LDO2_EN

= 1

LDO3_EN

= 1

LDO4_EN

= 1

No

HWEN Asserted

High

Yes

Enable Boost

Enable Buck

Enable LDO1

Enable LDO2

Enable LDO3

Enable LDO4

Wait 100us

APVIN_UVLO

&VIN12_UVLO

Good?

APVIN_UVLO

&VIN12_UVLO

Good?

APVIN_UVLO

&VIN3_UVLO

Good?

APVIN_UVLO

&VIN4_UVLO

Good?

APVIN_UVLO

Good?

APVIN_UVLO

Good?

Yes

No

BG Good?

Yes

No

FAULT

Disable

Boost

FAULT

Disable

Buck

FAULT

Disable

LDO1

FAULT

Disable

LDO2

FAULT

Disable

LDO3

FAULT

Disable

LDO4

APVIN_UVLO

Good?

Yes

No

XXXX_SEQ =

SEQ_

CONTROL =

01

No

Reset

SEQ_COUNT

to 000

010

Set AVIN_UVLO

Interrupt/Stat bits

Yes

Enable

Converter

Start

Sequence

Execution

HWEN = Low Yes

No

Update

SEQ_COUNT

BSTEN Asserted

High

Shutdown

Buck and

LDOs if

VIN_UVLO

Good?

XXXX_SEQ =

001

No

Enabled

FAULT

Disable

Converter

Wait 100us

SEQ_

CONTROL =

10

Yes

No

Yes

Enable

Converter

….

Repeat Steps for

No

BG Good?

Update

SEQ_COUNT

XXXX_SEQ = 011 to 110

Start Reverse

Sequence

Execution

Yes

VIN_UVLO

Good?

XXXX_SEQ =

111

No

Update

SEQ_COUNT

Enable Boost

Yes

FAULT

Disable

Converter

Enable

Converter

Sequencing

Complete

No

APVIN_UVLO

Good?

No

Yes

FAULT

Disable

Boost

VIN_UVLO

Good?

Yes

No

Reset

SEQ_COUNT

to 000

FAULT

Disable

Converter

Yes

BSTEN = Low No

Yes

Note: VIN_UVLO is used as a generic term for the power input associated with the converter being enabled.

Shutdown

Boost

Figure 28. Start−up and Shut Down Flow Chart

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19

FAN53880

Power Supplies

All converters use AV to power their analog and control

Table 8. CONVERTER DEPENDENCY OFF POWER

INPUTS

IN

circuitry.

The Buck and Boost use PV as their power source. PV

Converter

BUCK

AV

PV

V

IN4

IN

IN12

IN3

IN

X

must remain within 25 mV of AV for proper device

IN

BOOST

LDO1/LDO2

LDO3

operation (it’s recommended to locally connect PVIN to

AVIN). Because of this, the term APV may instead be used

X

IN

throughout this datasheet.

X

LDO1 and LDO2 use V

, LDO3 uses V and LDO4

IN3

IN12

LDO4

X

uses V to power their outputs. These power supplies have

IN4

independent UVLO thresholds with dedicated interrupts

and status bits.

See Table 8 for details.

POR

When a rising AV reaches ~2 V a POR occurs where

IN

registers reset and are readable through I2C.

See Table 9 for details.

Table 9. PMIC OPERATION IN APVIN UVLO

AV State

HWEN or BSTEN = High

Results

(1)

After AV > UVLO

IN

AV < V

No

(4)

(5)

(4)

(6)

IN

POR

V

POR

<AV < UVLO

(2)

IN

AV < V

Yes

(1)

IN

POR

V

POR

< AV < UVLO

(3)

IN

1. Device in shutdown, I2C registers not reliable

2. Band Gap off, I2C registers readable

3. Band Gap on, I2C registers readable

4. All registers set to their default values

5. Registers retain value prior to the fault and begin a

start up after HWEN or BSTEN are high

6. Registers retain value prior to fault and do an

automatic restart

Enable Auto−Sequencing

A programmable sequencer is available for controlling

power−up and power−down timing of the Buck and LDOs.

There are 7 time slots available and the sequencing speed

(period per slot) is programmable. The FAN53880

sequences through time slots 001 to 111 during power up,

and from 111 to 001 during power down when initiated with

the SEQ_CONTROL bits.

UVLO Rising

When rising AV reaches V

When a converter is added into a sequence slot, it can no

longer be enabled using the XXX_EN bits.

the ICs

VIN_UVLO_RISE

IN

internal circuitry is operable and an interrupt is generated.

The part will be in a Sleep state if HWEN=BSTEN=LOW.

If a converter faults during a start−up sequence, the other

converters will be started in their assigned time slot and the

faulted converter will not attempt to re−enable. An interrupt

is generated to inform the host of the fault and a status bit is

set.

UVLO Falling

When falling AV reaches V

a Chip

IN

VIN_UVLO_FALL

Fault occurs, all converters are suspended, an interrupt

generated, and related Status bits set. Registers will not reset

The two tables below summarize control pin, register bit,

and sequence combinations.

to default values unless AV falls below POR (~2 V).

IN

Control Pins and Enable Bits

There are two control pins, HWEN and BSTEN.

When HWEN=HIGH, the ICs internal circuitry turns on

in Standby state where converters can be enabled through

I2C, assuming their related power supplies are above their

UVLO thresholds (refer to the Electrical Characteristics

table).

Each converter has an independent enable bit, XXX_EN.

The BSTEN pin is a hardware enable option for the Boost

and its basic control circuits. BSTEN functions independent

of HWEN.

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20

FAN53880

These protections allow the converter to remain enabled

Table 10. BUCK AND LDO ENABLE/DISABLE

CONTROLS

or suspends or shuts off the faulted converter, but

doesn’t affect operation of non−related converters. The

specific fault behavior depends on the FLT_SD_B bit

setting.

Buck and LDO Control

HWEN XXX_SEQ XXX_EN SEQ_CONTROL

Dependent

On/Off

Low

High

Low

High

Low

High

Low

High

000

0

1

No

Yes

No

Yes

Off

FLT_SD_B Bit

There are two I2C selectable fault behavior options:

• Multiple Fault Shutdown (default)

Limits repetitive starting and faulting of a converter or

chip faults to 4 failures.

>000

000

Off

CNTL

Off

• Automatic Fault Recovery

000

On

No limit to repetitive starting and faulting of a

converter or to number of chip faults.

>000

Off

CNTL

NOTE: Sequencer fault behavior is independent of these

protection schemes.

NOTE: CNTL indicates that the state of the output will be

dependent on the setting of the SEQ_CONTROL bits.

When HWEN is high, SEQ_CONTROL = 01 will enable

any outputs based on their XXX_SEQ > 000.

Multiple Fault Shutdown

FLT_SD_B=“0” (default)

If a fault occurs, the IC will:

• Suspend the converter

Table 11. BOOST ENABLE/DISABLE CONTROLS

Boost Control

• Set Interrupt and Status bits

• Increment the internal 4−fault counter

• Wait 20 ms

HWEN

Low

BSTEN

Low

BST_ENx

On/Off

Off

0

1

High

Low

Off

• Re−enable the converter if XXX_EN=“1” or shut off

High

Low

On

the converter if XXX_SEQ=“1”

♦ Re−enable requires another SEQ_CONTROL=“01”

write

High

Low

On

Off

NOTE: UVLO and TSD faults will not re−enable the

converter after 20 ms unless the fault was

removed.

High

Low

On

High

On

High

On

If any four Chip Faults occur, the IC will:

• Shut off all converters

NOTE: The Boost Control table above shows that the Boost

operation requires either BSTEN to be high or a

combination of HWEN high and one of the enable bits in

register 0x0A needs to be set to 1.

• Reset all XXX_EN and XXX_SEQ bits to “0”

• Set Interrupt and Status bits, including the CHIP_SUSD

Status bit, to “1”. This bit will only clear after both

HWEN and BSTEN are set LOW

Fault Protection

Fault Protection Overview

Each fault described below has a dedicated interrupt and

status bit.

If any four Converter Faults occur, the IC will:

• Shut off that converter

• Set XXX_SUSD bit to “1”. This bit will only clear after

that converter is successfully re−enabled

• Reset that converter’s XXX_EN or XXX_SEQ bit to

“0”

The FAN53880 has two levels of fault protection:

• Chip Faults

(TSD, APV UVLO)

IN

The protection suspends or shuts off all enabled

converters. Recovery behavior depends on the

FLT_SD_B bit setting.

Re−enabling any converter after a fourth Chip Fault first

requires setting the HWEN and BSTEN pins LOW. Any

time HWEN and BSTEN pin is taken LOW, all fault

counters are globally reset.

• Converter Faults

(UVP, OVP, IPK, Short Circuit, V

UVLO)

V

IN12/ IN3 / IN4

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21

FAN53880

Automatic Fault Recovery

Modes of Operation

FLT_SD_B=“1” (should only be set prior to enabling any

converter).

If a fault occurs, the IC will:

During PWM operation, the Buck switches at a nominal

fixed frequency of 2.5 MHz. In Automode at light load

operation, the device will enter PFM mode. Instead, the

Buck can be put into Forced PWM mode by setting the

BUCK_MODE bit to “1”. Also, the FAN53880 provides a

bit, BUCK_LOAD, which the user can set to apply an

internal artificial load to maintain a minimum switching

frequency above 20 kHz.

• Set Interrupt and Status bits

Also:

Chip Faults

♦ Suspend all converters

♦ Any converter with XXX_EN=“1” will re−enable

after the APV UVLO or TSD fault is removed

♦ Any converter with XXX_SEQ=“1” re−enable

IN

Programmable Output Voltage

The Buck output voltage can be programmed via I2C in

12.5 mV steps.

requires another SEQ_CONTROL=“01” write

Converter Faults

Shutdown

♦ Any converter with an OVP or UVP, or any LDO

with an IPK or LDO short circuit fault will remain

enabled. Otherwise suspend that converter and:

When the Buck is disabled, switching will cease, the

output tristated, and the output will be discharged via the

load or if BUCK_DIS bit = “1”, via the active discharge

resistor.

⋅

Automatically re−enable after V

UVLO fault is removed

V

IN12/ IN3 / IN4

⋅

Automatically re−enable 20 ms after Buck or

Boost IPK fault or short circuit if XXX_EN=“1”,

or remain off until another

Boost Functionality

Startup Behavior

The Boost can be enabled by two methods:

SEQ_CONTROL=“01” write if XXX_SEQ=“1”

• Setting the BSTEN pin HIGH

Thermal Management

When the die temperature rises to T

• Setting the HWEN pin HIGH and setting any

, a Thermal

BOOST_ENx bit to “1”

WRN

Warning (TSD_WRN) interrupt is issued. Also, a Status bit

will be set and remain set until the die temperature drops to

a nominal value of 110°C.

The Boost can startup in PFM mode or automatic

pass−through mode depending on the VIN to VOUT

difference. When starting in PFM mode, the part has a linear

mode which limits inrush currents. Once VOUT charges up

to VIN, the linear mode current limit is disabled and the

regulator uses one−quarter current limit to charge the output

cap to the final VOUT target value. If VOUT fails to reach

90% of the VOUT target within 1 ms, a UVP fault is

declared.

If the die temperature continues to rise above T

,

WRN

Thermal Shutdown (TSD) will occur. After the die

temperature has fallen below T , recovery behavior

WRN

depends on the FLT_SD_B bit setting. Refer to the Fault

Protection section for details on Chip Faults.

Fault Handling

Mask−able Interrupt bits, a dedicated INTB pin, and real

time status bits are provided. Each converter has

independent protection debounce timers.

An interrupt is generated each time a fault occurs. All bits

set in the Interrupt registers must be cleared to reset the

INTB pin to HIGH.

Modes of Operation

During PWM operation, the Boost switches at a nominal

fixed frequency of 2.5 MHz. In Automode at light load

operation, the device will enter PFM mode. Instead, the

Boost can be put into Forced PWM mode by setting the

BST_MODE bit to “1”. Also, the FAN53880 provides a bit,

BST_LOAD, which the user can set to apply an internal

artificial load to maintain a minimum switching frequency

above 20 kHz.

Buck Functionality

Startup Behavior

The Buck can be enabled by two methods if and only if the

HWEN pin is high:

In normal operation, the device automatically transitions

from Boost Mode to Pass−Through Mode if

• Setting BUCK_EN to “1”

V

IN

> V _target − 250 mV. In Pass−Through Mode, there

OUT

• Setting BUCK_SEQ > “000” and SEQ_CONTROL to

is no switching and the device has a low impedance path

between V and V

“01”

.

OUT

IN

The Buck has internal soft−start and starts up within

400 ms (typical) when using the recommended external

components.

Programmable Output Voltage

The Boost output voltage can be programmed via I2C in

25 mV steps. When the output voltage is programmed to a

lower voltage, the active pull−down is used to expedite the

drop in voltage across the output capacitance.

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22

FAN53880

Shutdown

specifications. The SCL pin is an input and the SDA pin is

a bi−directional open−drain output. The IC supports single

register read and write transactions as well as multiple

register read transactions.

When the Boost is disabled, switching will cease, the

output tristated, and the output will be discharged via the

load or if BOOST_DIS bit = “1”, via the active discharge

resistor.

Slave Address

The default I2C Slave Address is the Table 12 and

Table 13. Other slave addresses can be accommodated

upon request. Contact your ON Semiconductor

representative if a different slave address is required.

LDO Functionality

Startup Behavior

The LDO’s can be enabled by two methods if and only if

the HWEN pin is high:

• Setting LDOx_EN to “1”

Table 12. I2C SLAVE ADDRESS

• Setting LDO_SEQ > “000” and SEQ_CONTROL to

Device

Hex

Decimal

7 bit Binary

“01”

FAN53880

7h35

53d

0110101

The Buck has internal soft−start which limits supply

current to the LDOx_ILIM setting. If VOUT fails to reach

UVP

in T

a UVP fault is declared.

LDOxx_HYS

SS_LDOxx,

Table 13. FAN53880 (7 BIT) SLAVE ADDRESS BYTE

7

6

5

4

3

2

1

X

Programmable Output Voltage

The LDO output voltages can be programmed via I2C in

25 mV steps.

0

1

0

1

0

1

R/W

NOTE: READ = 1

WRITE = 0

I2C Functionality

Introduction

Timing Diagrams

The FAN53880 serial interface is compatible with the

Standard−Mode, Fast−Mode, and Fast−Mode Plus I C bus

2

t_F

t_SU;STA

t_BUF

SDA

t_SU;DAT

t_R

t_HIGH

t_SU;STO

SCL

t_LOW

t_HD;DAT

t_HD;STA

STOP

START

REPEATED

START

Figure 29. I2C Interface Timing for Fast−Mode Plus, Fast−Mode, and Standard−Mode

2

Normally, data transfer occurs when SCL is LOW. Data

is clocked in on the rising edge of SCL. Typically data

transitions at or after the subsequent falling edge of SCL to

provide ample setup time for the next data bit to be ready

before the subsequent rising edge of SCL.

The idle state of the I C bus is SDA and SCL both in the

HIGH state. A valid transaction begins with a START

condition which occurs when SDA transitions from HIGH

to LOW when SCL remains HIGH.

Slave Address

MS Bit

T_HD:STA

Data Change Allowed

SDA

SCL

SDA

T_H

Figure 31. START Condition

T_SU

SCL

A valid transaction ends with a STOP condition which

occurs when SDA transitions from LOW to HIGH while

SCL remains HIGH.

Figure 30. Data Transfer Timing

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23

FAN53880

Slave Release Master Drives

A

REPEATED START condition is functionally

equivalent to a STOP condition followed immediately by a

START condition. During a read from the IC, the master

issues a REPEATED START after sending the register

address and before re−sending the slave address. The

REPEATED START is a HIGH to LOW transition on SDA

while SCL is HIGH,

T_SU;STO

ACK(0) or

NACK(1)

SDA

SCL

Figure 32. STOP Condition

T_SU;STA

Slave Release

T_HD;STA

ACK(0) or

NACK(1)

SLAVE ADDR

MS Bit

SDA

SCL

T_VD;DAT

Figure 33. REPEATED START Condition

Read and Write Transactions

The FAN53880 supports the following read and write

transaction protocols.

Figure 34. Single Register Write Transaction

Figure 35. Single Register Read Transaction

Figure 36. Multiple Register Read Transaction

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24

FAN53880

REGISTER MAPPING TABLE

Table 14. REGISTER MAPPING

Read Only

Bit[4]

Write Only

Bit[3]

Read /

Write

Read /

Clear

Write /

Clear

Address

Name

Bit[7]

Bit[6]

Bit[5]

Bit[2]

Bit[1]

Bit[0]

0x00

PROD-

UCT ID

Product ID

0x01

SILICON

REV ID

Revision

0x02

0x03

0x04

BUCK

BOOST

LDO1

BUCK_OUT

Reserved

BOOST_VOUT

LDO1_PA- LDO1_VOUT

SSTHRU

0x05

0x06

0x07

0x08

LDO2

LDO3

LDO4

IOUT

LDO2_PA- LDO2_VOUT

SSTHRU

LDO3_PA- LDO3_VOUT

SSTHRU

LDO4_PA- LDO4_VOUT

SSTHRU

0

LDO4_ILIM

0

LDO3_ILIM

LDO2_ILIM

LDO3_EN

LDO1_IL-

IM

0x09

0x0A

ENABLE

BST_MOD- BUCK_MO-

LDO4_EN

E

DE

BUCK_EN

BST_EN4

LDO2_EN LDO1_EN

BOOST_E- BST_EN7

NABLE

BST_EN6

BST_EN5

0

BST_EN3

BST_EN2

BST_EN1

BST_EN0

0x0B

0x0C

BUCK_SE-

Q

BUCK_SEQ

LDO12_S-

EQ

0

LDO1_SEQ

LDO2_SEQ

0x0D

0x0E

LDO34_S-

EQ

LDO4_SEQ

LDO3_SEQ

SE-

SEQ_SPEED

QUENC-

ING

SEQ_CONTROL

SEQ_ON

SEQ_COUNT

0x0F

DIS-

BUCK_LO- BOOST_L- LDO4_DIS

BOOST_D- BUCK_DIS

IS

CHARGE

AD

OAD

LDO3_DIS

LDO2_DIS

LDO1_DIS

0

0x10

0x11

RESET

0

SOFT_RESET

FLT_SD_B

INTER-

RUPT1

LDO4_OV-

P_INT

LDO3_UVP LDO2_UV- LDO1_UV-

_INT P_INT P_INT

LDO3_OV- LDO2_OVP

LDO1_OVP

_INT

LDO4_UVP

_INT

P_INT

_INT

0x12

0x13

0x14

0x15

0x16

INTER-

RUPT2

BST_OVP BUCK_OV- BST_UVP_I- BUCK_UVP LDO4_OCP LDO3_OCP LDO2_OC- LDO1_OC-

_INT

P_INT

NT

_INT

P_INT

INTER-

RUPT3

BST_IPK_I- BUCK_IPK APVIN_UVL- LDO12_UVL- LDO3_UVL- LDO4_UVL- TSD_INT

TSD_WRN

_INT

NT

_INT

O_INT

STATUS1

STATUS2

STATUS3

LDO4_OV- LDO3_OV- LDO2_OVP

P_STAT P_STAT _STAT

LDO1_OVP

_STAT

LDO4_UVP LDO3_UVP LDO2_UV- LDO1_UV-

_STAT _STAT P_STAT P_STAT

BST_OVP BUCK_OV- BST_UVP_- BUCK_UVP LDO4_OCP LDO3_OCP LDO2_OC- LDO1_OC-

_STAT P_STAT STAT _STAT _STAT _STAT P_STAT P_STAT

BST_IPK_- BUCK_IPK APVIN_UVL- LDO12_UVL- LDO3_UVL- LDO4_UVL- TSD_STAT TSD_WRN

STAT _STAT O_STAT O_STAT O_STAT O_STAT _STAT

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25

FAN53880

Table 14. REGISTER MAPPING

Read Only

Bit[4]

Write Only

Bit[3]

Read /

Write

Read /

Clear

Write /

Clear

Address

Name

MINT1

Bit[7]

Bit[6]

Bit[5]

Bit[2]

Bit[1]

Bit[0]

0x17

MASK_LD- MASK_LD- MASK_LDO MASK_LDO MASK_LDO MASK_LDO MASK_LD- MASK_LD-

O4_OVP O3_OVP 2_OVP 1_OVP 4_UVP 3_UVP O2_UVP O1_UVP

0x18

0x19

0x1A

MINT2

MASK_BS- MASK_BU- MASK_BST MASK_BUC- MASK_LDO MASK_LDO MASK_LD- MASK_LD-

T_OVP CK_OVP _UVP K_UVP 4_OCP 3_OCP O2_OCP O1_OCP

MINT3

MASK_BS- MASK_BU- MASK_APVI- MASK_LDO MASK_LDO MASK_LDO MASK_TS- MASK_TS-

T_IPK

CK_IPK

N_UVLO

12_UVLO

3_UVLO

4_UVLO

D

D_WRN

STATUS4

0

CHIP_SUS- BOOST_SU- BUCK_SUS- LDO4_SUS- LDO3_SUS- LDO2_SU- LDO1_SU-

D

SD

D

SD

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26

FAN53880

REGISTER DETAILS

Table 15. REGISTER DETAILS − 0x00 PRODUCT ID

0x00 PRODUCT ID

Default = 00000001

Description

Bit

Name

Default

Type

7:00

Product ID

00000001

Read

Allows customers to identify manufacturer and version

Product ID Table

Code

0

Product

−

1

FAN53880

Reserved

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

Table 16. REGISTER DETAILS − 0x01 SILICON REV ID

0x01 SILICON REV ID

Default = See Description

Description

Bit

Name

Default

Type

7:0

Revision

See

Description

Read

Provides the silicon revision

Part Number

REG 01 [7:0] Silicon Rev ID

00000011

FAN53880UC001X

FAN53880UC002X

00000100

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27

FAN53880

Table 17. REGISTER DETAILS − 0x02 BUCK

0x02 BUCK

Default = 00000000

Description

Bit

Name

Default

Type

7:00

BUCK_OUT

00000000

R/W

Buck programming steps are 12.5 mV with a range of 0.6 to 3.3 V.

Vout = [0.0125 x (d−31)] + 0.6; Where “d” is the decimal value of the

register.

Hex

0

V

Hex

28

V

OUT

DEFAULT

Reserved

0.6000V

0.6125V

0.6250V

0.6375V

0.6500V

0.6625V

0.6750V

0.6875V

0.7000V

0.7125V

............

01 −1E

1F

29−F6

F0

3.2125V

3.2250V

3.2375V

3.2500V

3.2625V

3.2750V

3.2875V

3.3000V

Reserved

20

F1

21

F2

22

F3

23

F4

24

F5

25

F6

26

F7

27

F8−FF

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28

FAN53880

Table 18. REGISTER DETAILS − 0x03 BOOST

0x03 BOOST

Default = 00000000

Description

Bit

7

Name

Default

Type

R/W

BST_PASS

0

6:0

BOOST_VO 0000000

UT

The boost output voltage is programmable in the 25 mV steps.

Equation: V = 3.000 + (d−4)*0.025V; where “d” is the decimal value.

OUT

Hex

0

V

Hex

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

V

Hex

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

V

Hex

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

V

OUT

DEFAULT

Reserved

3.000V

3.025V

3.050V

3.075V

3.100V

3.125V

3.150V

3.175V

3.200V

3.225V

3.250V

3.275V

3.300V

3.325V

3.350V

3.375V

3.400V

3.425V

3.450V

3.475V

3.500V

3.525V

3.550V

3.575V

3.600V

3.625V

3.650V

3.675V

3.700V

3.725V

3.750V

3.775V

3.800V

3.825V

3.850V

3.875V

3.900V

3.925V

3.950V

3.975V

4.000V

4.025V

4.050V

4.075V

4.100V

4.125V

4.150V

4.175V

4.200V

4.225V

4.250V

4.275V

4.300V

4.325V

4.350V

4.375V

4.400V

4.425V

4.450V

4.475V

4.500V

4.525V

4.550V

4.575V

4.600V

4.625V

4.650V

4.675V

4.700V

4.725V

4.750V

4.775V

4.800V

4.825V

4.850V

4.875V

4.900V

4.925V

4.950V

4.975V

5.000V

5.025V

5.050V

5.075V

5.100V

5.125V

5.150V

5.175V

5.200V

5.225V

5.250V

5.275V

5.300V

5.325V

5.350V

5.375V

5.400V

5.425V

5.450V

5.475V

5.500V

5.525V

5.550V

5.575V

5.600V

5.625V

5.650V

5.675V

5.700V

1

2

3

4

5

6

7

8

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

71−7F Reserved

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29

FAN53880

Table 19. REGISTER DETAILS − 0x04 LDO1

0x04 LDO1

Default = 00000000

Description

Bit

Name

Default

Type

6:0

LDO1_VOUT

0000000

R/W

Sets LDO1 regulation target voltage.

Equation: Vout = 0.800V + [(d−15)*25mV]; Where d is the decimal

value of the register

Hex

0

V

Hex

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

V

OUT

DEFAULT

Reserved

0.800V

2.025V

2.050V

2.075V

2.100V

2.125V

2.150V

2.175V

2.200V

2.225V

2.250V

2.275V

2.300V

2.325V

2.350V

2.375V

2.400V

2.425V

2.450V

2.475V

2.500V

2.525V

2.550V

2.575V

2.600V

2.625V

2.650V

2.675V

2.700V

2.725V

2.750V

2.775V

2.800V

2.825V

2.850V

2.875V

2.900V

2.925V

1

2

3

4

5

6

7

8

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

0.825V

0.850V

0.875V

0.900V

0.925V

0.950V

0.975V

1.000V

1.025V

1.050V

1.075V

1.100V

1.125V

1.150V

1.175V

1.200V

1.225V

1.250V

1.275V

1.300V

1.325V

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30

FAN53880

Table 19. REGISTER DETAILS − 0x04 LDO1

0x04 LDO1

Default = 00000000

Description

Bit

Name

Default

Type

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

1.350V

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

2.950V

2.975V

1.375V

1.400V

1.425V

1.450V

1.475V

1.500V

1.525V

1.550V

1.575V

1.600V

1.625V

1.650V

1.675V

1.700V

1.725V

1.750V

1.775V

1.800V

1.825V

1.850V

1.875V

1.900V

1.925V

1.950V

1.975V

2.000V

3.000V

3.025V

3.050V

3.075V

3.100V

3.125V

3.150V

3.175V

3.200V

3.225V

3.250V

3.275V

3.300V

Reserved

www.onsemi.com

31

FAN53880

Table 20. REGISTER DETAILS − 0x05 LDO2

0x05 LDO2

Default = 00000000

Description

Bit

7

Name

Default

Type

UNUSED

6:0

LDO2_VOUT

0000000

R/W

Sets LDO2 regulation target voltage.

Equation: Vout = 0.800V + [(d−15)*25mV]; Where d is the decimal

value of the register

Hex

0

V

Hex

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

V

OUT

DEFAULT

Reserved

0.800V

2.025V

2.050V

2.075V

2.100V

2.125V

2.150V

2.175V

2.200V

2.225V

2.250V

2.275V

2.300V

2.325V

2.350V

2.375V

2.400V

2.425V

2.450V

2.475V

2.500V

2.525V

2.550V

2.575V

2.600V

2.625V

2.650V

2.675V

2.700V

2.725V

2.750V

2.75V

1

2

3

4

5

6

7

8

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

0.825V

0.850V

0.875V

0.900V

0.925V

0.950V

0.975V

1.000V

1.025V

1.050V

1.075V

1.100V

1.125V

1.150V

1.175V

1.200V

2.800V

2.825V

2.850V

2.875V

2.900V

1.225V

1.250V

1.275V

1.300V

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32

FAN53880

Table 20. REGISTER DETAILS − 0x05 LDO2

0x05 LDO2

Default = 00000000

Description

Bit

Name

Default

Type

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

1.325V

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

2.925V

2.950V

1.350V

1.375V

1.400V

1.425V

1.450V

1.475V

1.500V

1.525V

1.550V

1.575V

1.600V

1.625V

1.650V

1.675V

1.700V

1.725V

1.750V

1.775V

1.800V

1.825V

1.850V

1.875V

1.900V

1.925V

1.950V

1.975V

2.000V

2.975V

3.000V

3.025V

3.050V

3.075V

3.100V

3.125V

3.150V

3.175V

3.200V

3.225V

3.250V

3.275V

3.300V

Reserved

www.onsemi.com

33

FAN53880

Table 21. REGISTER DETAILS − 0x06 LDO3

0x06 LDO3

Default = 00000000

Description

Bit

7

Name

Default

Type

UNUSED

6:0

LDO3_VOUT

0000000

R/W

Sets LDO3 regulation target voltage.

Equation: Vout = 0.800V + [(d−15)*25mV]; Where d is the decimal

value of the register

Hex

0

V

Hex

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

V

OUT

DEFAULT

Reserved

0.800V

2.025V

2.050V

2.075V

2.100V

2.125V

2.150V

2.175V

2.200V

2.225V

2.250V

2.275V

2.300V

2.325V

2.350V

2.375V

2.400V

2.425V

2.450V

2.475V

2.500V

2.525V

2.550V

2.575V

2.600V

2.625V

2.650V

2.675V

2.700V

2.725V

2.750V

2.75V

1

2

3

4

5

6

7

8

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

0.825V

0.850V

0.875V

0.900V

0.925V

0.950V

0.975V

1.000V

1.025V

1.050V

1.075V

1.100V

1.125V

1.150V

1.175V

1.200V

2.800V

2.825V

2.850V

2.875V

2.900V

1.225V

1.250V

1.275V

1.300V

www.onsemi.com

34

FAN53880

Table 21. REGISTER DETAILS − 0x06 LDO3

0x06 LDO3

Default = 00000000

Description

Bit

Name

Default

Type

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

1.325V

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

2.925V

2.950V

1.350V

1.375V

1.400V

1.425V

1.450V

1.475V

1.500V

1.525V

1.550V

1.575V

1.600V

1.625V

1.650V

1.675V

1.700V

1.725V

1.750V

1.775V

1.800V

1.825V

1.850V

1.875V

1.900V

1.925V

1.950V

1.975V

2.000V

2.975V

3.000V

3.025V

3.050V

3.075V

3.100V

3.125V

3.150V

3.175V

3.200V

3.225V

3.250V

3.275V

3.300V

Reserved

www.onsemi.com

35

FAN53880

Table 22. REGISTER DETAILS − 0x07 LDO4

0x07 LDO4

Default = 00000000

Description

Bit

7

Name

Default

Type

UNUSED

6:0

LDO4_VOUT

0000000

R/W

Sets LDO4 regulation target voltage.

Equation: Vout = 0.800V + [(d−15)*25mV]; Where d is the decimal

value of the register

Hex

0

V

Hex

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

V

OUT

DEFAULT

Reserved

0.800V

2.025V

2.050V

2.075V

2.100V

2.125V

2.150V

2.175V

2.200V

2.225V

2.250V

2.275V

2.300V

2.325V

2.350V

2.375V

2.400V

2.425V

2.450V

2.475V

2.500V

2.525V

2.550V

2.575V

2.600V

2.625V

2.650V

2.675V

2.700V

2.725V

2.750V

2.75V

1

2

3

4

5

6

7

8

9

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

0.825V

0.850V

0.875V

0.900V

0.925V

0.950V

0.975V

1.000V

1.025V

1.050V

1.075V

1.100V

1.125V

1.150V

1.175V

1.200V

2.800V

2.825V

2.850V

2.875V

2.900V

1.225V

1.250V

1.275V

1.300V

www.onsemi.com

36

FAN53880

Table 22. REGISTER DETAILS − 0x07 LDO4

0x07 LDO4

Default = 00000000

Description

Bit

Name

Default

Type

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

1.325V

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

2.925V

2.950V

1.350V

1.375V

1.400V

1.425V

1.450V

1.475V

1.500V

1.525V

1.550V

1.575V

1.600V

1.625V

1.650V

1.675V

1.700V

1.725V

1.750V

1.775V

1.800V

1.825V

1.850V

1.875V

1.900V

1.925V

1.950V

1.975V

2.000V

2.975V

3.000V

3.025V

3.050V

3.075V

3.100V

3.125V

3.150V

3.175V

3.200V

3.225V

3.250V

3.275V

3.300V

Reserved

www.onsemi.com

37

FAN53880

Table 23. REGISTER DETAILS − 0x08 IOUT

0x08 IOUT

Default = 01010101

Description

Bit

7

Name

Default

Type

UNUSED

LDO4_ILIM

6

1

R/W

Reset condition: −

Code

Current Limit

0

1

150 mA (minimum)

360 mA (minimum)

5

4

UNUSED

LDO3_ILIM

1

R/W

Code

Current Limit

150 mA (minimum)

360 mA (minimum)

0

1

3

2

UNUSED

LDO2_ILIM

Code

Current Limit

150 mA (minimum)

360 mA (minimum)

0

1

0

UNUSED

LDO1_ILIM

Code

Current Limit

150 mA (minimum)

360 mA (minimum)

0

1

Table 24. REGISTER DETAILS − 0x09 ENABLE

0x09 ENABLE

Default = 00000000

Description

Bit

Name

Default

Type

7

BST_MODE

0

R/W

Code

Effect

0

Automatically select between

PFM and PWM Modes

1

Code

0

Forced PWM mode.

6

BUCK_MODE

0

R/W

Effect

Auto selection between PFM and

PWM modes

1

Forced PWM mode

5

4

UNUSED

BUCK_EN

Enable bit for the BUCK. This bit only controls the state of the BUCK

if BUCK_SEQ = 000.

Code

Status of Buck

Disabled

0

1

Enabled

3

LDO4_EN

Enable bit for LDO4. This bit only controls the state of the LDO if

LDO4_SEQ = 000.

Code

Status of LDO4

Disabled

0

1

Enabled

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38

FAN53880

Table 24. REGISTER DETAILS − 0x09 ENABLE

0x09 ENABLE

Default = 00000000

Description

Bit

Name

Default

Type

2

LDO3_EN

0

R/W

Enable bit for LDO3. This bit only controls the state of the LDO if

LDO3_SEQ = 000.

Code

Status of LDO3

Disabled

0

1

Enabled

1

0

LDO2_EN

LDO1_EN

0

R/W

Enable bit for LDO2. This bit only controls the state of the LDO if

LDO2_SEQ = 000.

Code

Status of LDO2

Disabled

0

1

Enabled

Enable bit for LDO1. This bit only controls the state of the LDO if

LDO1_SEQ = 000.

Code

Status of LDO1

Disabled

0

1

Enabled

Table 25. REGISTER DETAILS − 0x0A BOOST_ENABLE

0x0A BOOST_ENABLE

Default = 00000000

Description

Bit

Name

Default

Type

7

BST_EN7

0

R/W

BST_EN7 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

6

5

4

3

BST_EN6

BST_EN5

BST_EN4

BST_EN3

0

R/W

BST_EN6 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

BST_EN5 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

BST_EN4 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

BST_EN3 bit is for enabling the boost converter.

Code

Effect

Diabled

Enabled

0

1

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39

FAN53880

Table 25. REGISTER DETAILS − 0x0A BOOST_ENABLE

0x0A BOOST_ENABLE

Default = 00000000

Description

Bit

Name

Default

Type

2

BST_EN2

0

R/W

BST_EN2 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

0

BST_EN1

BST_EN0

0

R/W

BST_EN1 bit is for enabling the boost converter.

Code

Effect

Disabled

Enabled

0

1

BST_EN0 bit is for enabling the boost converter.

Code

Effect

0

1

Disabled

Ensabled

Table 26. REGISTER DETAILS − 0x0B BUCK_SEQ

0x0B BUCK_SEQ

Default = 00000000

Description

Bit

7:3

2:0

Name

Default

Type

UNUSED

BUCK_SEQ

000

R/W

The buck sequencing is selected by setting bits [2:0]

Code

Effect

000

Controlled through I2C by setting

the buck_en bit.

001

010

011

100

101

110

111

Selects slot 1 for the buck to be

enabled in at power up.

Selects slot 2 for the buck to be

enabled in at power up.

Selects slot 3 for the buck to be

enabled in at power up.

Selects slot 4 for the buck to be

enabled in at power up.

Selects slot 5 for the buck to be

enabled in at power up.

Selects slot 6 for the buck to be

enabled in at power up.

Selects slot 7 for the buck to be

enabled in at power up.

www.onsemi.com

40

FAN53880

Table 27. REGISTER DETAILS − 0x0C LDO12_SEQ

0x0C LDO12_SEQ

Default = 00000000

Description

Bit

7:6

5:3

Name

Default

Type

UNUSED

LDO2_SEQ

000

R/W

The LDO2 sequencing is selected by setting bits [2:0]

Code

Effect

000

Controlled through I2C by setting

the LDO2_EN bit.

001

010

011

100

101

110

111

Selects slot 1 for the LDO2 to be

enabled in at power up.

Selects slot 2 for the LDO2 to be

enabled in at power up.

Selects slot 3 for the LDO2 to be

enabled in at power up.

Selects slot 4 for the LDO2 to be

enabled in at power up.

Selects slot 5 for the LDO2 to be

enabled in at power up.

Selects slot 6 for the LDO2 to be

enabled in at power up.

Selects slot 7 for the LDO2 to be

enabled in at power up.

2:0

LDO1_SEQ

000

R/W

The LDO1 sequencing is selected by setting bits [2:0]

Code

Effect

000

Controlled through I2C by setting

the LDO1_EN bit.

001

010

011

100

101

110

111

Selects slot 1 for the LDO1 to be

enabled in at power up.

Selects slot 2 for the LDO1 to be

enabled in at power up.

Selects slot 3 for the LDO1 to be

enabled in at power up.

Selects slot 4 for the LDO1 to be

enabled in at power up.

Selects slot 5 for the LDO1 to be

enabled in at power up.

Selects slot 6 for the LDO1 to be

enabled in at power up.

Selects slot 7 for the LDO1 to be

enabled in at power up.

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41

FAN53880

Table 28. REGISTER DETAILS − 0x0D LDO34_SEQ

0x0D LDO34_SEQ

Default = 00000000

Description

Bit

7:6

5:3

Name

Default

Type

UNUSED

LDO4_SEQ

000

R/W

The LDO4 sequencing is selected by setting bits [2:0]

Code

Effect

000

Controlled through I2C by setting

the LDO4_EN bit.

001

010

011

100

101

110

111

Selects slot 1 for the LDO4 to be

enabled in at power up.

Selects slot 2 for the LDO4 to be

enabled in at power up.

Selects slot 3 for the LDO4 to be

enabled in at power up.

Selects slot 4 for the LDO4to be

enabled in at power up.

Selects slot 5 for the LDO4 to be

enabled in at power up.

Selects slot 6 for the LDO4 to be

enabled in at power up.

Selects slot 7 for the LDO4 to be

enabled in at power up.

2:0

LDO3_SEQ

000

R/W

The LDO3 sequencing is selected by setting bits [2:0]

Code

Effect

000

Controlled through I2C by setting

the LDO3_EN bit.

001

010

011

100

101

110

111

Selects slot 1 for the LDO3 to be

enabled in at power up.

Selects slot 2 for the LDO3 to be

enabled in at power up.

Selects slot 3 for the LDO3 to be

enabled in at power up.

Selects slot 4 for the LDO3 to be

enabled in at power up.

Selects slot 5 for the LDO3 to be

enabled in at power up.

Selects slot 6 for the LDO3 to be

enabled in at power up.

Selects slot 7 for the LDO3 to be

enabled in at power up.

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42

FAN53880

Table 29. REGISTER DETAILS − 0x0E SEQUENCING

0x0E SEQUENCING

Default = 00000000

Description

Bit

Name

Default

Type

7:6

SEQ_SPEED

00

R/W

Code

Period per Slot

00

01

500 ms

1.0 ms

10

1.5 ms

2.0 ms

11

5:4

SEQ_CONTR

OL

00

W1CLR

Code

00

Effect

Default

01

Starts a converter power up sequence.

Starts a converter shutdown sequence.

Bit configuration is ignored

10

11

Note: The bits will always clear immediately when written to

and always readback 00.

3

SEQ_ON

0

Read

Code

Effect

0

1

Indicates that the sequencing is not in process

Indicates that the sequencing is executing and

somewhere between the start of slot 1 and the

end of slot 7. The bit remains a 1 until slot 7 has

completed at start−up or slot 1 has finished at

shutdown, regardless of what slots are used.

This bit is a read only status bit to indicate the sequencing is on.

2:0

SEQ_COUNT

000

Read

Code

Slot

000

Indicates sequencing has completed or not

started.

001

010

011

100

101

110

111

Indicates was in slot 1 during register read

Indicates was in slot 2 during register read

Indicates was in slot 3 during register read

Indicates was in slot 4 during register read

Indicates was in slot 5 during register read

Indicates was in slot 6 during register read

Indicates was in slot 7 during register read

These register bits provide the status of the sequencing.

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43

FAN53880

Table 30. REGISTER DETAILS − 0x0F DISCHARGE

0x0F DISCHARGE

Default = 00111111

Description

Bit

Name

Default

Type

7

BUCK_LOAD

0

R/W

Code

Effect

0

1

Buck internal load is removed from output.

Buck internal load is applied to the output during PFM

operation.

6

5

BOOST_LOAD

LDO4_DIS

0

1

R/W

Code

Effect

0

1

Boost internal load is removed from output.

Boost internal load is applied to the output during PFM

operation.

Code

Effect

0

LDO4 Active Discharge feature is disabled. Pull down will

not be activated when LDO4 is disabled by any event.

1

LDO4 Active Discharge feature is enabled. Pull down will

be activated when LDO4 is disabled by HWEN going low or

LDO4_EN = 0 or a Sequenced shutdown or in an OVP

event.

4

3

2

LDO3_DIS

LDO2_DIS

LDO1_DIS

1

R/W

Code

Effect

0

LDO3 Active Discharge feature is disabled. Pull down will

not be activated when LDO3 is disabled by any event.

1

LDO3 Active Discharge feature is enabled. Pull down will

be activated when LDO3 is disabled by HWEN going low or

LDO3_EN = 0 or a Sequenced shutdown or in an OVP

event.

Code

Effect

0

LDO2 Active Discharge feature is disabled. Pull down will

not be activated when LDO2 is disabled by any event.

1

LDO2 Active Discharge feature is enabled. Pull down will

be activated when LDO2 is disabled by HWEN going low or

LDO2_EN = 0 or a Sequenced shutdown or in an OVP

event.

Code

Effect

0

LDO1 Active Discharge feature is disabled. Pull down will

not be activated when LDO1 is disabled by any event.

1

LDO1 Active Discharge feature is enabled. Pull down will

be activated when LDO1 is disabled by HWEN going low or

LDO1_EN = 0 or a Sequenced shutdown or in an OVP

event.

1

0

BOOST_DIS

BUCK_DIS

1

R/W

Code

Effect

0

Boost Active Discharge feature is disabled. Pull down will

not be activated when Boost is disabled by any event.

1

Boost Active Discharge is enabled and output is discharged

by internal resistor when the Boost is disabled by BSTEN

going low or BST_EN0 = 0 or in an OVP event.

Code

Effect

0

Buck Active Discharge feature is disabled. Pull down will not

be activated when Buck is disabled by any event.

1

Buck Active Discharge feature is enabled. Pull down will be

activated when Buck is disabled by HWEN going low or

BUCK_EN = 0 or a Sequenced shutdown or in an OVP

event.

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44

FAN53880

Table 31. REGISTER DETAILS − 0x10 RESET

0x10 RESET

Default = 00000000

Description

Bit

7

Name

Default

Type

UNUSED

6:3

SOFT_RESET

0000

Write

Reset condition: 0

Code

Effect

1011

Writing a “1011” begins a soft reset of the device

I2C registers to their default values. This bit is

cleared upon execution of the Reset function.

Any other value than “1011” will be ignored.

2:1

0

UNUSED

FLT_SD_B

0

R/W

Code

Effect

0

Converter is shutdown if an OVP, UVP or OCP

event occurs.

1

Converter is not shutdown if an OVP, UVP or

OCP event occurs.

Notes:

− If this bit function is desired, FLT_SD_B should be set to “1” prior

to enabling any converters after a Power−On−Reset

− If a hard short occurs on either the buck or boost output, the

converter will shutdown to protect itself even if the FLT_SD_B bit is

set to “1”.

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45

FAN53880

Table 32. REGISTER DETAILS − 0x11 INTERRUPT1

0x11 INTERRUPT1

Default = 00000000

Description

Bit

Name

Default

Type

7

LDO4_OVP_INT

0

R/CLR

Code

Effect

0

1

Clear

Over−Voltage event detected on LDO4 output

or the voltage has fallen below the

OVP_Falling threshold.

6

5

4

3

2

1

0

LDO3_OVP_INT

LDO2_OVP_INT

LDO1_OVP_INT

LDO4_UVP_INT

LDO3_UVP_INT

LDO2_UVP_INT

LDO1_UVP_INT

0

Code

Effect

0

1

Clear

Over Voltage event detected on LDO3

output or the voltage has fallen below the

OVP_Falling threshold.

Code

Effect

0

1

Clear

Over−Voltage event detected on LDO2

output or the voltage has fallen below the

OVP_Falling threshold.

Code

Effect

0

1

Clear

Over−Voltage event detected on LDO1

output or the voltage has fallen below the

OVP_Falling threshold.

Code

Effect

0

1

Clear

Under−Voltage event detected on LDO4

output or the voltage has risen above the

UVP_Rising threshold.

Code

Effect

0

1

Clear

Under−Voltage event detected on the output of

LDO3 or the voltage has risen above the

UVP_Rising threshold.

Code

Effect

0

1

Clear

Under−Voltage event detected on LDO2

output or the voltage has risen above the

UVP_Rising threshold.

Code

Effect

0

1

Clear

Under−Voltage event detected on LDO1

output or the voltage has risen above the

UVP_Rising threshold.

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46

FAN53880

Table 33. REGISTER DETAILS − 0x12 INTERRUPT2

0x12 INTERRUPT2

Default = 00000000

Description

Bit

Name

Default

Type

7

BST_OVP_INT

0

R/CLR

Code

Effect

0

1

Clear

Over−Voltage event detected on the Boost

output or the voltage has fallen below the

OVP_Falling threshold.

6

5

4

3

2

1

0

BUCK_OVP_IN

T

0

Code

Effect

0

1

Clear

Over−Voltage event detected on the Buck

output or the voltage has fallen below the

OVP_Falling threshold.

BST_UVP_INT

Code

Effect

0

1

Clear

Under−Voltage event detected on on the

Boost output or the voltage has risen above

the UVP_Rising threshold.

BUCK_UVP_IN

T

Code

Effect

0

1

Clear

Under−Voltage event detected on on the Buck

output or the voltage has risen above the

UVP_Rising threshold.

LDO4_OCP_IN

T

Code

Effect

0

1

Clear

Over−Current event detected on LDO4

output or that a successful restart has

occurred after an OCP event.

LDO3_OCP_IN

T

Code

Effect

0

1

Clear

Over−Current event detected on LDO3

output or that a successful restart has

occurred after an OCP event.

LDO2_OCP_IN

T

Code

Effect

0

1

Clear

Over−Current event detected on LDO2

output or that a successful restart has

occurred after an OCP event.

LDO1_OCP_IN

T

Code

Effect

0

1

Clear

Over−Current event detected on LDO1

output or that a successful restart has

occurred after an OCP event.

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47

FAN53880

Table 34. REGISTER DETAILS − 0x13 INTERRUPT3

0x13 INTERRUPT3

Default = 00000000

Description

Bit

Name

Default

Type

7

BST_IPK_INT

0

R/CLR

Code

Effect

0

1

Clear

Boost Peak Current limit reached or the Boost

successfully completed a restart after a Peak Current

fault.

6

5

BUCK_IPK_INT

0

R/CLR

Code

Effect

0

1

Clear

Buck Peak Current reached or the Buck successfully

completed a restart after a Peak Current fault.

APVIN_UVLO_INT

Code

Effect

0

1

Normal operation

Indicates that the AV and/or PV power fell below

IN

the UVLO input threshold or that the supplies have

risen above the rising thresholds after a UVLO fault.

Reading the the associated status bit provides present state of the input

voltage.

4

3

2

LDO12_UVLO_INT

LDO3_UVLO_INT

LDO4_UVLO_INT

0

R/CLR

Code

Effect

0

1

Normal operation

Indicates V

fell below the UVLO threshold while

LDO1 and/or LDO2 are enabled or that the supply has

risen above the rising thresholds after a UVLO fault.

IN12

Reading the the associated status bit provides present state of the input

voltage.

Code

Effect

0

1

Normal Operation

Indicates that the V

fell below the UVLO threshold

IN3

while LDO3 was enabled or that the supply has risen

above the rising thresholds after a UVLO fault.

Reading the the associated status bit provides present state of the input

voltage.

Code

Effect

0

1

Normal Operation

Indicates V

fell below the UVLO threshold while

LDO4 where enabled or that the supply has risen

above the rising thresholds after a UVLO fault.

IN4

Reading the the associated status bit provides present state of the input

voltage.

1

0

TSD_INT

0

R/CLR

Code

Effect

0

1

Clear

A Thermal Shutdown event detected or that the

temperature has fallen below the hysteresis level.

TSD_WRN_INT

Code

Effect

0

1

Clear

Thermal Shutdown Warning threshold was

surpassed or that the temperature has fallen below the

hysteresis level.

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48

FAN53880

Table 35. REGISTER DETAILS − 0x14 STATUS1

0x14 STATUS1

Default = 00000000

Description

Bit

Name

Default

Type

7

LDO4_OVP_STAT

0

Read

Code

Effect

0

Clear

1

An Over−Voltage condition exists on LDO4 output

6

5

4

3

2

LDO3_OVP_STAT

LDO2_OVP_STAT

LDO1_OVP_STAT

LDO4_UVP_STAT

LDO3_UVP_STAT

0

Read

Code

Effect

0

Clear

1

An Over−Voltage condition exists on LDO3 output.

Code

Effect

0

Clear

1

An Over−Voltage condition exists on LDO2 output

Code

Effect

0

Clear

1

An Over−Voltage condition exists on LDO1 output

Code

Effect

0

Clear

1

Code

0

An Under−Voltage condition exists on LDO4 output.

Effect

Clear

1

An Under−Voltage condition exists on the output of

LDO3

1

0

LDO2_UVP_STAT

LDO1_UVP_STAT

0

Read

Code

Effect

0

Clear

1

Code

0

An Under−Voltage condition exists on LDO2 output

Effect

Clear

1

An Under−Voltage condition exists on LDO1 output

Table 36. REGISTER DETAILS − 0x15 STATUS2

0x15 STATUS2

Default = 00000000

Bit

Name

Default

Type

Description

7

BST_OVP_STAT

0

Read

Code

Effect

0

Clear

1

An Over−Voltage condition exists on the Boost output.

6

5

BUCK_OVP_STAT

BST_UVP_STAT

0

Read

Code

Effect

0

Clear

1

Code

0

An Over−Voltage condition exists on the Buck output.

Effect

Clear

1

An Under−Voltage condition exists on the Boost

output.

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49

FAN53880

Table 36. REGISTER DETAILS − 0x15 STATUS2

4

BUCK_UVP_STAT

0

Read

Code

Effect

0

1

Clear

An Under−Voltage condition exists on the Buck

output.

3

2

1

0

LDO4_OCP_STAT

LDO3_OCP_STAT

LDO2_OCP_STAT

LDO1_OCP_STAT

0

Read

Code

Effect

0

Clear

1

An Over−Current condition exists on LDO4 output

Code

Effect

0

Clear

1

An Over−Current condition exists on LDO3 output

Code

Effect

0

Clear

1

Code

0

An Over−Current condition exists on LDO2 output

Effect

Clear

1

An Over−Current condition exists on LDO1 output

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FAN53880

Table 37. REGISTER DETAILS − 0x16 STATUS3

0x16 STATUS3

Default = 00000000

Description

Bit

Name

Default

Type

7

BST_IPK_STAT

0

Read

Code

Effect

0

Clear

1

Code

0

Boost is hitting the Peak Current limit.

6

5

BUCK_IPK_STAT

0

Read

Effect

Clear

1

The Buck is hitting the Peak Current limit

Reset condition: 0

Effect

APVIN_UVLO_STAT

Code

0

1

Normal Operation

Indicates AV and/or PV are below the UVLO

IN

threshold.

4

3

2

LDO12_UVLO_STAT

LDO3_UVLO_STAT

LDO4_UVLO_STAT

0

Read

Code

Effect

0

1

Normal Operation

indicates V

is below the UVLO threshold while

LDO1 and/or LDO2 have been enabled.

IN12

Code

Effect

0

1

Normal Operation

Indicates V

power rail is below the UVLO

threshold while LDO3 is enabled.

IN3

Code

Effect

0

1

Normal Operation

Indicates V

is below the UVLO threshold while

LDO4 is been commanded to be enabled.

IN4

1

0

TSD_STAT

0

Read

Code

Effect

0

Clear

1

Code

0

The device is in thermal shutdown (TSD)

TSD_WRN_STAT

Effect

Clear

1

The temperature is above the Thermal Shutdown

Warning threshold and shutdown is impending.

Table 38. REGISTER DETAILS − 0x17 MINT1

0x17 MINT1

Default = 00000000

Description

Bit

Name

Default

Type

7

MASK_LDO4_OVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO4 Over−Voltage

interrupt occurs.

6

MASK_LDO3_OVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO3 Over−Voltage

interrupt occurs.

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51

FAN53880

Table 38. REGISTER DETAILS − 0x17 MINT1

0x17 MINT1

Default = 00000000

Description

Bit

Name

Default

Type

5

MASK_LDO2_OVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO2 Over−Voltage

interrupt occurs.

4

3

2

1

0

MASK_LDO1_OVP

MASK_LDO4_UVP

MASK_LDO3_UVP

MASK_LDO2_UVP

MASK_LDO1_UVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO1 Over−Voltage

interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO4

Under−Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO3

Under−Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO2

Under−Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO1

Under−Voltage interrupt occurs.

Table 39. REGISTER DETAILS − 0x18 MINT2

0x18 MINT2

Default = 00000000

Description

Bit

Name

Default

Type

7

MASK_BST_OVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Boost Over−Voltage

interrupt occurs.

6

5

4

MASK_BUCK_OVP

MASK_BST_UVP

MASK_BUCK_UVP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Buck Over−Voltage

interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Boost

Under−Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Buck Under−Voltage

interrupt occurs.

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52

FAN53880

Table 39. REGISTER DETAILS − 0x18 MINT2

0x18 MINT2

Default = 00000000

Description

Bit

Name

Default

Type

3

MASK_LDO4_OCP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO4 Over−Current

interrupt occurs.

2

1

0

MASK_LDO3_OCP

MASK_LDO2_OCP

MASK_LDO1_OCP

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO3 Over−Current

interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO2 Over−Current

interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when LDO1 Over−Current

interrupt occurs.

Table 40. REGISTER DETAILS − 0x19 MINT3

0x19 MINT3

Default = 00000000

Description

Bit

Name

Default

Type

7

MASK_BST_IPK

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Boost Peak

Current limit interrupt occurs.

6

5

4

3

2

MASK_BUCK_IPK

MASK_APVIN_UVLO

MASK_LDO12_UVLO

MASK_LDO3_UVLO

MASK_LDO4_UVLO

0

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when Buck Peak Current

limit interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when AV /PV Input

IN

Power Under Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when V

Input Power

IN12

Under Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when V

Input Power

IN3

Under Voltage interrupt occurs.

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when V

Input Power

IN4

Under Voltage interrupt occurs.

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53

FAN53880

Table 40. REGISTER DETAILS − 0x19 MINT3

0x19 MINT3

Default = 00000000

Description

Bit

Name

Default

Type

1

MASK_TSD

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB pin is not pulled low when a Thermal

Shutdown interrupt occurs.

0

MASK_TSD_WRN

0

R/W

Code

Effect

0

1

No masking of interrupt.

INTB Pin is not pulled low when a Thermal

Shutdown Warning interrupt occurs.

Table 41. REGISTER DETAILS − 0x1A STATUS4

0x1A STATUS4

Default = 00000000

Description

Bit

7

Name

Default

Type

UNUSED

6

CHIP_SUSD

0

Read

Code

Effect

0

1

Chip normal state

The entire chip has been suspended due to a global

fault condition.

5

4

3

2

1

0

BOOST_SUSD

BUCK_SUSD

LDO4_SUSD

LDO3_SUSD

LDO2_SUSD

LDO1_SUSD

0

Read

Code

Effect

0

1

Boost normal state

Boost converter has been suspended due to a fault

condition.

Code

Effect

0

1

Buck in normal state.

Buck converter has been suspended due to a fault

condition.

Code

Effect

0

1

LDO4 in normal state.

LDO4 converter has been suspended due to a fault

condition.

Code

Effect

0

1

LDO3 in a normal state

LDO3 converter has been suspended due to a fault

condition.

Code

Effect

0

1

LDO2 in normal state

LDO2 converter has been suspended due to a fault

condition.

Code

Effect

0

1

LDO1 is in normal state

LDO1 converter has been suspended due to a fault

condition.

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54

FAN53880

APPLICATION CIRCUIT

Application Circuit Diagram

PVIN

AVIN

SW1

L1

CPVIN

CBUCK

PGND1

FB1

CAVIN

CVIN12

CVIN3

LDO1

AGND

VIN12

CLDO1

CLDO3

LDO2

CLDO2

LDO3

LDO4

VIN3

VIN4

FAN53880

CVIN4

CLDO4

VBST

SW2

CBST

L2

PGND2

CBSTIN

HWEN

SCL

BSTEN

N/C

SDA

N/C

INTB

DGND

Figure 37. Application Diagram

Application Circuit Components

Table 42. RECOMMENDED EXTERNAL COMPONENTS

Component

Manufacturer

TDK

Part Number

Value

10 mF

22 mF

2.2 mF

Case Size

Voltage Rating

6.3 V

C

C1005X5R0J106M050BC

GRM188R61A226ME15D

GRM033R60J225ME47D

0402/1005 (1.0mm x 0.5mm)

0603/1608 (1.6mm x 0.8mm)

0201/0603 (0.6mm x 0.3mm)

PVIN

BUCK

BSTIN

C

TDK

6.3 V

C

TDK

6.3 V

C

Murata

10 V

BST

C

, C

VIN4

,

6.3 V

VIN12

VIN3

C

, C

LDO3

,

Murata

GRM033R60J225ME47D

2.2 mF

4.7 mF

0201/0603 (0.6mm x 0.3mm)

0402/1005 (1.0mm x 0.5mm)

6.3 V

LDO1

LDO2

, C

LDO4

C

TDK

C1005X5R0J475M

MEKK2016T1R0M

AVIN

L1

Taiyo Yuden

1.0 mH, I

= 4.0 A,

0806/2016 (2.0mm x 1.6mm x

1.0mm)

SAT

R

= 50 mW

DC

L2

Taiyo Yuden

MEKK2012HR47M

0.47 mH, I

= 5.3 A,

0805/2012 (2.0mm x 1.2mm x

1.0mm)

SAT

R

= 25 mW

DC

www.onsemi.com

55

FAN53880

Recommended Alternative Components

Table 43. ALTERNATIVE COMPONENTS

Component

Manufacturer

Taiyo Yuden

Semco

Part Number

Value

10 mF

22 mF

2.2 mF

Case Size

Voltage Rating

6.3 V

C

JMK105CBJ106MV

CL10A226MP8NUXE

CLO3A225MQCRNC

0402/1005 (1.0mm x 0.5mm)

0603/1608 (1.6mm x 0.8mm)

0201/0603 (0.6mm x 0.3mm)

PVIN

BUCK

BSTIN

C

6.3 V

C

6.3 V

C

10 V

BST

C

, C

LDO3

,

Semco

6.3 V

LDO1

LDO2

LDO4

C

, C

L1

TDK

TFM201610GHM−1R0MTAA 1.0 mH, I

= 3.8 A, 2016 (2.0mm x 1.6mm x 1.0mm)

SAT

R

= 50 mW

DC

www.onsemi.com

56

FAN53880

APPLICATION GUIDELINES

Buck Input Capacitor Considerations

A minimum capacitance of 2.2 mF with ceramic

the PWM−to−PFM transition point, output voltage ripple,

and efficiency.

dielectric, input capacitor should be placed as close as

The ripple current (DI) of the regulator is:

possible between the V pin and GND to minimize the

parasitic inductance. If a long wire is used to bring power to

the IC, additional “bulk” capacitance (electrolytic or

IN

V_OUT

V_IN

V

_IN* V_OUT

L @ f_SW

_@ǒ

Ǔ

DI [

The maximum average load current, I

related to the peak current limit, I

current, given by:

is

MAX(LOAD),

tantalum) should be placed between C and the power

IN

, by the ripple

LIM(PK)

source lead to reduce the ringing that can occur between the

inductance of the power source leads and C .

IN

The effective capacitance value decreases as

DI

2

I

_MAX(LOAD)+ I_LIM(PK)*

V

increases due to DC bias effects.

IN

The FAN53880 is optimized for operation with L = 1.0uH.

The inductor should be rated to maintain at least 80% of its

Buck Output Capacitor Considerations

FAN53880 uses a 22 mF, 0402 (1005 metric) for an output

capacitor. The effective capacitance of ceramic capacitors

decrease as the bias voltage across the capacitor increases.

Increasing the output capacitor has no effect on loop stability

and therefore to overcome the effects of bias voltage across

value at I

. It is recommended to select an inductor

LIM(PK)

where its saturation current is above the I

value.

LIM(PK)

Efficiency is affected by the inductor DCR and inductance

value. Decreasing the inductor value for a given physical

size typically decreases the DCR; but because DI increases,

the RMS current increases, as do the core and skin effect

losses.

C

OUT

, the capacitor value can be increased to reduce the

output voltage ripple and/or to improve transient response.

Output voltage ripple is defined as:

V_OUT

V_IN

V

_IN* V_OUT

L @ f_SW

_@ǒ

Ǔ

DI [

f

_SW@ C_OUT@ ESR²

2 @ D @ (1 * D)

1

ƪ

ƫ

DV_OUT+ DI_L

)

8 @ f_SW@ C_OUT

The increased RMS current produces higher losses

through the R of the IC MOSFETs, as well as the

DS(ON)

Buck Inductor Considerations

inductor DCR. Increasing the inductor value produces lower

RMS currents, but degrades transient response. For a given

physical inductor size, increased inductance usually results

in an inductor with lower saturation current and higher DCR.

The output inductor must meet both the required

inductance and the energy−handling capability of the

application. The inductor value affects average current limit,

Table 44.

Inductor Value

Increase

I

DV

Transient Response

Degraded

MAX(LOAD)

OUT

Increase

Decrease

Increase

Decrease

Improved

www.onsemi.com

57

FAN53880

Boost Input Capacitor Considerations

The 10 mF ceramic 0402 (1005 metric) input capacitor

LDO Input Capacitor Considerations

If long wires are used to bring power to an evaluation

board, additional “bulk” capacitance (electrolytic or

tantalum) should be placed (on Eval board) between

should be placed as close as possible between the V pin

IN

and GND to minimize the parasitic inductance. If a long wire

is used to bring power to the IC, additional “bulk”

capacitance (electrolytic or tantalum) should be placed (on

C

IN

and the power source lead to reduce ringing that can

occur between the inductance of the power source leads and

C .

Eval board) between C and the power source lead to

IN

reduce the ringing that can occur between the inductance of

The effective capacitance value decreases as

V increases due to DC bias effects. Adding additional

IN

the power source leads and C .

IN

The effective capacitance value decreases as

capacitance to the minimum recommended ensures reliable

operation.

V

increases due to DC bias effects.

IN

Boost Output Capacitor

LDO Output Capacitor Considerations

Output voltage ripple is inversely proportional to C

.

FAN53880 LDO’s are tuned for high load capacitance of

2.2 to 26 mF. Total capacitance on the LDO output that is

outside this window may result in instability or as a

minimum, the LDO not meeting the performance listed in

the Electrical and System Characteristics tables. For

instance: Adding additional capacitance can slow the soft

start when the LDO is enabled but also improves transient

response. The effective capacitance of ceramic capacitors

decrease as the bias voltage across the capacitor increases.

BST

During t , when the boost switch is on, all load current is

ON

supplied by C . The maximum V

occurs when V

BST

RIPPLE

IN

is minimum and I

is maximum.

LOAD

It is recommended to use the capacitor shown in either the

Recommended External Components or the Alternate

Components table. If a different component is chosen, it is

important that it’s effective capacitance is equal to or greater

than that of the Recommended Component. For better ripple

performance, additional output capacitance can be added.

Boost Inductor Considerations

The FAN53880 employs a peak current limiting, so peak

inductor current can reach 4 A for a short duration during

overload conditions. Saturation effects causes the inductor

current ripple to become higher under high loading, as only

the peak of the inductor current ripple is controlled.

www.onsemi.com

58

FAN53880

Recommended Layout

All Layer Layout

Figure 38. All Layer Layout

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59

FAN53880

Layer 1

Figure 39. Layer 1

www.onsemi.com

60

FAN53880

Layer 2, Ground Plane

Figure 40. Layer 2, Ground Plane

www.onsemi.com

61

FAN53880

Layer 3, Signal Plane

Figure 41. Layer 3, Signal Plane

www.onsemi.com

62

FAN53880

Layer 4, Power Plane

Figure 42. Layer 4, Power Plane

Layout Considerations

For thermal reasons, it is suggested to maximize the pour

To minimize spikes for the buck at V

, C

must be

area for all planes other than SW. Especially the ground pour

should be set to fill all available PCB surface area and tied

to internal layers with a cluster of thermal vias.

OUT OUT

placed as close as possible to PGND1 and VOUT, as shown

in the recommended layout. For the boost, CIN should be

located as close to PGND2 as possible to minimize the

spikes and noise generated by the switching node LX2.

www.onsemi.com

63

FAN53880

PACKAGE DIMENSIONS

WLCSP25 2.16x2.16x0.586

CASE 567QT

ISSUE A

Table 45. PRODUCT SPECIFIC DIMENSIONS

Product

D (mm)

E (mm)

X (mm)

Y (mm)

FAN53880

2.16

0.08

www.onsemi.com

64

FAN53880

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65


型号：	FAN53880UC002X
厂家：	ONSEMI
描述：	一个降压，一个升压和四个 LDO PMIC 集成电源管理电路
文件：	总66页 (文件大小：3602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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