FAM65HR51XS1 [ONSEMI]
H-Bridge in APM16 Series for LLC and Phase-shifted DC-DC Converter;
| 型号： | FAM65HR51XS1 |
| 厂家： | 
ONSEMI |
| 描述： | H-Bridge in APM16 Series for LLC and Phase-shifted DC-DC Converter |
| 文件： | 总12页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H-Bridge in APM16 Series
for LLC and Phase-shifted
DC-DC Converter
FAM65HR51XS1,
FAM65HR51XS2
www.onsemi.com
Features
• SIP or DIP H−Bridge Power Module for On−board Charger (OBC) in
EV or PHEV
• 5 kV/1 sec Electrically Isolated Substrate for Easy Assembly
• Creepage and Clearance per IEC60664−1, IEC 60950−1
• Compact Design for Low Total Module Resistance
• Module Serialization for Full Traceability
• Lead Free, RoHS and UL94V−0 Compliant
• Automotive Qualified per AEC Q101 and AQG324 Guidelines
APMCA−A16
16 LEAD
CASE MODGF
Applications
• DC−DC Converter for On−board Charger in EV or PHEV
Benefits
• Enable Design of Small, Efficient and Reliable System for Reduced
Vehicle Fuel Consumption and CO Emission
2
• Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
APMCA−B16
16 LEAD
CASE MODGJ
MARKING DIAGRAM
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
XXXX = Specific Device Code
ZZZ = Lot ID
AT
Y
= Assembly & Test Location
= Year
W
= Work Week
NNN = Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
June, 2021 − Rev. 3
FAM65HR51XS1/D
FAM65HR51XS1, FAM65HR51XS2
ORDERING INFORMATION
Snubber
DBC
Pb−Free and
Operating
Packing
Capacitor Inside Material RoHS Compliant Temperature (T ) Method
Part Number
FAM65HR51XS1
FAM65HR51XS2
Package
Lead Forming
Y−Shape
A
APM16−CAA
APM16−CAB
Yes
Yes
ALN
ALN
Yes
Yes
−40°C ~ 125°C
−40°C ~ 125°C
Tube
Tube
L−Shape
Pin Configuration and Description
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
AC1
Pin Description
Phase 1 Leg of the H−Bridge
Source Sense of Q1
1, 2
3
Q1 Sense
Q1 Gate
B+
4
Gate Terminal of Q1
5, 6
7, 8
9
Positive Battery Terminal
Negative Battery Terminal
Source Sense of Q2
B−
Q2 Sense
Q2 Gate
Q4 Sense
Q4 Gate
Q3 Sense
Q3 Gate
AC2
10
Gate Terminal of Q2
11
Source Sense of Q4
12
Gate Terminal of Q4
13
Source Sense of Q3
14
Gate Terminal of Q3
15, 16
Phase 2 Leg of the H−Bridge
www.onsemi.com
2
FAM65HR51XS1, FAM65HR51XS2
INTERNAL EQUIVALENT CIRCUIT
Figure 2. Internal Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Max
Unit
V
V
V
(Q1~Q4)
(Q1~Q4)
Drain−to−Source Voltage
Gate−to−Source Voltage
650
DS
GS
20
V
Drain Current Continuous (T = 25°C, V = 10 V) (Note 1)
64
40
A
I
D
(Q1~Q4)
C
GS
Drain Current Continuous (T = 100°C, V = 10 V) (Note 1)
A
C
GS
E
E
(Q1~Q4)
(Q1~Q4)
Single Pulse Avalanche Energy (Note 2)
623
mJ
mJ
A
AS
Single Pulse Avalanche Energy (Note 2)
Avalanche Current
21
AS
I
AS
6.5
P
Power Dissipation (Note 1)
Maximum Junction Temperature
Maximum Case Temperature
Storage Temperature
463
W
°C
°C
°C
D
T
−55 to +150
−40 to +125
−40 to +125
J
T
C
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum continuous current and power, without switching losses, to reach T = 150°C respectively at T = 25°C and T = 100°C; defined
J
C
C
by design based on MOSFET R
and R
and not subject to production test
q
DS(ON)
JC
2. 623 mJ is characterized at T = 25°C, L = 29.5 mH, I = 6.5 A, V = 145 V.
J
AS
DD
21 mJ is 100% tested at L = 1 mH, I = 6.5 A.
AS
Table 3. COMPONENTS (Note 3)
Device
Parameter
Capacitance
Rated Voltage
Condition
Min
Typ
150
630
Max
165
−
Unit
nF
V
Capacitor (Snubber)
AEC Q200 qualified
T = 25°C
J
135
−
3. These values are obtained from the specification provided by the manufacturer.
DBC Substrate
Flammability Information
0.63 mm ALN alumina with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
All materials present in the power module meet UL
flammability rating class 94V−0.
Lead Frame
Compliance to RoHS Directives
OFC copper alloy, 0.50 mm thick. Plated with 8 um to
25.4 um thick Matte Tin
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
Solder
Solder used is a lead free SnAgCu alloy.
www.onsemi.com
3
FAM65HR51XS1, FAM65HR51XS2
Solder presents high risk to melt at temperature beyond
mounting on the PCB or during welding to prevent the
210°C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200°C during
re−melting of the solder joints.
Table 4. ELECTRICAL SPECIFICATIONS (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Conditions
I = 1 mA, V = 0 V
D
Min
650
3.0
−
Typ
−
Max
−
Unit
V
BV
Drain−to−Source Breakdown Voltage
Gate to Source Threshold Voltage
Q1 – Q4 MOSFET On Resistance
Q1 – Q4 MOSFET On Resistance
Forward Transconductance
DSS
GS
V
GS(th)
V
GS
= V , I = 3.3 mA
−
5.0
51
−
V
DS
D
R
R
V
GS
= 10 V, I = 20 A
44
79
30
−
mW
mW
S
DS(ON)
DS(ON)
D
V
GS
= 10 V, I = 20 A, T = 125°C (Note 4)
−
D
J
g
FS
V
DS
= 20 V, I = 20 A (Note 4)
−
−
D
I
Gate−to−Source Leakage Current
Drain−to−Source Leakage Current
V
=
20 V, V = 0 V
−100
−
+100
10
nA
mA
GSS
GS
DS
DS
I
V
= 650 V, V = 0 V
−
DSS
GS
DYNAMIC CHARACTERISTICS (Note 4)
C
Input Capacitance
V
V
f = 1 MHz
= 400 V
−
−
−
−
−
−
−
−
4864
109
16
−
−
−
−
−
−
−
−
pF
pF
pF
pF
W
iss
DS
= 0 V
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Effective Output Capacitance
Gate Resistance
rss
C
V
DS
= 0 to 520 V, V = 0 V
652
2
oss(eff)
GS
R
f = 1 MHz
g
Q
Total Gate Charge
V
DS
= 380 V
= 20 A
= 0 to 10 V
123
37.5
49
nC
nC
nC
g(tot)
I
D
Q
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
gs
V
GS
Q
gd
SWITCHING CHARACTERISTICS (Note 4)
t
Turn−on Time
V
= 400 V
= 20 A
−
−
−
−
−
−
87
47
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
on
DS
I
D
t
t
Turn−on Delay Time
Turn−on Rise Time
Turn−off Time
d(on)
V
R
= 10 V
GS
t
r
43
= 4.7 W
G
t
148
118
29
off
d(off)
Turn−off Delay Time
Turn−off Fall Time
t
f
BODY DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
Reverse Recovery Time
I
= 20 A, V = 0 V
−
−
−
0.95
133
669
−
−
−
V
SD
SD
GS
T
V
= 520 V, I = 20 A,
ns
nC
rr
DS
t
D
d /d = 100 A/ms (Note 4)
I
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Defined by design, not subject to production test
Table 5. THERMAL RESISTANCE
Parameters
Min
−
Typ
0.19
0.75
Max
0.27
−
Unit
°C/W
°C/W
R
R
(per chip)
(per chip)
Q1~Q4 Thermal Resistance Junction−to−Case (Note 5)
Q1~Q4 Thermal Resistance Junction−to−Sink (Note 6)
θ
JC
JS
−
θ
5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 6. ISOLATION (Isolation resistance at tested voltage from the base plate to control pins or power terminals.)
Test
Test Conditions
Isolation Resistance
Unit
Leakage @ Isolation Voltage (Hi−Pot)
V
AC
= 5 kV, 50 Hz
100M <
W
www.onsemi.com
4
FAM65HR51XS1, FAM65HR51XS2
PARAMETER DEFINITIONS
Reference to Table 4: Parameter of Electrical Specifications
BV
Q1 – Q4 MOSFET Drain−to−Source Breakdown Voltage
DSS
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
The measurement conditions are to be found in Table 4.
The typ. Temperature behavior is described in Figure 13
V
GS(th)
Q1 – Q4 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 3.
The typ. Temperature behavior can be found in Figure 12
R
Q1 – Q4 MOSFET On Resistance
DS(ON)
RDS(on) is the total resistance between the source and the drain during the on state.
The measurement conditions are to be found in Table 4.
The typ behavior can be found in Figure 10 and Figure 11 as well as Figure 17
g
FS
Q1 – Q4 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFET, expressed in the Equation below.
It describes the change in drain current by the change in the gate−source bias voltage: g = [ DI / DV ]
fs
DS
GS VDS
I
Q1 – Q4 MOSFET Gate−to−Source Leakage Current
GSS
The current flowing from Gate to Source at the maximum allowed VGS
The measurement conditions are described in the Table 4.
I
Q1 – Q4 MOSFET Drain−to−Source Leakage Current
DSS
Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the
gate is shorted to the source.
IDSS has a positive temperature coefficient.
www.onsemi.com
5
FAM65HR51XS1, FAM65HR51XS2
Figure 3. Timing Measurement Variable Definition
Table 7. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (t
)
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
d(on)
Rise Time (t )
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current ID.
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
r
Turn−On Time (t
)
Is the sum of turn−on−delay and rise time
on
Turn−Off Delay (t
)
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current ID is still flowing
d(off)
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
Fall Time (t )
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage VDS rises accordingly.
The measurement conditions are described in the Table 4.
f
For signal definition please check Figure 3 above.
Turn−Off Time (t
)
Is the sum of turn−off−delay and fall time
off
www.onsemi.com
6
FAM65HR51XS1, FAM65HR51XS2
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
70
60
V
= 10 V
GS
50
40
30
20
R
= 0.27°C/W
q
JC
R
= 0.27°C/W
q
JC
0.2
0
10
0
0
3
0
25
50
75
100
125
150
25
50
75
100
125
150
T , CASE TEMPERATURE (°C)
T , CASE TEMPERATURE (°C)
C
C
Figure 4. Normalized Power Dissipation vs.
Case
Figure 5. Maximum Continuous ID vs. Case
Temperature
V = 0 V
GS
60
50
40
30
20
V
= 20 V
DS
100
10
1
T = 25°C
J
T = 150°C
T = 25°C
J
J
0.1
T = 150°C
J
10
0
T = −55°C
J
0.01
4
5
6
7
8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
, GATE−TO−SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
GS
Figure 6. Transfer Characteristics
Figure 7. Forward Diode
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
V
= 15 V
10 V
GS
8.0 V
V
GS
= 15 V
10 V
7.0 V
6.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
5.5 V
5.0 V
10
0
10
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30
40 50 60 70
80 90 100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. On Region Characteristics (255C)
Figure 9. On Region Characteristics (1505C)
www.onsemi.com
7
FAM65HR51XS1, FAM65HR51XS2
TYPICAL CHARACTERISTICS
200
150
100
2.5
I
V
= 20 A
I
D
= 20 A
D
= 10 V
GS
2.0
1.5
1.0
T = 150°C
J
T = 25°C
J
50
0
0.5
0
5.5
6.5
7.5
8.5
9.5
−75 −50 −25
0
25
50 75 100 125 150 175
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. On−Resistance vs. Gate−to−Source
Figure 11. RDS(norm) vs. Junction Temperature
Voltage
1.2
1.0
1.2
1.1
1.0
I
D
= 3.3 mA
I = 10 A
D
0.8
0.6
0.9
0.8
−75 −50 −25
0
25 50 75 100 125 150 175
−75 −50 −25
0
25 50 75 100 125 150 175
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 12. Normalized Gate Threshold Voltage
vs. Temperature
Figure 13. Normalized Breakdown Voltage vs.
Temperature
30
25
20
15
10
100K
10K
1K
C
ISS
C
C
OSS
100
RSS
V
= 0 V
GS
10
1
5
0
f = 1 MHz
0
100
200
300
400
500
600
700
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 14. Eoss vs. Drain−to−Source Voltage
Figure 15. Capacitance Variation
www.onsemi.com
8
FAM65HR51XS1, FAM65HR51XS2
TYPICAL CHARACTERISTICS
10
8
0.060
T
C
= 25°C
V
DD
= 130 V
0.055
0.050
V
DD
= 400 V
V
GS
= 10 V
6
4
V
GS
= 20 V
0.045
0.040
2
0
0
40
80
120
160
0
20
40
60
80
Q , GATE CHARGE (nC)
G
I , DRAIN CURRENT (A)
D
Figure 16. Gate Charge Characteristics
Figure 17. ON−Resistance Variation with Drain
Current and Gage Voltage
1000
100
10
T
R
= 25°C
For temperatures above 25°C
C
= 0.27°C/W
derate peak current as follows:
q
JC
100
Single Pulse
1 ms
150 * T
C
Ǹ
I + I
2
125
10 ms
Limited I
240 A
DM
100 ms
1 ms
10 ms
100
Notes:
= 0.27°C/W
1
R
Limit
DS(on)
R
100 ms
q
JC
Thermal Limit
Package Limit
Peak T = P
x Z (t) + T
q
JC C
J
DM
Single Pulse
0.000001 0.00001 0.0001 0.001
t, PULSE WIDTH (sec)
Duty Cycle, D = t /t
1
2
0.1
10
0.1
1
10
1000
0.01
0.1
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 18. Safe Operating Area
Figure 19. Peak Current Capability
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
0.01
Notes:
Single Pulse
R
= 0.27°C/W
q
JC
t
Peak T = P
x Z (t) + T
q
JC C
1
J
DM
t
Duty Cycle, D = t /t
2
1
2
0.001
0.00001
0.0001
0.001
t, PULSE WIDTH (sec)
0.01
0.1
1
Figure 20. Transient Thermal Impedance
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
CASE MODGF
ISSUE C
DATE 03 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
W
= Assembly & Test Location
= Year
= Work Week
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94732G
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA−B16 / 16LD, AUTOMOTIVE MODULE
CASE MODGJ
ISSUE C
DATE 03 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
W
= Assembly & Test Location
= Year
= Work Week
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON97133G
APMCA−B16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明