ESD7421 [ONSEMI]
ESD Protection Diodes;
| 型号： | ESD7421 |
| 厂家： | 
ONSEMI |
| 描述： | ESD Protection Diodes |
| 文件： | 总6页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7421, SZESD7421
ESD Protection Diodes
Micro−Packaged Diodes for ESD Protection
The ESD7421 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, and fast
response time provide best in class protection on designs that are
exposed to ESD. Because of its small size, it is suited for use in cellular
phones, automotive sensors, infotainment, MP3 players, digital
cameras and many other applications where board space comes at a
premium.
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Pin 1
Pin 2
Specification Features
• Low Capacitance 0.3 pF
• Low Clamping Voltage
• Low Leakage 100 nA
MARKING
DIAGRAM
• Response Time is < 1 ns
• IEC61000−4−2 Level 4 ESD Protection
5 M
G
XDFN2
(SOD−882)
CASE 711AM
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
5
= Specific Device Code
= Date Code
= Pb−Free Package
M
G
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
MAXIMUM RATINGS
†
Device
Package
Shipping
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
ESD7421N2T5G
XDFN2
8000 /
Contact
Air
12
15
kV
(Pb−Free)
Tape & Reel
SZESD7421N2T5G
XDFN2
(Pb−Free)
8000 /
Tape & Reel
Total Power Dissipation on FR−5 Board
°P °
300
mW
D
(Note 1) @ T = 25°C
A
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Junction and Storage Temperature Range T , T
J
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2014 − Rev. 1
ESD7421/D
ESD7421, SZESD7421
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR2 RWM
V
Clamping Voltage @ I
V
C
V
C
PP
V
I
V
V
V
R
T
RWM BR1 C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Breakdown Voltage @ I
Test Current
BR1
BR2
T
T
I
PP
V
Bi−Directional TVS
I
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Reverse Working
Voltage
V
RWM
Pin 1 to GND
Pin 2 to GND
5
5
16
10
V
Breakdown Voltage
Breakdown Voltage
V
I = 1 mA, Pin 1 to GND
16.5
10.5
V
V
BR1
T
V
BR2
I = 1 mA, Pin 2 to GND
T
14
Reverse Leakage
Current
I
R
V
RWM
= 5 V, I/O Pin to GND
100
500
nA
Clamping Voltage
(Note 2)
V
IEC61000−4−2, 8 kV Contact
See Figures 2 and 3
C
C
Clamping Voltage TLP
(Note 3)
V
I
= 8 A
= 16 A
= −8 A
= −16 A
35
38.1
−21
V
PP
I
PP
I
PP
I
−29.5
PP
Junction Capacitance
C
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.3
0.6
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For test procedure see Figure 5 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
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2
ESD7421, SZESD7421
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−5 −4 −3
−2
−1
0
1
2
3
4
5
VBias (V)
Figure 1. Typical CV Characteristic Curve
Pin1 to GND (GND connected to Pin2)
120
100
80
20
0
−20
−40
−60
−80
60
40
20
−100
−120
0
−20
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125
150
TIME (ns)
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
Pin1 to GND (GND connected to Pin2)
Pin1 to GND (GND connected to Pin2)
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3
ESD7421, SZESD7421
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD7421, SZESD7421
−20
−18
−16
−14
−12
−10
−8
20
18
16
14
12
10
8
−6
6
4
−4
2
0
−2
0
0
−5
−10
−15
−20
−25
−30
−35
0
5
10
15
20
25
30
35
40
45
VOLTAGE (V)
VOLTAGE (V)
Figure 6. Positive TLP IV Curve
Figure 7. Negative TLP IV Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns.
0
p
r
1
2
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD7421, SZESD7421
PACKAGE DIMENSIONS
XDFN2 1.0x0.6, 0.65P (SOD−882)
CASE 711AM
ISSUE O
NOTES:
0.10
C
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
A B
E
D
PIN 1
INDICATOR
MILLIMETERS
DIM MIN
MAX
0.44
0.05
0.53
A
A1
b
0.34
−−−
0.43
0.05
C
TOP VIEW
D
E
e
1.00 BSC
0.60 BSC
0.65 BSC
NOTE 3
A
0.10
0.10
C
L
0.20
0.30
C
A1
SEATING
PLANE
RECOMMENDED
C
SIDE VIEW
SOLDER FOOTPRINT*
1.20
e
2X
0.60
2X
0.47
b
e/2
M
0.05
C A B
PIN 1
1
DIMENSIONS: MILLIMETERS
2X
L
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
M
0.05
C A B
BOTTOM VIEW
ON Semiconductor and
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ESD7421/D
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